KR100590061B1 - Gray-scale current generating circuit, display device using the same, and display panel and driving method thereof - Google Patents

Abstract

The present invention relates to a gradation current generating circuit, a display device using the same, a display panel, and a driving method thereof. According to an exemplary embodiment of the present invention, a display device includes a display unit including a plurality of data lines for transmitting a data current, a plurality of scan lines for transmitting a selection signal, and a plurality of pixel regions defined by the data lines and the scan lines, and a plurality of gray scale data. A data driver converting current into a data line and sequentially applying a selection signal to the plurality of scan lines, wherein the data driver inputs a plurality of different first currents to correspond to grayscale data. And a plurality of digital / analog converter groups for outputting a digital signal, wherein the digital / analog converter group includes a first digital / analog converter for inputting a first current and outputting a data current corresponding to grayscale data; Second digital inputting a first voltage to output a data current corresponding to the grayscale data Includes an analog converter.

Gray current generator, current sample / hold circuit, bias current, digital / analog converter, data driver

Description

Gradient current generation circuit, display device using same, display panel and driving method thereof {GRAY-SCALE CURRENT GENERATING CIRCUIT, DISPLAY DEVICE USING THE SAME, AND DISPLAY PANEL AND DRIVING METHOD THEREOF}

1 is a plan view schematically illustrating an organic EL display device according to an exemplary embodiment of the present invention.

2 is a block diagram illustrating a data driver according to an exemplary embodiment of the present invention.

3 is a block diagram illustrating a gradation current generating unit according to a first embodiment of the present invention.

4 exemplarily shows a current sample / hold circuit used in the digital-to-analog converter DAC1 of FIG. 3.

FIG. 5 illustrates in more detail a digital / analog converter according to a first embodiment of the present invention.

6 is a block diagram illustrating a gray scale current generator according to a second exemplary embodiment of the present invention.

FIG. 7 exemplarily illustrates a current sample / hold circuit used in the digital-to-analog converter DAC2 of FIG. 6.

8 is a circuit diagram illustrating a digital / analog converter group according to a second embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a gradation current generating circuit, an organic electroluminescent display using the same, and a display panel and a driving method thereof.

In general, an organic EL display device is a display device that electrically excites a fluorescent organic compound to emit light, and is capable of displaying an image by voltage or current writing N × M organic light emitting cells. The organic light emitting cell has a structure of an anode (ITO), an organic thin film, and a cathode layer (metal). The organic thin film has a multilayer structure including an emitting layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL) to improve the emission efficiency by improving the balance between electrons and holes. It also includes a separate electron injecting layer (EIL) and a hole injecting layer (HIL).

The organic light emitting cell may be driven using a simple matrix method and an active matrix method using a thin film transistor (TFT) or a MOSFET. In the simple matrix method, the anode and the cathode are orthogonal and the line is selected and driven, whereas the active driving method connects the thin film transistor and the capacitor to each indium tin oxide (ITO) pixel electrode to maintain the voltage by the capacitor capacitance. It is a driving method. In this case, the active driving method is divided into a voltage programming method and a current programming method according to the type of signal applied to maintain the voltage on the capacitor.

However, in the conventional pixel circuit of the voltage write method, there is a problem in that it is difficult to obtain a high gradation due to variations in the threshold voltage V _TH of the thin film transistor and the mobility of the carrier caused by the nonuniformity of the manufacturing process. On the contrary, in the pixel circuit of the current write method, if the current source for supplying the current to the pixel circuit is uniform through the panel, even if the driving transistors in each pixel have non-uniform voltage-current characteristics, uniform display characteristics can be obtained.

When a display device is implemented using such a current write type pixel, a gray scale current generation circuit for converting gray scale data into gray scale current and applying the same to a pixel is required.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a gradation current generation circuit capable of outputting a gradation current corresponding to gradation data, a display device using the same, a display panel, and a driving method thereof.

According to an aspect of the present invention, a display device includes a plurality of data lines for transmitting a data current, a plurality of scan lines for transmitting a selection signal, and a plurality of pixels defined by the data lines and the scan lines, respectively. A display unit including an area; A data driver converting a plurality of grayscale data into the data current and applying the same to the data line; And a scan driver for sequentially applying the selection signal to the plurality of scan lines, wherein the data driver inputs a plurality of different first currents to output the data currents corresponding to the grayscale data. An analog converter group, wherein the digital / analog converter group includes a first digital / analog converter configured to input the first current to output the data current corresponding to the grayscale data, and a first corresponding to the first current; And a second digital / analog converter configured to input a voltage to output the data current corresponding to the grayscale data.

According to another aspect of the present invention, a display device includes: a display unit including a plurality of data lines for transmitting a data current, a plurality of scan lines for transmitting a selection signal, and a plurality of pixel regions defined by the data lines and the scan lines; A first shift register configured to sequentially delay the first signal by a first period to generate a plurality of second signals; A first latch configured to latch and output a plurality of gray scale data in synchronization with the second signal; A gradation current generation unit configured to input the plurality of gradation data to output the data current corresponding to the gradation data; And an output unit for applying the data current output from the gradation current generator to the plurality of data lines, wherein the gradation current generator includes a bias current generator for generating a plurality of different bias currents and the plurality of biases. And a plurality of digital / analog converter groups configured to sequentially input current to output the data current corresponding to the grayscale data, wherein the digital / analog converter group inputs the bias current to the data corresponding to the grayscale data. And a second digital / analog converter configured to output a current, and a second digital / analog converter configured to input a first voltage corresponding to the bias current to output the data current corresponding to the grayscale data.

According to an aspect of the present invention, a display panel includes: a display unit including a plurality of pixels to display an image in response to an applied data current; A first current generator configured to generate a plurality of different first currents; A plurality of first sample / hold circuits for storing a first voltage corresponding to the first current and outputting a second current corresponding to the first voltage in response to first grayscale data; And a plurality of second samples / holds configured to copy the first current to store a second voltage corresponding to the first current, and output a third current corresponding to the second voltage in response to second grayscale data. It includes a circuit.

A gradation current generation circuit according to an aspect of the present invention is a gradation current generation circuit for converting and outputting a plurality of digital gradation data including first and second gradation data into first and second gradation currents, respectively. A first current generator configured to output different first currents; A plurality of first sample / hold circuits each sampling the first current and outputting a second current corresponding to the sampled data in response to each bit data of the first grayscale data; And a plurality of second sample / hold circuits configured to copy the first current and output a third current corresponding to the copied first current in response to each bit data of the second grayscale data.

A driving method according to an aspect of the present invention is a driving method for driving a display panel in which a plurality of pixels are formed to display an image in response to an applied data current, wherein the plurality of different first currents are sampled. A first step of storing a plurality of first voltages respectively corresponding to currents; A second step of copying the first current to store a plurality of second voltages respectively corresponding to the first current; A third step of outputting a plurality of second currents respectively corresponding to the first voltage in response to first gray level data indicating a gray level of a first pixel among the plurality of pixels; A fourth step of outputting a plurality of third currents respectively corresponding to the second voltages in response to second gray level data indicating a gray level of a second pixel among the plurality of pixels; And a fifth step of applying the second and third currents to the first and second pixels, respectively.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the following description, when a part is connected to another part, this includes not only a case in which the part is directly connected, but also a case in which another part is electrically connected in between. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

A display device and a driving method thereof according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings. In the embodiment of the present invention, an organic electroluminescence (hereinafter referred to as "organic EL") display device using electroluminescence of an organic material as a display device will be described as an example.

1 is a plan view schematically illustrating an organic EL display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, an organic EL display device according to an exemplary embodiment of the present invention includes a substrate 1000 for forming a display panel, and the substrate 1000 includes a display unit 100 on which an actual image is displayed. It includes a peripheral portion where an image is not displayed. The data driver 200 and the scan drivers 300 and 400 are formed in the peripheral portion.

The display unit 100 includes a plurality of data lines D1 to Dm, a plurality of selected scan lines S1 to Sn, a plurality of light emitting scan lines E1 to En, and a plurality of pixels 110. The data lines D1 to Dm extend in the column direction, and transfer data current representing an image to the pixel. The selection scan lines S1 to Sm and the emission scan lines E1 to En extend in the row direction and transmit the selection signal and the emission signal to the pixels, respectively. The pixel area is defined by one data line and one selection scan line.

The data driver 200 applies a data current to the data lines D1 to Dm. The scan driver 300 sequentially applies selection signals to the plurality of selection scan lines S1 to Sn, and the scan driver 400 sequentially applies emission signals to the plurality of emission scan lines E1 to En.

The data driver and / or scan driver 300 or 400 may be directly mounted on the substrate 1000 in the form of an integrated circuit. Alternatively, the drivers 200, 300, and / or 400 may be formed on the substrate 1000 by the same layers as the layers forming the data lines D1 to Dm, the scan lines S1 to Sn, E1 to En, and the transistors of the pixel circuit. It may be formed. Alternatively, the driving units 200, 300, and / or 400 may be formed on a substrate separate from the substrate 1000 to electrically connect these substrates to the substrate 1000, and may be bonded to the substrate 1000 and electrically connected to the substrate 1000. The chip may be mounted in a tape carrier package (TCP), a flexible printed circuit (FPC), or a tape automatic bonding (TAB).

2 is a block diagram illustrating a data driver 200 according to an embodiment of the present invention.

As shown in FIG. 2, the data driver 200 according to an exemplary embodiment includes a shift register 210, a latch 220, a gray current generator 230, and an output unit 240. .

The shift register 210 sequentially shifts and outputs the start signal SP in synchronization with the clock signal Clk. The latch 220 latches and outputs an image signal in synchronization with the output signal of the shift register 210.

The gray current generator 230 inputs an image signal output from the latch 220 to generate gray currents I _{D1 to} I _Dm corresponding to the image signals.

The output unit 240 applies the gradation currents I _{D1 to} I _Dm output from the gradation current generating unit 230 to the data lines D1 to Dm. The output unit 240 may be formed as a buffer circuit connected between the output terminal of the gray scale current generator 230 and the data lines D1 to Dm, respectively.

Hereinafter, the gradation current generating unit according to the first embodiment of the present invention will be described with reference to FIGS. 3 to 5. In the following description, it is assumed that the image signal is 6-bit grayscale data for convenience of description.

3 is a block diagram illustrating a gray current generator 230 according to a first embodiment of the present invention.

As shown in FIG. 3, the gray scale current generator 230 according to the first exemplary embodiment of the present invention includes a shift register 231, a bias current generator 232, and digital / analog converters DAC1 to DACm. do.

The shift register 231 sequentially processes the start signal (not shown) in synchronization with the clock signal (not shown) so that each of the digital / analog converters DAC1 to DACm sequentially inputs the bias currents I _{B1 to} I _B6 . Shift to.

The bias current generator 232 generates bias currents I _{B1 to} I _B6 corresponding to the number of bits of the gray scale data and outputs them to the digital / analog converters DAC1 to DACm. According to one embodiment of the invention, the bias current I _B2 is set to be substantially twice the bias current I _B1 , and the bias currents I _{B3 to} I _B6 are each substantially equal to the bias current I _B1 . 4 times, 8 times, 16 times, and 32 times.

The digital / analog converters DAC1 to DACm convert the grayscale data into analog currents Iout1 to Ioutm in synchronization with the output signals SR1 to SRm of the shift register 231. Each digital-to-analog converter DAC1 to DACm includes a current sample / hold circuit corresponding to the number of bits of the gray scale data. Six current sample / hold circuits included in one digital / analog converter sample / hold the bias currents I _{B1 to} I _B6 , respectively, and output currents sampled / hold in response to each bit of the gray scale data.

4 illustrates a current sample / hold circuit according to a first embodiment of the present invention, and illustrates a current sample / hold circuit for sampling / holding a current corresponding to a first bit of grayscale data.

As shown in FIG. 4, the current sample / hold circuit according to the first embodiment of the present invention includes a transistor M11, a capacitor C11, and switching elements SW11 to SW13.

The transistor M11 is formed of a MOS transistor having a P-type channel, and a source thereof is connected to the power supply voltage VDD. The capacitor C11 is connected between the gate and the source of the transistor M11.

The switching element SW11 is connected between the drain and the gate of the transistor M11 and is turned on in response to the output signal SR1 of the shift register 231.

The switching element SW12 is connected between the output terminal of the bias current generator 232 and the drain of the transistor M11 and turned on in response to the output signal SR1 of the shift register 231.

The switching element SW13 is connected between the drain of the transistor M11 and the output terminal of the digital / analog converter DAC1 and is turned on in response to the first bit of the grayscale data.

Thus, when the output signal SR1 is input from the shift register 321, the switching element SW11 is turned on, the transistor M11 is diode-connected, and the switching element SW12 is turned on so that the bias current I _B1 is turned on. Delivered to M11. Therefore, the voltage corresponding to the bias current I _B1 is stored in the capacitor C11.

Thereafter, grayscale data is applied to the switching element SW13, and when the first bit of the grayscale data is 1, the switching element SW13 is turned on. Then, a current corresponding to the voltage stored in the capacitor C11 flows to the output terminal of the digital / analog converter DAC1 through the transistor M11. When the first bit of the gray scale data is 0, the switching element SW13 is turned off and the current from the transistor M11 is cut off.

Such a current sample / hold circuit is formed by the number of bits of the gray scale data, and the first to sixth bits of the gray scale data are applied to the switching element SW13 of each current sample / hold circuit to thereby correspond to the 6-bit gray scale data. The gradation currents I _{D1 to} I _Dm can be output.

FIG. 5 illustrates a digital / analog converter according to a first embodiment of the present invention, and representatively illustrates a digital / analog converter DAC1 among the plurality of digital / analog converters DAC1 to DACm.

The digital / analog converter DAC1 according to an embodiment of the present invention includes six current sample / hold circuits, each of the current sample / hold circuits sampling / holding the bias currents I _{B1 to} I _B6 and adjusting the gray level. In response to each bit of data, the bias currents I _{B1 to} I _B6 are output to the output terminal.

Specifically, when the output signal SR1 is applied from the shift register 321, the switching elements SW11 to SW16 of the six current sample / hold circuits are turned on to diode-connect the transistors M11 to M61, and the switching element ( SW12 to SW62 are turned on so that the bias currents I _{B1 to} I _B6 flow through the transistors M11 to M61. Therefore, voltages corresponding to the bias currents I _{B1 to} I _B6 are stored in the capacitors C11 to C61, respectively.

When each bit of the gray scale data is applied to the switching elements SW13 to SW63 of the six current sample / hold circuits, the current sample / hold circuit corresponds to the voltage stored in the capacitors C11 to C61 in response to the gray scale data. Output to the output.

For example, when the gray scale data is (001010), the switching elements SW23 and SW43 of the second and fourth current sample / hold circuits on the left side of FIG. 5 are turned on to correspond to voltages stored in the capacitors C21 and C41. (Iout1 [1], Iout1 [4]) is output.

Then, while the output signals SR1 to SRm are sequentially applied from the shift register 231 to the plurality of digital / analog converters DAC1 to DACm, the corresponding grayscale data is applied to the digital / analog converters DAC1 to DACm. The digital / analog converters DAC1 to DACm sequentially output currents Iout1 to Ioutm corresponding to the gray scale data in synchronization with the output signals SR1 to SRm of the shift register 231.

In addition, the digital-to-analog converter according to an embodiment of the present invention generates six bias currents I _{B1 to} I _B6 corresponding to each bit of the gray scale data in the bias current generator 232 as described above. Output to two current sample / hold circuits. Therefore, compared to the case of holding a plurality of different currents by inputting one bias voltage or current, it is possible to prevent the variation of the holding current due to the characteristics of the transistors M11 to M61.

That is, by using one bias voltage or current and controlling the width and length of the channels of the transistors M11 to M61 included in each current sample / hold circuit, each current sample / hold circuit samples / holds different currents. In this case, however, a problem may occur in which a desired current is not held due to variations of the transistors M11 to M61.

Therefore, in an embodiment of the present invention, the characteristics of the transistors M11 to M61 included in each current sample / hold circuit are set to be substantially the same, and the bias current generator 232 generates a plurality of bias currents to generate current. By transferring each to the sample / hold circuit, variations in current caused by the transistors M11 to M61 can be prevented.

However, the gradation current generator 230 according to the first embodiment of the present invention generates the bias currents I _{B1 to} I _B6 in the bias current generator 232 and sequentially performs the digital current to the digital / analog converters DAC1 to DACm. Since it should be applied as, the sampling period allocated to each of the digital / analog converters DAC1 to DACm is very short. That is, while the selection signals are sequentially applied to the scan lines S1 to Sn, the output unit 233 must apply data currents to the m data lines D1 to Dm, and thus all digital / analog converters within the horizontal period. There was a burden that (DAC1-DACm) samples / holds the bias currents I _B1 -I _B6 and outputs a gradation current corresponding to the gradation data to the output unit 233.

Therefore, the problem in which the current sample / hold circuits included in the digital / analog converters DAC1 to DACm hold the current in a state in which the voltage corresponding to the bias currents I _{B1 to} I _B6 is not sufficiently charged. Was generated.

In order to overcome this problem, the gradation current generator 230 according to the second embodiment of the present invention divides the digital / analog converters DAC1 to DACm into a plurality of groups and includes the digital / analog converters included in one group. Ensures the sampling time by performing the sampling operation substantially simultaneously.

Hereinafter, the gray scale current generator 230 according to the second exemplary embodiment of the present invention will be described with reference to FIGS. 6 to 8.

FIG. 6 is a block diagram illustrating a gray current generator 230 according to a second embodiment of the present invention.

As shown in FIG. 6, the gradation current generator 230 according to the second embodiment of the present invention divides the plurality of digital / analog converters DAC1 to DACm into at least two groups to transfer bias currents. It is different from the gradation current generator according to the first embodiment of the present invention.

The output signals SR1 to SRi of the shift register 231 are applied to any one of the plurality of digital / analog converters included in each group, and the bias currents I _{B1 to} I _B6 are applied to the shift register 231. The output signal is supplied to the applied digital / analog converter.

That is, when two digital / analog converters are set to one group 234 as shown in FIG. 6, the output signals SR1 to SRi of the shift register 231 are the first digital / analog converter DAC included in each group. may be applied to _2i~1), the D / a converter (DAC _2i-1) is the bias current (I _B1 ~I _B6) the input, the D / a converter (DAC _2i) is (I _B1 bias current ~ Input the voltage corresponding to I _B6 ).

As a result, the enable period of the output signals SR1 to SRi of the shift register 231 is substantially doubled as compared to the output signals SR1 to SRm of the shift register according to the first embodiment of the present invention. The sampling period of the bias currents I _{B1 to} I _B6 of the converters DAC1 to DACm is doubled.

Hereinafter, the configuration and operation of the digital / analog converter of the gradation current generator 230 according to the second embodiment of the present invention will be described in more detail. However, for convenience of description, one digital / analog group includes two digital / analog converters, and centers the digital / analog converters DAC1 to DAC2 included in the first group of the plurality of digital / analog groups. This will be described.

According to the second embodiment of the present invention, the digital / analog converter DAC1 includes six current sample / hold circuits, and one current sample / hold circuit is formed substantially the same as in FIG. 4.

That is, the current sample / hold circuit of the digital-to-analog converter DAC1 includes a transistor M11, a capacitor C11, and switching elements SW11 to SW13. The switching elements SW11 and SW12 are turned on by the output signal SR1 of the shift register 231, and the capacitor C11 stores a voltage corresponding to the bias current flowing through the transistor M11. The switching element SW13 is turned on in response to the gray scale data, and when the switching element SW13 is turned on, a current corresponding to the voltage stored in the capacitor C11 is output to the output terminal of the digital / analog converter DAC1.

The digital / analog converter (DAC2) also includes six current sample / hold circuits, each of which copies the bias current flowing through the current sample / hold circuit of the digital / analog converter (DAC1) to the bias current. Save the corresponding voltage.

FIG. 7 shows a current sample / hold circuit of a digital-to-analog converter DAC2 according to a second embodiment of the present invention, and shows a current sample / hold circuit holding a current corresponding to the first bit of grayscale data. It is.

As shown in FIG. 7, the current sample / hold circuit of the digital-to-analog converter DAC2 includes a transistor M12, a capacitor C12, and a switching element SW14.

The transistor M11 has a gate connected to the gate of the transistor M11 (not shown), and a source connected to the power supply VDD. A capacitor C12 is connected between the gate and the source of the transistor M11, and the capacitor C12 stores a voltage corresponding to the current flowing in the transistor M11.

The switching element SW14 is connected to the drain of the transistor M12 and is turned on in response to the first bit of the grayscale data.

With such a configuration, a voltage substantially equal to the voltage applied to the gate of the transistor M11 is applied to the gate of the transistor M12, and thus a current substantially equal to the bias current IB1 flowing through the transistor M11. Flows through the transistor M12.

Therefore, the voltage corresponding to the current flowing in the transistor M12 is charged in the capacitor C12. When the switching element SW14 is turned on in response to the first bit of the gray scale data, a current corresponding to the voltage stored in the capacitor C14 is output through the switching element SW14.

When the current sample / hold circuit included in the digital / analog converter DAC2 is connected to the current sample / hold circuit included in the digital / analog converter DAC1, the digital / analog converters DAC1 and DAC2 are substantially simultaneously. Sampling / holding operation of the bias current is performed.

As a result, the plurality of current sample / hold circuits included in one group performs the sampling / holding operation substantially simultaneously, and outputs the sampled current in response to the applied grayscale data. In this case, the gray scale data may be sequentially applied to two digital / analog converters DAC1 and DAC2 or simultaneously.

8 is a circuit diagram illustrating digital / analog converters DAC1 and DAC2 included in one group according to the second embodiment of the present invention.

As shown in FIG. 8, bias currents I _{B1 to} I _B6 are applied to each current sample / hold circuit of the digital / analog converter DAC1, and transistors M12 to M62 of the digital / analog converter DAC2. Is connected to the gates of the transistors M11 to M61 of the digital-to-analog converter DAC1.

Therefore, the plurality of digital / analog converters DAC _2i-1 and DAC _2i included in one group sample the bias currents I _{B1 to} I _B6 at substantially the same time, thereby increasing the sampling period of the current sample / hold circuit. do. In addition, the bias current generator 232 may sequentially reduce the deviation between the bias currents supplied to the digital / analog converters DAC1 to DACm by sequentially transmitting bias currents to the groups.

That is, when the bias current is supplied to only one digital / analog converter DAC1 to DACm and the voltage corresponding to the bias current is supplied to the remaining digital / analog converters DAC2 to DACm, the transistor included in the current sample / hold circuit. The deviation between the bias currents supplied to the digital-to-analog converters DAC1 to DACm becomes large due to the characteristic deviation of.

Therefore, by appropriately adjusting the number of digital / analog converters included in one group, it is possible to reduce the deviation between the bias currents supplied to each digital / analog converter while ensuring the sampling period of the current sample / hold circuit.

As described above, the gradation current generating circuit for generating the gradation current, the display device using the same, the display panel, and the driving method thereof have been described. The above-described embodiment is an embodiment to which the concept of the present invention is applied, and the scope of the present invention is not limited to the above embodiment, and various modified embodiments may be formed using the concept of the present invention.

For example, although the circuits shown in FIGS. 4 and 7 are used as the current sample / hold circuits included in the digital / analog converter, the scope of the present invention is not limited to a specific current sample / hold circuit, and the output signal of the shift register is used. The current sample / hold circuit of various types that can sample the bias current and output the sampled current in response to the gray scale data, and the current flowing to other current sample / hold circuits are copied in response to the gray scale data. Many types of current sample / hold circuits are available that can output current.

4 to 8 illustrate that the transistors of the current sample / hold circuit are formed of MOS transistors having P-type channels, the transistors may be formed of MOS transistors having N-type channels. It may be formed using another active element having three electrodes and outputting a current corresponding to the voltage applied between the two electrodes to the other electrode.

According to the present invention, a gradation current generation circuit capable of outputting a gradation current corresponding to gradation data, a display device using the same, a display panel, and a driving method thereof can be provided.

In addition, by generating a plurality of different bias currents and applying the plurality of bias currents to the plurality of current sample / hold circuits, the variation of the holding current due to the variation of the transistors used in the current sample / hold circuit can be reduced.

Furthermore, the sampling period of the current sample / hold circuit included in the digital / analog converter by dividing the plurality of digital / analog converters into a plurality of groups and allowing the digital / analog converter included in one group to sample the bias current substantially simultaneously. Can be secured.

Claims (20)

A display unit including a plurality of data lines for transmitting a data current, a plurality of scanning lines for transmitting a selection signal, and a plurality of pixel regions respectively defined by the data lines and the scanning lines; A data driver converting a plurality of grayscale data into the data current and applying the same to the data line; And A scan driver for sequentially applying the selection signal to the plurality of scan lines; The data driver includes a plurality of digital / analog converter groups for inputting a plurality of different first currents to output the data currents corresponding to the grayscale data. The digital / analog converter group may include a first digital / analog converter configured to input the first current to output the data current corresponding to the grayscale data, and a first voltage corresponding to the first current to input the grayscale data. And a second digital / analog converter configured to output the data current corresponding to the data current. The method of claim 1, And the data driver includes a shift register configured to sequentially delay the first signal by a first period to generate a plurality of second signals. The method of claim 2, The first digital-to-analog converter is configured to sample / hold the first current to store a second voltage corresponding to the first current, and output a second current corresponding to the second voltage in response to the grayscale data. A display device comprising a plurality of first sample / hold circuits. The method of claim 3, The first sample / hold circuit is, A first transistor having first to third electrodes and outputting a current corresponding to a voltage applied between the first and second electrodes to the third electrode, A first switching element diode-connecting the first transistor in response to the second signal; A second switching element transferring the first current to the first transistor in response to the second signal; A first capacitor storing the second voltage corresponding to the first current, and And a third switching device configured to output the second current corresponding to the second voltage in response to the grayscale data. The method according to any one of claims 1 to 4, The second digital to analog converter stores a third voltage corresponding to the first current, and outputs a third current corresponding to the third voltage in response to the grayscale data. Display device including. The method of claim 5, The second sample / hold circuit is, A first electrode, a second electrode, and a third electrode connected to the first electrode of the first transistor, and output a current corresponding to a voltage applied between the first and second electrodes to the third electrode A second transistor, A capacitor connected between the first and second electrodes of the second transistor and storing the third voltage corresponding to the first current, and And a fourth switching element configured to output the third current corresponding to the voltage stored in the capacitor in response to the gray scale data. The method of claim 5, The number of the first and second sample / hold circuits is substantially the same as the number of bits of the grayscale data, And the first and second sample / hold circuits respectively output the second and third currents in response to data of each bit of the grayscale data. A display unit including a plurality of data lines for transmitting a data current, a plurality of scanning lines for transmitting a selection signal, and a plurality of pixel regions respectively defined by the data lines and the scanning lines; A first shift register configured to sequentially delay the first signal by a first period to generate a plurality of second signals; A first latch configured to latch and output a plurality of gray scale data in synchronization with the second signal; A gradation current generation unit configured to input the plurality of gradation data to output the data current corresponding to the gradation data; And An output unit for applying the data current output from the gradation current generation unit to the plurality of data lines, The gray current generator includes a bias current generator for generating a plurality of different bias currents and a plurality of digital / analog converter groups for sequentially inputting the plurality of bias currents to output the data current corresponding to the gray data. , The digital / analog converter group may include a first digital / analog converter configured to input the bias current to output the data current corresponding to the grayscale data, and a first voltage corresponding to the bias current to correspond to the grayscale data. And a second digital / analog converter for outputting the data current. The method of claim 8, The gray level current generator further includes a second shift register configured to sequentially delay the third signal by a second period to generate a plurality of fourth signals. And the first digital to analog converter inputs the bias current in response to the fourth signal. The method of claim 9, The first digital-to-analog converter includes a plurality of first sample / hold circuits for sampling a bias current in response to the fourth signal and outputting the sampled current in response to the gradation data; The second digital-to-analog converter includes a plurality of second sample / hold circuits that input the first voltage corresponding to the bias current and output a current corresponding to the first voltage in response to the grayscale data. Display device. A display unit including a plurality of pixels for displaying an image in response to an applied data current; A first current generator configured to generate a plurality of different first currents; A plurality of first sample / hold circuits storing a first voltage corresponding to the first current and outputting a second current corresponding to the first voltage in response to first grayscale data; And A plurality of second sample / hold circuits configured to copy the first current to store a second voltage corresponding to the first current, and output a third current corresponding to the second voltage in response to second grayscale data; Display panel comprising a. The method of claim 11, And a shift register configured to sequentially delay the first signal by a first period to generate a plurality of second signals. The method of claim 12, The first sample / hold circuit stores the first voltage corresponding to the first current in response to the second signal. A gradation current generation circuit for converting a plurality of digital gradation data including first and second gradation data into first and second gradation currents and outputting the gradation current, respectively, A first current generator configured to output a plurality of different first currents; A plurality of first sample / hold circuits each sampling / holding the first current and outputting a second current corresponding to the sampled / holding data in response to each bit data of the first grayscale data; And A plurality of second sample / hold circuits configured to copy the first current and output a third current corresponding to the copied first current in response to each bit data of the second grayscale data; Gray current generating circuit comprising a. The method of claim 14, And the number of the first and second sample / hold circuits is substantially the same as the number of bits of the first and second gray level data, respectively. The method according to claim 14 or 15, The first sample / hold circuit is, A first transistor having first to third electrodes and outputting a current corresponding to a voltage applied between the first and second electrodes to the third electrode, A first switching element diode-connecting the first transistor in response to the second signal; A second switching element transferring the first current to the first transistor in response to the second signal; A first capacitor storing a first voltage corresponding to the first current, and And a third switching device configured to output the second current corresponding to the first voltage in response to the grayscale data. The method of claim 16, The second sample / hold circuit is, A first electrode, a second electrode, and a third electrode connected to the first electrode of the first transistor, and output a current corresponding to a voltage applied between the first and second electrodes to the third electrode A second transistor, A capacitor connected between the first and second electrodes of the second transistor and storing a second voltage corresponding to the first current, and And a fourth switching element configured to output the third current corresponding to the voltage stored in the capacitor in response to the gray scale data. A driving method for driving a display panel in which a plurality of pixels for displaying an image in response to an applied data current is provided. Sampling a plurality of different first currents and storing a plurality of first voltages respectively corresponding to the first currents; A second step of copying the first current to store a plurality of second voltages respectively corresponding to the first current; A third step of outputting a plurality of second currents respectively corresponding to the first voltage in response to first gray level data indicating a gray level of a first pixel among the plurality of pixels; A fourth step of outputting a plurality of third currents respectively corresponding to the second voltages in response to second gray level data indicating gray levels of a second pixel of the plurality of pixels; And And a fifth step of applying the second and third currents to the first and second pixels, respectively. The method of claim 18, The third step outputs the second current corresponding to the first voltage in response to each bit data of the first grayscale data, The fourth step may include outputting the third current corresponding to the second voltage in response to each bit data of the second grayscale data. The method of claim 19, The number of different first currents is substantially the same as the number of bits of the first grayscale data, and the first current is a current corresponding to each bit of the grayscale data.

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