JP2006128600A - Solid-state imaging device and method of controlling thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make information charge to be ejected in the middle of vertical transfer. <P>SOLUTION: This solid imaging device is provided with a plurality of vertical shift registers which are arranged as columns parallel to each other in a vertical direction, crossing with a plurality of transfer electrodes 14-1 to 14-3, 34-1 to 34-3 to transfer the information charge in a vertical direction; first and second output gate electrodes 16 and 18 which are common in the respective columns of the plurality of vertical shift registers, and where an array order is inverted between an odd-numbered column and an even-numbered column; a third output gate electrode 30 arranged on an output side compared with the first and second output gate electrodes 16 and 18; and a fourth output gate electrode 32, arranged on the input side compared with the first and second output gate electrodes 16 and 18. An output control clock, controlled independently from a transfer clock pulse and an output control clock applied to the first to third output gate electrodes 16, 18 and 30 can be applied to at least one among the transfer electrodes 34-1 to 34-3, in common with fourth output gate electrode 32. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a CCD solid-state imaging device capable of discharging unnecessary information charges when information charges are vertically transferred and a control method thereof.

  FIG. 11 is a configuration diagram of a solid-state imaging device including a frame transfer type CCD solid-state imaging device. The frame transfer type CCD solid-state imaging device includes an imaging unit 2i, a storage unit 2s, a horizontal transfer unit 2h, and an output unit 2d. The imaging unit 2i includes a plurality of columns of vertical shift registers. The vertical shift register of the imaging unit 2i includes light receiving pixels arranged in a matrix that receives light from the outside and generates information charges in an amount corresponding to the intensity of the incident light. When a vertical clock pulse is input from the clock pulse generation unit 4 to the imaging unit 2i, information charges generated in each light receiving pixel are transferred to the storage unit 2s along the vertical shift register. In a CCD solid-state imaging device for color imaging, each light receiving pixel of the imaging unit 2i is covered with one of transmission filters corresponding to wavelengths of red (R), green (G), and blue (B), as shown in FIG. Thus, each transmission filter is arranged in a mosaic. That is, the information charges corresponding to red (R) and green (G) are alternately transferred in the odd columns of the vertical shift register, and the information charges corresponding to green (G) and blue (B) are transferred in the even columns of the vertical shift register. Are transferred alternately. The accumulating unit 2s includes a vertical shift register arranged continuously with the vertical shift register of the imaging unit 2i. The vertical shift register of the storage unit 2s is shielded from light and is used to store information charges for one frame. The vertical clock pulse and the output control clock are input from the clock pulse generator 4 to the accumulator 2s. By applying the vertical clock pulse and the output control clock, the information charges held in the storage unit 2s are transferred and output to the horizontal transfer unit 2h line by line. The horizontal transfer unit 2h includes a horizontal shift register. Information charges for one pixel are sequentially transferred and output from each vertical shift register of the storage unit 2s to each bit of the horizontal shift register of the horizontal transfer unit 2h. A horizontal clock pulse is input from the clock pulse generator 4 to the horizontal transfer unit 2h. The horizontal transfer unit 2h receives a horizontal clock pulse and transfers information charges to the output unit 2d in units of pixels. The output unit 2d converts the information charge amount for each pixel into a voltage value, and the change in the voltage value is used as the CCD output.

  FIG. 12 shows a plan view of a part of the internal structure of the storage unit 2s and the horizontal transfer unit 2h. The storage unit 2s includes a plurality of vertical shift registers extending in parallel with each other. The vertical shift register can be formed as follows. A P well (PW) which is a P type diffusion layer is formed in an N type semiconductor substrate, and an N well which is an N type diffusion layer is formed thereon. In addition, isolation regions 10 to which P-type impurities are added are provided in parallel to each other at a predetermined interval along the extending direction of the vertical shift register. Therefore, the N well is electrically partitioned by the adjacent isolation region 10. A region sandwiched between the isolation regions 10 becomes a channel region 12 which is a transfer path of information charges. The isolation region 10 forms a potential barrier between adjacent channel regions 12 to electrically isolate each channel region 12. Further, an insulating film is formed on the surface of the semiconductor substrate. A plurality of transfer electrodes 14 made of a polysilicon film are arranged in parallel to each other so as to be orthogonal to the extending direction of the channel region 12 with the insulating film interposed therebetween. A set of three adjacent transfer electrodes 14-1, 14-2, and 14-3 constitutes one pixel. The vertical shift register of the imaging unit 2i can be configured in the same manner, and is arranged to be continuous with each vertical shift register of the storage unit 2s.

  The first output gate electrode 16 is arranged in parallel with the transfer electrode 14 on the output side of the vertical shift register so as to meander away from the channel region 22 in the odd columns and approach the channel region 22 in the even columns. Contrary to the first output gate electrode 16, the second output gate electrode 18 meanders so as to approach the channel region 22 in the odd-numbered columns and away from the channel region 22 in the even-numbered columns, and on the isolation region 10. One output gate electrode 16 is arranged so as to intersect with an insulating film. The third output gate electrode 20 is disposed further on the output side than the first output gate electrode 16 and the second output gate electrode 18. The third output gate electrode 20 is arranged so as to be close to the first output gate electrode 16 in the odd-numbered column and to overlap the second output gate electrode 18 via the insulating film in the even-numbered column.

  The horizontal transfer unit 2h includes a horizontal shift register that receives and transfers information charges output from the vertical shift register of the storage unit 2s. The horizontal shift register includes a channel region 22 and horizontal transfer electrodes 24-1 and 24-2. The channel region 22 is formed with respect to the extending direction of the vertical shift register by the separation region 10 extending from the vertical shift register of the storage unit 2s and the horizontal isolation region 26 which is a P-type diffusion layer provided facing the storage unit 2s. Are partitioned in directions perpendicular to each other. The channel region 12 of the vertical shift register and the channel region 22 of the horizontal shift register are continuously arranged with a gap between the extended separation regions 10. The first horizontal transfer electrode 24-1 is disposed on the semiconductor substrate via an insulating film on the extension of the channel region 12 of the vertical shift register. The second horizontal transfer electrode 24-2 covers the gap of the first horizontal transfer electrode 24-1, and a part of the second horizontal transfer electrode 24-2 overlaps the first horizontal transfer electrode 24-1 with an insulating film interposed therebetween. 22 so as to intersect with 22.

Vertical clock pulses φs _{1 to} φs ₃ are applied to the transfer electrodes 14-1 to 14-3, respectively. Output control clocks TG1 and TG2 are applied to the first output gate electrode 16 and the second output gate electrode 18, respectively. Further, the vertical clock pulse φs ₁ applied to the transfer electrode 14-1 is applied to the third output gate electrode 20.

FIG. 13 shows a timing chart of the vertical clock pulses φs _{1 to} φs ₃ and the output control clocks TG 1 and TG 2 when information charges are vertically transferred. FIG. 14 shows the formation state of the potential wells under the transfer electrodes 14-1 to 14-3 and the first to third output gate electrodes 16, 18, 20 corresponding to each time of FIG. The state of is shown.

  In this way, by performing vertical transfer so that odd and even columns are alternately output to the horizontal shift register, mixing of information charges of different colors in color imaging is prevented, and bits of the horizontal shift register The number is reduced.

JP-A-8-139999

  When capturing an image with a low resolution, it is necessary to add and combine information charges corresponding to the same color in the vertical direction and the horizontal direction. However, in the above-described conventional CCD solid-state imaging device, information charges corresponding to the same color in the horizontal direction can be added and combined, but information charges corresponding to the same color in the vertical direction can be added and combined in the device. Could not do.

  Further, as shown in FIG. 10, even when only a part of an image captured by the imaging unit 2i (an area not hatched) is to be acquired, accumulation is performed in an unnecessary image area (an area indicated by hatching). It was impossible to cut out only the necessary image area by discarding the information charges that were being transferred.

  An object of the present invention is to provide a solid-state imaging device and a control method therefor that can discharge unnecessary information charges during vertical transfer in view of the above-described problems of the prior art.

  The present invention includes a plurality of transfer electrodes extending in the horizontal direction and arranged at a predetermined interval, arranged as a vertical column intersecting the plurality of transfer electrodes, and controlling transfer clock pulses applied to the transfer electrodes A solid-state imaging device having a plurality of vertical shift registers for transferring information charges in the vertical direction, provided on the output side of the vertical shift register, and common to each column of the plurality of vertical shift registers, and odd columns And the first and second output gate electrodes whose arrangement order is reversed between the even-numbered columns and the columns of the plurality of vertical shift registers, and are arranged on the output side from the first and second output gate electrodes. A third output gate electrode; and a fourth output gate electrode that is common to each column of the plurality of vertical shift registers and is arranged on the input side from the first and second output gate electrodes. , Each bit is associated with an output from the plurality of vertical shift registers, at least one of a plurality of transfer electrodes associated with at least one bit of the vertical shift register, and the fourth output gate electrode. An output control clock controlled independently of the transfer clock pulse and the output control clock applied to the first to third output gate electrodes can be applied in common.

  Specifically, an output control clock that is controlled independently of an output control clock applied to the third output gate electrode can be applied to the first and second output gate electrodes. .

  In the solid-state imaging device having such a configuration, information charges can be discharged during vertical transfer by changing an output control clock applied in common with the fourth output gate electrode. More specifically, the information charge is discharged during the vertical transfer by simultaneously turning off the output control clock and the transfer clock pulse applied in common with the fourth output gate electrode.

  In the solid-state imaging device having the above-described configuration, the storage positions of the information charges in the plurality of vertical shift registers are shifted by 1 bit between the odd and even columns, and the information charges are horizontally shifted from the odd and even columns of the vertical shift register. Can be output alternately.

  More generally, the present invention includes a plurality of transfer electrodes extending in the horizontal direction and arranged at a predetermined interval, arranged as a vertical column intersecting the plurality of transfer electrodes, and applied to the transfer electrodes. A solid-state imaging device having a plurality of vertical shift registers for transferring information charges in the vertical direction by controlling clock pulses, provided on the output side of the vertical shift register and common to each column of the plurality of vertical shift registers A plurality of middle-stage output gate electrodes and a plurality of vertical shift registers that are common to each column, a rear-stage output gate electrode disposed on the output side from the plurality of middle-stage output gate electrodes, and a plurality of vertical shift registers A pre-stage output gate electrode that is common to the column and disposed on the input side from the plurality of middle-stage output gate electrodes, and from the plurality of vertical shift registers Each bit is associated with a force, and at least one of a plurality of transfer electrodes associated with at least one bit of the vertical shift register and the previous output gate electrode, the transfer clock pulse and the middle output gate electrode An output control clock controlled independently from an output control clock applied to the output gate clock and an output control clock applied to the subsequent-stage output gate electrode can be applied in common.

  Here, it is preferable that an output control clock controlled independently of an output control clock applied to the subsequent output gate electrode can be applied to the plurality of middle output gate electrodes.

  Further, n intermediate output gate electrodes (where n is an integer equal to or greater than 2) are provided, and one set of adjacent n columns of vertical shift registers is used as one vertical shift register group. The information charge is selectively transferred from the shift register to the subsequent output gate electrode.

  Further, the information charge is discharged during the vertical transfer by changing an output control clock applied in common with the latter-stage output gate electrode.

  According to the present invention, unnecessary information charges can be discharged during the vertical transfer of information charges. As a result, information charges corresponding to the same color can be added and combined in the vertical direction when performing color imaging. Further, when the required image area is smaller than the standard size, unnecessary horizontal transfer processing and the like can be omitted, and the overall transfer speed can be improved.

<First Embodiment>
A CCD solid-state imaging device and a control method thereof according to the first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the solid-state imaging device in the present embodiment. Similar to the conventional CCD solid-state imaging device shown in FIG. 11, the CCD solid-state imaging device in the present embodiment includes an imaging unit 6i, a storage unit 6s, a horizontal transfer unit 6h, and an output unit 6d.

  The imaging unit 6i includes a plurality of columns of vertical shift registers. Each bit of each vertical shift register is associated with a light receiving pixel arranged in a matrix. As shown in FIG. 2, color filters that transmit red (R) and green (G) wavelength regions are alternately arranged in association with the respective light receiving pixels along the transfer direction of the odd-numbered vertical shift registers, Color filters that transmit blue (B) and green (G) wavelength regions are alternately arranged in correspondence with the respective light receiving pixels along the transfer direction of the even-numbered vertical shift registers. The imaging unit 6i receives a vertical clock pulse from the clock pulse generation unit 8, and performs imaging and information charge transfer according to the change of the vertical clock pulse.

  The accumulation unit 6s includes a vertical shift register that is continuous with the vertical shift register of the imaging unit 6i. A vertical clock pulse and an output control clock are input from the clock pulse generator 8 to the accumulator 6s. This embodiment is characterized by being controlled by a four-phase output control clock that can be controlled independently of the vertical clock pulse. By controlling the vertical clock pulse and the output control clock, the information charges stored in the storage unit 6s are transferred to the horizontal transfer unit 6h line by line.

  The horizontal transfer unit 6h includes a horizontal shift register having a number of bits corresponding to the number of columns of the vertical shift registers of the imaging unit 6i and the storage unit 6s. A horizontal clock pulse is input from the clock pulse generation unit 8 to the horizontal transfer unit 6h, and information charges are transferred to the output unit 6d in units of pixels. The output unit 6d converts the information charge amount for each pixel into a voltage value and outputs the voltage value.

  FIG. 3 is a plan view of the internal structure of the storage unit 6s and the horizontal transfer unit 6h, which are the main parts of the CCD solid-state imaging device in the present embodiment. In FIG. 3, the same components as those in the prior art are given the same reference numerals.

The configuration of the storage unit 6s and the horizontal transfer unit 6h of the CCD solid-state imaging device in the present embodiment is substantially the same as that of the above-described conventional technology, but the vertical clock pulses φs _{1 to} φs ₃ and the output control are applied to the third output gate electrode 30. An output control clock TG3 that can be controlled independently of the clocks TG1 and TG2 is applied. The third output gate electrode 30 in the present embodiment can be formed in the same manner as the conventional third output gate electrode 20. In addition, transfer electrodes 34-1 to 34-3 constituting pixels for one row are further provided at the final stage of the storage unit 6s, and the transfer electrodes 14-1 are continuously connected to the transfer electrodes 34-1 to 34-3. A fourth output gate electrode 32 is provided with the electrode interposed therebetween. Here, any one fourth output gate electrode 32 of the transfer electrodes 34-1～34-3 a vertical clock pulses φs ₁ ~φs ₃ and the output control clock TG1, TG2, TG3 controllable independently of the A common output control clock TG4 is applied.

FIG. 4 shows a timing chart of the vertical clock pulses φs _{1 to} φs ₃ and the output control clocks TG _{1 to} TG ₄ when performing vertical transfer without discharging information charges. 5 and 6 show transfer electrodes 14-1 to 14-3, 34-1 to 34-3, and first to fourth transfer electrodes 14-1 to 14-3, 34-1 to 34-3 corresponding to respective times in the odd-numbered column and even-numbered column vertical shift registers. The formation state of the potential well under the output gate electrodes 16, 18, 30, and 32 and the state of information charge transfer are shown. Information charges (R, G, B) corresponding to different wavelength components are distinguished from each other by using different hatching. The transfer electrodes 14-1 to 14-3, 34-1 and 34-3 and the output gate electrodes 16, 18, 30 and 32 are turned on when the applied clock pulse is at a high level (H), and the low level ( L).

At times t _{1 to} t ₁₄ , the information charges corresponding to the green (G) wavelength components in the odd-numbered columns, that is, the information charges stored on the side closest to the horizontal shift register are transferred and output to the horizontal transfer unit 6 h. The At times t _{1 to} t ₇ , control is performed in the same manner as at times t _{1 to} t ₇ in the conventional solid-state imaging device. At time t ₈ , the vertical clock pulse φs ₁ and the output control clock TG 4 are set to the low level (L) while the vertical clock pulses φs ₂ and φs ₃ and the output control clocks TG 1 and TG 2 are maintained at the high level (H). At time _{t 9,} the vertical clock pulses .phi.s _2, the output control clock TG1 while maintaining the .phi.s ₃ and the output control clock TG2 to the high level (H) and low level (L). At time _{t 10,} the vertical clock pulses .phi.s _2, maintaining .phi.s ₃ and the output control clock TG2 to the high level (H), to change the output control clock TG4 to the high level (H). At time t ₁₁ , the vertical clock pulses φs ₂ and φs ₃ and the output control clocks TG 2 and TG 4 are maintained at a high level (H), and the output control clock TG 3 is changed to a high level (H). At time _{t 12,} the vertical clock pulses .phi.s _2, maintaining .phi.s ₃ and the output control clock TG3, TG4 at the high level (H), to change the output control clock TG2 to the low level (L). Further, the horizontal clock pulse HS1 applied to the horizontal transfer electrodes 24-1 and 24-2 connected to the odd columns is set to the high level (H). At time _{t 13,} the vertical clock pulses φs _2, φs _3, to maintain the output control clock TG4 to the high level (H), the output control clock TG3 a low level (L). At time _{t 14,} to maintain a vertical clock pulses φs _2, φs _3, the output control clock TG4 to the high level (H), the output control clock TG2 and high level (H).

  As a result, the information charges accumulated in the potential wells below the transfer electrodes 14-1 to 14-3 and 34-1 to 34-3 other than the final stage in the odd column vertical shift register are held, and the even column vertical shift is performed. The transfer electrodes 34-1 to 34-3 and the output gate electrodes 16 and 18 are held while retaining the information charges accumulated in the potential wells below the transfer electrodes 14-1 to 14-3 and 34-1 to 34-3 in the register. , 30, and 32, information charges corresponding to green (G) in the odd-numbered columns can be transferred and output to the horizontal shift register. At time FH, the information charges transferred and output below the horizontal transfer electrodes 24-1 and 24-2 are horizontally transferred along the horizontal shift register.

At time t ₁₅ ~t _20, closest to the information charges to the horizontal shift register in the even-numbered columns, the information charges corresponding to the wavelength component of 6 blue (B), is transferred and output to the horizontal transfer portion 6h. At time t ₁₅ , the vertical clock pulses φs ₂ and φs ₃ and the output control clocks TG 1, TG 2, and TG 4 are set to the high level (H), and the vertical clock pulse φs ₁ and the output control clock TG 3 are set to the low level (L). . At time _{t 16,} the vertical clock pulses .phi.s _2, while maintaining the .phi.s ₃ and the output control clock TG1, TG2 to the high level (H), to change the output control clock TG4 to the low level (L). At time t ₁₇ , the output control clock TG 2 is changed to the low level (L) while maintaining the vertical clock pulses φs ₂ and φs ₃ and the output control clock TG 1 at the high level (H). At time _{t 18,} the vertical clock pulses .phi.s _2, while maintaining the .phi.s ₃ and the output control clock TG1 to the high level (H), the output control clock TG3, TG4 also changed to a high level (H). At time _{t 19,} the vertical clock pulses .phi.s _2, while maintaining the .phi.s ₃ and the output control clock TG3, TG4 at the high level (H), to change the output control clock TG1 to the low level (L). Further, the horizontal clock pulse HS2 applied to the horizontal transfer electrodes 24-1 and 24-2 connected to the even columns is changed to a high level (H). At time _{t 20,} the vertical clock pulses .phi.s _2, while maintaining the .phi.s ₃ and the output control clock TG4 to the high level (H), to change the output control clock TG3 to the low level (L).

  As a result, the information charges accumulated in the potential wells below the transfer electrodes 14-1 to 14-3 and 34-1 to 34-3 other than the final stage in the even column vertical shift register are held, and the odd column vertical shift is performed. The transfer electrodes 34-1 to 34-3 and the output gate electrodes 16 and 18 are held while retaining the information charges accumulated in the potential wells below the transfer electrodes 14-1 to 14-3 and 34-1 to 34-3 in the register. , 30, and 32, the information charges corresponding to the even-numbered blue (B) can be transferred and output to the horizontal shift register. At time FH, the information charges transferred and output below the horizontal transfer electrodes 24-1 and 24-2 are horizontally transferred along the horizontal shift register.

Here, the time _t 7 _{~t 14} and time _t 15 _~t in the vertical transfer of up to _20, the information charges accumulated in addition to the final stage of the vertical shift register transfer electrodes 14-2,14-3,34-2, It is almost fixed to the potential well below 34-3. Note that the movement of information charges occurs at the positions indicated by black dots (dots) in FIGS. As described above, by adding the output control clocks TG3 and TG4 that are controlled independently of the output control clocks TG1 and TG2, the substantial transfer stage can be reduced as compared with the conventional case.

  When the information charge of the maximum saturation amount is accumulated, every time the information charge is transferred, electron-hole recombination occurs in the potential well, and the information charge accumulated therein is reduced. According to the present embodiment, it is possible to suppress the deterioration of information charges by reducing the substantial number of transfer stages. In addition, the substantial difference in the number of transfer stages between the odd and even columns can be reduced. Along with this, it is possible to prevent the deterioration of the linearity of the output signal due to the decrease in information charge, and to increase the saturated output of the signal.

  In addition, by performing vertical transfer so that odd columns and even columns are alternately output to the horizontal shift register, mixing of information charges corresponding to different wavelength components is prevented when performing color imaging, and horizontal shifting is performed. The number of bits of the register can be reduced.

  Conventionally, there is a high demand for miniaturization of a CCD solid-state imaging device, and an increase in output control clock has been difficult due to an increase in the number of pins of a chip and a complicated and large clock pulse generation circuit. However, as the resolution of CCD solid-state imaging devices in recent years has increased, the chip size has increased, and even if the output control clock is increased, the increase in the number of pins and the complexity and increase in size of the clock pulse generation circuit are major problems. It is no longer becoming.

FIG. 7 shows a timing chart of the vertical clock pulses φs _{1 to} φs ₃ and the output control clocks TG _{1 to} TG ₄ when transferring while discharging unnecessary information charges during the vertical transfer. In FIG. 7, the information charges corresponding to the central pixel among three consecutive pixels in the middle of the vertical transfer are discharged, and the information charges corresponding to the same color are added and synthesized in the vertical direction and transferred to the horizontal shift register. The timing chart is shown. The transfer electrodes 14-1 to 14-3, 34-1, 34-3 and the output gate electrodes 16, 18, 30, and 32 are turned on when the applied clock pulse is at a high level (H). It shall be turned off at level (L). Also, the period to perform the same control and timing chart of FIG. 4 represents the same reference numerals as the time t ₁ ~t _20.

  8 and 9, transfer electrodes 14-1 to 14-3, 34-1 to 34-3, and first to fourth transfer electrodes 14-1 to 14-3, 34-1 to 34-3 corresponding to respective times in the odd-numbered column and even-numbered column vertical shift registers, respectively. The formation state of the potential well under the output gate electrodes 16, 18, 30, and 32 and the state of information charge transfer are shown. Information charges (R, G, B) corresponding to different wavelength components are distinguished from each other by using different hatching.

From time t _{1 to} t ₆ , vertical transfer is performed as in FIG. The information charges closest to the horizontal shift register are moved to the potential well below the output gate electrodes 16, 18, 30, and 32 by the transfer at times t _{1 to} t ₆ .

At time D1, the vertical clock pulses φs ₁ and φs ₃ and the output control clock TG3 are maintained at a low level (L), the vertical clock pulse φs ₂ and the output control clocks TG1 and TG2 are maintained at a high level (H). The output control clock TG4 commonly applied to the transfer electrode 34-2 and the output gate electrode 32 is changed to the low level (L). Thereby, the vertical clock pulse clocks φs ₁ and φs ₃ applied to the transfer electrodes 34-1 and 34-3 and the output control clock TG4 applied to the transfer electrode 34-2 are simultaneously set to the low level (L). All the transfer electrodes 34-1 to 34-3 provided in the final stage of the vertical shift register are turned off. Therefore, the information charge closest to the horizontal shift register (green (G) in the odd-numbered column, blue (B) in the even-numbered column) and the information charge third closest to the horizontal shift register (green (G) in the odd-numbered column, Blue (B)), that is, the information charge that is the second closest to the horizontal shift register stored in the potential well below the transfer electrode 34-2 (red (R) in the odd-numbered columns), In the even-numbered row, green (G)) is discharged to the deep part of the substrate of the solid-state imaging device.

  Subsequently, at time D2, the output control clock TG4 that is commonly applied to the transfer electrode 34-2 and the fourth output gate electrode 32 is changed to a high level (H). As a result, the potential well is formed again under the transfer electrode 34-2, but the potential well is emptied by the discharge operation of the information charge at time D1.

In the present embodiment, is performed to discharge the information charges by one by the output control clock TG4, it is also preferable to discharge more reliably information charges by repeating the state of the time D ₁ and D _2.

At times S _{1 to} S ₁₂ , the vertical clock pulses φs _{1 to} φs ₃ are applied at different phases, whereby the third closest information charge from the horizontal shift register (green (G) in odd columns, blue (G in even columns)) B)) is transferred to the output gate electrodes 16, 18, 30, 32, and is added and combined with information charges corresponding to the same color (green (G) in odd columns and blue (B) in even columns). At this time, the output control clock TG4 is varied in the same phase as the vertical clock pulse .phi.s _2.

At time _{S 1,} the vertical clock pulses .phi.s ₃ is changed to the high level (H). At time _{S 2,} a vertical clock pulse .phi.s ₂ and an output control clock TG4 is changed to low level (L). As a result, the information charges accumulated in the potential well under the transfer electrode 14-2 are moved to the potential well under the transfer electrode 14-3. At time _{S 3,} the vertical clock pulses .phi.s ₁ is changed to the high level (H). At time _{S 4,} the vertical clock pulses .phi.s ₃ is changed to low level (L). As a result, the information charges accumulated in the potential well under the transfer electrode 14-3 are moved to the potential well under the transfer electrodes 14-1, 34-1. At a time _{S 5,} the vertical clock pulses .phi.s ₂ and an output control clock TG4 is changed to the high level (H). At time _{S 6,} the vertical clock pulses .phi.s ₁ is changed to the low level (L). As a result, the information charges accumulated in the potential well below the transfer electrodes 14-1 and 34-1 are moved to the potential well below the transfer electrodes 14-2 and 34-2. At the time _{S 7,} the vertical clock pulses .phi.s ₃ is changed to the high level (H). At time _{S 8,} the vertical clock pulses .phi.s ₂ and an output control clock TG4 is changed to low level (L). As a result, the information charges accumulated in the potential well under the transfer electrodes 14-2 and 34-2 are moved to the potential well under the transfer electrodes 14-3 and 34-3. At time _{S 9,} the vertical clock pulses .phi.s ₁ is changed to the high level (H). At time _{S 10,} the vertical clock pulses .phi.s ₃ is changed to low level (L). As a result, the information charges accumulated in the potential well below the transfer electrodes 14-3 and 34-3 are moved to the transfer electrodes 14-1 and 34-1. At time _{S 11,} the vertical clock pulses .phi.s ₂ and an output control clock TG4 is changed to the high level (H).

Then, at time _{S 12,} the vertical clock pulses .phi.s ₁ is changed to the low level (L). As a result, the information charges accumulated in the potential well under the transfer electrodes 14-1 and 34-1 are transferred to the potential well under the transfer electrodes 14-2 and 34-2 and the output gate electrode 32 (16, 18, 30). Moved. As a result, information charges for two pixels corresponding to the same color (green (G) in the odd-numbered column and blue (B) in the even-numbered column) are added and synthesized in the vertical direction.

Hereinafter, similarly to the timing chart in the period of time t _{7 to} t ₂₀ in FIG. 4, by controlling the vertical clock pulses φs _{1 to} φs ₃ and the output control clocks TG _{1 to} TG ₄ , information is alternately input from the odd and even columns. Charges can be output to the horizontal shift register.

  In this case as well, the information charges accumulated in other than the final stage of the vertical shift register are substantially fixed in the potential well below the transfer electrodes 14-2, 14-3, 34-2, and 34-3. Note that the movement of information charges occurs at the positions indicated by black dots (dots) in FIGS.

  As described above, according to the present embodiment, the substantial transfer stage can be reduced as compared with the prior art, and information charges corresponding to the same color can be added and combined during vertical transfer. As a result, when it is sufficient to capture an image with a low resolution, information charges can be added and synthesized while preventing mixing of information charges corresponding to different wavelength components when color imaging is performed, and the number of horizontal transfers in the horizontal shift register. Can be reduced.

  In addition, as shown in FIG. 10, when it is desired to acquire an image region (region without hatching) obtained by cutting out only a part of the image 50 obtained by the imaging unit 6i of the solid-state imaging device, output control controlled independently. By changing the clock TG4, the information charges corresponding to the unnecessary image area 52 (hatched area) among the information charges transferred to the storage section 6s are discharged to the substrate at the transfer electrode 34-2, and the necessary image is obtained. It is also possible to cut out only the region in the vertical direction.

In the present embodiment, the vertical clock pulses φs _{1 to} φs ₃ and the output control clocks TG 1, TG 2, TG 3 are applied to the transfer electrode 34-2 among the transfer electrodes 34-1 to 34-3 as the final stage of the storage unit 6s. The output control clock TG4 that can be controlled independently from the control circuit TG4 is applied. However, if the output control clock TG4 can be applied to any one of the transfer electrodes 34-1 to 34-3, the present embodiment Similar effects can be obtained.

  The application range of the present invention is not limited to the frame transfer type CCD solid-state imaging device. For example, the same operation and effect can be obtained by applying the same electrode configuration and control method to other imaging devices such as an interline transfer type and a frame interline transfer type CCD solid-state imaging device.

<Second Embodiment>
A CCD solid-state imaging device and a control method thereof according to the second embodiment of the present invention will be described below with reference to the drawings. FIG. 15 shows the configuration of the solid-state imaging device in the present embodiment. The CCD solid-state imaging device in the present embodiment includes an imaging unit 6i, a storage unit 6s, a horizontal transfer unit 6h, and an output unit 6d.

  The imaging unit 6i includes a plurality of columns of vertical shift registers. Each bit of each vertical shift register is associated with a light receiving pixel arranged in a matrix. The imaging unit 6i receives a vertical clock pulse from the clock pulse generation unit 8, and performs imaging and information charge transfer according to the change of the vertical clock pulse. The accumulation unit 6s includes a vertical shift register that is continuous with the vertical shift register of the imaging unit 6i. A vertical clock pulse and an output control clock are input from the clock pulse generator 8 to the accumulator 6s. The horizontal transfer unit 6h includes a horizontal shift register having a number of bits corresponding to the number of columns of the vertical shift registers of the imaging unit 6i and the storage unit 6s. A horizontal clock pulse is input from the clock pulse generation unit 8 to the horizontal transfer unit 6h, and information charges are transferred to the output unit 6d in units of pixels. The output unit 6d converts the information charge amount for each pixel into a voltage value and outputs the voltage value.

  This embodiment is characterized in that it is controlled by a five-phase output control clock that can be controlled independently of the vertical clock pulse. FIG. 16 is a plan view of the internal structure of the storage unit 6s and the horizontal transfer unit 6h, which are the main parts of the CCD solid-state imaging device in the present embodiment.

  In the present embodiment, five output gate electrodes are arranged in the boundary region between the vertical shift register and the horizontal shift register. The first output gate electrode 60 is meandered so as to be closest to the channel region 12 in the 3n + 1 column, in the intermediate position in the 3n + 2 column, and farthest from the channel region 12 in the 3n + 3 column, and to the transfer electrode 14 on the output side of the vertical shift register. Arranged in parallel. The second output gate electrode 62 is in the middle position in the 3n + 1 column, is farthest from the channel region 12 in the 3n + 2 column, and meanders so as to be closest to the channel region 12 in the 3n + 3 column. Arranged in parallel. The third output gate electrode 64 is farthest from the channel region 12 of the 3n + 1 column, is closest to the channel region 12 of the 3n + 2 column, meanders so as to be an intermediate position in the 3n + 3 column, and is transferred to the output side of the vertical shift register. 14 in parallel. The first to third output gate electrodes 60, 62, 64 are arranged on the isolation region 10 so as to cross each other via an insulating film. These first to third output gate electrodes become middle stage output gate electrodes. The fourth output gate electrode 66 is disposed further on the output side than the first to third output gate electrodes 60, 62, 64. The fourth output gate electrode 66 is close to the third output gate electrode 64 in the 3n + 1 column, close to the second output gate electrode 62 in the 3n + 2 column, and close to the first output gate electrode 60 in the 3n + 3 column. . The fourth output gate electrode 66 is disposed with an insulating film between the first to third output gate electrodes 60, 62, and 64. The fourth output gate electrode 66 becomes a subsequent output gate electrode. Here, n is 0 or an integer of 1 or more.

The first to fourth output gate electrode 60, 62, 64, 66, the output control clock TG1 four-phase vertical clock pulses φs ₁ ~φs ₃ which is controlled independently, TG2, TG3, TG4, respectively Applied.

In addition, transfer electrodes 34-1 to 34-3 constituting pixels for one row are further provided at the final stage of the storage unit 6s, and the transfer electrodes 14-1 are continuously connected to the transfer electrodes 34-1 to 34-3. A fifth output gate electrode 68 is provided across the electrode. The fifth output gate electrode 68 becomes the previous output gate electrode. Here, any one of the transfer electrodes 34-1 to 34-3 and the fifth output gate electrode 68 have outputs that can be controlled independently of the vertical clock pulses φs _{1 to} φs ₃ and the output control clocks TG1 to TG4. A control clock TG5 is applied in common.

  In the first embodiment, the fourth output gate electrode 32 corresponds to the previous output gate electrode, the first and second output gate electrodes 16 and 18 correspond to the middle output gate electrode, and the third The output gate electrode 30 corresponds to a subsequent output gate.

FIG. 17 shows a timing chart of vertical clock pulses φ _{1 to} φ ₃ and output control clocks TG _{1 to} TG ₅ when information charges are vertically transferred. 18 to 20, the potentials under the transfer electrodes 14-1 to 14-3 and 34-1 to 34-3 and the first to fifth output gate electrodes 60 to 68 corresponding to the respective times of FIG. The state of well formation and the state of information charge transfer are shown. The transfer electrodes 14-1 to 14-3, 34-1 to 34-3 and the first to fifth output gate electrodes 60 to 68 are turned on when the applied clock pulse is at a high level (H), It shall be turned off at level (L).

At times t _{1 to} t ₃ , the information charges in each column are transferred to the potential well formed under the transfer electrodes 14-2 and 34-2 and the fifth output gate electrode 68. At this time, the output control clock TG5 is controlled by the vertical clock pulse .phi.s ₂ the same phase. At time _{t 4,} a vertical clock pulse .phi.s ₂ and the output control clock TG1, TG2, TG3, the TG5 and high level (H), the vertical clock pulses φs _1, φs ₃ and the output control clock TG4 a low level (L) . As a result, the information charges in the vertical shift register are held in the transfer electrodes 14-2 and 34-2, and the information charges closest to the horizontal shift register are formed under the output gate electrodes 60, 62, 64, and 68. Retained.

At time D1, the vertical clock pulses φs ₁ and φs ₃ and the output control clock TG4 are maintained at a low level (L), and the vertical clock pulse φs ₂ and the output control clocks TG1, TG2, and TG3 are maintained at a high level (H). At the same time, the output control clock TG5 commonly applied to the transfer electrode 34-2 and the fifth output gate electrode 68 is changed to the low level (L). As a result, the vertical clock pulses φs ₁ and φs ₃ applied to the transfer electrodes 34-1 and 34-3 and the output control clock TG5 applied to the transfer electrode 34-2 are simultaneously set to the low level (L). All the transfer electrodes 34-1 to 34-3 provided in the final stage of the vertical shift register are turned off. Therefore, in each column, the information charge existing between the information charge closest to the horizontal shift register and the information charge closest to the third from the horizontal shift register, that is, accumulated in the potential well below the transfer electrode 34-2. The second closest information charge is discharged from the horizontal shift register to the deep part of the substrate of the solid-state imaging device.

  Subsequently, at time D2, the output control clock TG5 applied in common to the transfer electrode 34-2 and the fifth output gate electrode 68 is changed to a high level (H). As a result, the potential well is formed again under the transfer electrode 34-2, but the potential well is emptied by the discharge operation of the information charge at time D1.

In the present embodiment, is performed in a single discharge of the information charges by the action of the output control clock TG5, also be discharged more reliably information charges by repeating the state of the time D ₁ and D ₂ preferable.

At times S _{1 to} S ₁₂ , the vertical clock pulses φs _{1 to} φs ₃ are applied at different phases, so that the information charges that are the third closest to the horizontal shift register in each column are output gate electrodes 60 and 62. , 64, 68 and is added and synthesized with the information charge closest to the horizontal shift register. At this time, the output control clock TG5 is varied in the same phase as the vertical clock pulse .phi.s _2.

At time _{S 1,} the vertical clock pulses .phi.s ₃ is changed to the high level (H). At time _{S 2,} a vertical clock pulse .phi.s ₂ and an output control clock TG5 is changed to low level (L). As a result, the information charges accumulated in the potential well under the transfer electrode 14-2 are moved to the potential well under the transfer electrode 14-3. At time _{S 3,} the vertical clock pulses .phi.s ₁ is changed to the high level (H). At time _{S 4,} the vertical clock pulses .phi.s ₃ is changed to low level (L). As a result, the information charges accumulated in the potential well under the transfer electrode 14-3 are moved to the potential well under the transfer electrodes 14-1, 34-1. At a time _{S 5,} the vertical clock pulses .phi.s ₂ and an output control clock TG5 is changed to the high level (H). At time _{S 6,} the vertical clock pulses .phi.s ₁ is changed to the low level (L). As a result, the information charges accumulated in the potential well below the transfer electrodes 14-1 and 34-1 are moved to the potential well below the transfer electrodes 14-2 and 34-2. At the time _{S 7,} the vertical clock pulses .phi.s ₃ is changed to the high level (H). At time _{S 8,} the vertical clock pulses .phi.s ₂ and an output control clock TG5 is changed to low level (L). As a result, the information charges accumulated in the potential well under the transfer electrodes 14-2 and 34-2 are moved to the potential well under the transfer electrodes 14-3 and 34-3. At time _{S 9,} the vertical clock pulses .phi.s ₁ is changed to the high level (H). At time _{S 10,} the vertical clock pulses .phi.s ₃ is changed to low level (L). As a result, the information charges accumulated in the potential well below the transfer electrodes 14-3 and 34-3 are moved to the transfer electrodes 14-1 and 34-1. At time _{S 11,} the vertical clock pulses .phi.s ₂ and an output control clock TG5 is changed to the high level (H).

Then, at time _{S 12,} the vertical clock pulses .phi.s ₁ is changed to the low level (L). As a result, the information charges accumulated in the potential well under the transfer electrodes 14-1 and 34-1 are transferred to the potential under the transfer electrodes 14-2 and 34-2 and the output gate electrode 68 (60, 62, 64, 66). Moved to the well. As a result, information charges for two pixels in each column are added and synthesized in the vertical direction.

At time _{t 5,} the vertical clock pulses .phi.s ₃ is changed to the high level (H). Further, the horizontal clock pulse HS1 applied to the horizontal transfer electrodes of the horizontal shift registers connected to the 3n + 1 column is set to the high level (H). At time _{t 6,} the vertical clock pulses .phi.s ₂ and an output control clock TG5 is changed to a low level. As a result, the information charge added and synthesized with the horizontal shift register is transferred to the potential well formed under the output gate electrodes 60, 62 and 64. At time _{t 7,} to maintain a vertical clock pulse .phi.s ₃ and the output control clock TG3 to the high level (H), a vertical clock pulses φs _1, φs ₂ and an output control clock TG1, TG2, TG4, TG5 a low level (L) And As a result, the information charges in the 3n + 1 column are held in the potential well adjacent to the fourth output gate electrode 66, and the information charges in the 3n + 2 column and 3n + 3 column are held in the potential well located at a position away from the output gate electrode 66. .

At time _{t 8,} the vertical clock pulses .phi.s ₃ and the output control clock TG1, TG3, TG4 at the high level (H). Further, the output control clock TG3 At time _{t 9} is changed to the low level (L), the output control clock TG4 at time _{t 10} is changed to the low level (L). Here, since the horizontal clock pulse HS1 applied to the horizontal transfer electrode 24 of the horizontal shift register connected to the 3n + 1 column is at the high level (H), the information charges are transferred from the 3n + 1 column to the horizontal shift register. . On the other hand, 3n + 2 and 3n + 3 columns of information charges are transferred from the potential well below the third output gate electrode 64 to the potential well below the first output gate electrode 60. At time FH, the information charges transferred from the 3n + 1 column vertical shift register to the horizontal shift register are horizontally transferred along the horizontal shift register.

At times t _{11 to} t ₁₄ , 3n + 2 columns of information charges are transferred / output to the horizontal transfer unit 6h. At time t _11, the horizontal clock pulse HS2 applied to horizontal transfer electrodes 24 of the horizontal shift register connected to 3n + 2 rows has a high level (H). At time _{t 12,} the vertical clock pulses .phi.s ₃ and the output control clock TG1 is being maintained at the high level (H), the output control clock TG2, TG4 is changed to the high level (H). Further, the output control clock TG1 At time _{t 13} is changed to the low level (L), the output control clock TG4 at time _{t 14} is changed to a low level (L). Here, since the horizontal clock pulse HS2 applied to the horizontal transfer electrode 24 of the horizontal shift register connected to the 3n + 2 column is at a high level (H), information charges are transferred from the 3n + 2 column to the horizontal shift register. . On the other hand, 3n + 3 columns of information charges are transferred from the potential well under the first output gate electrode 60 to the potential well under the second output gate electrode 62. At time FH, the information charges transferred from the 3n + 2 columns of vertical shift registers to the horizontal shift register are horizontally transferred along the horizontal shift register.

At time _t 15 _{~t 18,} 3n + 3 rows of information charges are transferred and output to the horizontal transfer portion 6h. At time t _15, the horizontal clock pulses HS3 applied to horizontal transfer electrodes 24 of the horizontal shift register coupled to 3n + 3 column is set to the high level (H). At time _{t 16,} the vertical clock pulses .phi.s ₃ and the output control clock TG2 is being maintained at the high level (H), the output control clock TG4 is changed to high level (H). Further, the output control clock TG2 At time _{t 17} is changed to the low level (L), output control clock TG4 at time _{t 18} is changed to the low level (L). Here, since the horizontal clock pulse HS3 applied to the horizontal transfer electrode 24 of the horizontal shift register connected to the 3n + 3 column is at the high level (H), the information charges are transferred from the 3n + 3 column to the horizontal shift register. . At time FH, the information charges transferred from the 3n + 3 columns of vertical shift registers to the horizontal shift register are horizontally transferred along the horizontal shift register.

At time _{t 19,} the vertical clock pulses .phi.s ₁ is a high level (H). Thereafter, at time t ₁ , the vertical clock pulse φs ₃ is set to the low level (L), so that the information charges held in the potential well below the transfer electrode 14-3 in each column are transferred to the transfer electrode 14−. 2 is transferred to the lower potential well. Hereinafter, by repeating the control of each clock pulse from time t1 to t19, unnecessary information charges can be discharged, and information charges can be transferred while adding information charges in the vertical transfer direction.

  In this way, one front stage output gate electrode 68, three middle stage output gate electrodes 60, 62, 64, and one rear stage output gate electrode 64 are provided, and these output gate electrodes 60 to 68 and the final stage of the vertical shift register are provided. Any one of the transfer electrodes 34-1 to 34-3 is controlled by an output control clock that can be controlled independently of the vertical clock pulse, so that three vertical shift registers are set as one set. Thus, one vertical shift register can be sequentially selected to output information charges. Further, if necessary, information charges can be discharged to the deep part of the substrate and output while thinning out information charges in the vertical direction. Similarly, n middle stage output gate electrodes are provided, and one front stage output gate electrode and one rear stage output gate electrode are provided before and after the middle stage output gate electrode, respectively, and each output gate electrode is controlled independently of the vertical clock pulse. By allowing a possible output control clock to be applied and allowing a common output control clock to be applied to any one of the previous-stage output gate electrode and the transfer electrode as the final stage of the vertical shift register, n columns of vertical control clocks can be applied. Information charges can be output by selecting one set of shift registers and sequentially selecting each set of vertical shift registers one by one. Further, if necessary, information charges can be discharged to the deep part of the substrate and output while thinning out information charges in the vertical direction.

  If unnecessary information charges do not need to be discharged, the information charges can be transferred by skipping the processes at times D1 and D2. Furthermore, when there is no need to add and combine information charges for a plurality of pixels, it is possible to transfer information charges by skipping the processing of S1 to S12.

  According to the present embodiment, the substantial number of transfer stages is reduced. As a result, the deterioration of information charges can be suppressed. In addition, the substantial difference in the number of transfer stages in each column can be reduced. Further, it is possible to prevent deterioration of the linearity of the output signal due to the decrease of the information charge and increase the saturated output of the signal.

  In addition, information charges can be added and combined during vertical transfer. This makes it possible to add and synthesize information charges when it is sufficient to capture an image with a low resolution, and to reduce the number of horizontal transfers in the horizontal shift register.

  Similarly to the first embodiment, when it is desired to obtain an image region obtained by cutting out only a part of an image obtained by the imaging unit 6i of the solid-state imaging device, the information charge transferred to the storage unit 6s It is also possible to discharge information charges corresponding to an unnecessary image area to the substrate at the transfer electrode 34-2 and cut out only the required image area in the vertical direction.

In the present embodiment, the vertical clock pulses φs _{1 to} φs ₃ and the output control clocks TG _{1 to} TG ₄ are applied to the transfer electrode 34-2 among the transfer electrodes 34-1 to 34-3 as the final stage of the storage unit 6s. The output control clock TG5 that can be controlled independently is applied. However, if the output control clock TG5 can be applied to any one of the transfer electrodes 34-1 to 34-3, the configuration is the same as that of the present embodiment. The effect can be obtained.

  The application range of the present invention is not limited to the frame transfer type CCD solid-state imaging device. For example, the same operation and effect can be obtained by applying the same electrode configuration and control method to other imaging devices such as an interline transfer type and a frame interline transfer type CCD solid-state imaging device.

It is a figure which shows the structure of the solid-state imaging device in 1st Embodiment. It is a figure which shows the arrangement structure of the pixel of the solid-state image sensor in 1st Embodiment. It is a top view which shows the internal structure of the solid-state image sensor in 1st Embodiment. It is a figure which shows the timing chart of the vertical clock pulse in the 1st Embodiment, an output control clock, and a horizontal clock pulse. It is a figure which shows the change of the potential of the storage part and horizontal transfer part in 1st Embodiment. It is a figure which shows the change of the potential of the storage part and horizontal transfer part in 1st Embodiment. It is a figure which shows the timing chart of the vertical clock pulse in the 1st Embodiment, an output control clock, and a horizontal clock pulse. It is a figure which shows the change of the potential of the storage part and horizontal transfer part in 1st Embodiment. It is a figure which shows the change of the potential of the storage part and horizontal transfer part in 1st Embodiment. It is a figure which shows the captured image containing an unnecessary image area | region (hatching part). It is a figure which shows the structure of the conventional solid-state imaging device. It is a top view which shows the internal structure of the conventional solid-state image sensor. It is a figure which shows the timing chart of the vertical clock pulse in the conventional solid-state imaging device, an output control clock, and a horizontal clock pulse. It is a figure which shows the change of the potential of the storage part and horizontal transfer part in the conventional solid-state imaging device. It is a figure which shows the structure of the solid-state imaging device in 2nd Embodiment. It is a top view which shows the internal structure of the solid-state image sensor in 2nd Embodiment. It is a figure which shows the timing chart of the vertical clock pulse in a 2nd Embodiment, an output control clock, and a horizontal clock pulse. It is a figure which shows the change of the potential of the storage part and horizontal transfer part in 2nd Embodiment. It is a figure which shows the change of the potential of the storage part and horizontal transfer part in 2nd Embodiment. It is a figure which shows the change of the potential of the storage part and horizontal transfer part in 2nd Embodiment.

Explanation of symbols

  2d output unit, 2i imaging unit, 2h horizontal transfer unit, 2s storage unit, 4 clock pulse generation unit, 6d output unit, 6i imaging unit, 6h horizontal transfer unit, 6s storage unit, 8 clock pulse generation unit, 10 separation region, 12 channel region, 14 transfer electrode, 16 first output gate electrode, 18 second output gate electrode, 20 third output gate electrode, 22 channel region, 24 horizontal transfer electrode, 26 horizontal separation region, 30 third Output gate electrode, 32 Fourth output gate electrode, 34 Transfer electrode, 50 Captured image, 52 Unnecessary image area, 60, 62, 64 Middle output gate electrode (first to third output gate electrodes), 66 Subsequent output Gate electrode (fourth output gate electrode), 68 Previous stage output gate electrode (fifth output gate electrode).

Claims (8)

A plurality of transfer electrodes extending in the horizontal direction and arranged at a predetermined interval, arranged as vertical columns intersecting the plurality of transfer electrodes, and controlling information by controlling transfer clock pulses applied to the transfer electrodes A solid-state imaging device including a plurality of vertical shift registers for transferring charges in the vertical direction,
First and second output gate electrodes provided on the output side of the vertical shift register, common to each column of the plurality of vertical shift registers, and in which the arrangement order is reversed between the odd and even columns;
A third output gate electrode that is common to each column of the plurality of vertical shift registers and is arranged on the output side from the first and second output gate electrodes;
A fourth output gate electrode that is common to each column of the plurality of vertical shift registers and is arranged on the input side from the first and second output gate electrodes,
Each bit is associated with an output from the plurality of vertical shift registers, and at least one of a plurality of transfer electrodes associated with at least one bit of the vertical shift register, and the fourth output gate electrode, A solid-state imaging device, wherein an output control clock controlled independently of the transfer clock pulse and the output control clock applied to the first to third output gate electrodes can be applied in common. The solid-state imaging device according to claim 1,
An output control clock controlled independently of an output control clock applied to the third output gate electrode can be applied to the first and second output gate electrodes. Solid-state imaging device. A control method for a solid-state imaging device according to claim 1 or 2,
A control method for a solid-state imaging device, wherein information charges are discharged during vertical transfer by changing an output control clock applied in common with the fourth output gate electrode. It is a control method of the solid-state imaging device according to claim 3,
In the plurality of vertical shift registers, the storage positions of the information charges are shifted by 1 bit between the odd and even columns, and the information charges are alternately output to the horizontal shift register from the odd and even columns of the vertical shift register. Control method of solid-state imaging device. A plurality of transfer electrodes extending in the horizontal direction and arranged at a predetermined interval, arranged as vertical columns intersecting the plurality of transfer electrodes, and controlling information by controlling transfer clock pulses applied to the transfer electrodes A solid-state imaging device including a plurality of vertical shift registers for transferring charges in the vertical direction,
A plurality of middle output gate electrodes provided on the output side of the vertical shift register and common to each column of the plurality of vertical shift registers;
A rear output gate electrode that is common to each column of the plurality of vertical shift registers and is arranged on the output side from the plurality of middle output gate electrodes;
A pre-stage output gate electrode that is common to each column of the plurality of vertical shift registers and is arranged on the input side from the plurality of middle-stage output gate electrodes,
Each bit is associated with an output from the plurality of vertical shift registers, the transfer to at least one of the plurality of transfer electrodes associated with at least one bit of the vertical shift register, and the preceding output gate electrode An output control clock controlled independently of a clock pulse, an output control clock applied to the middle output gate electrode, and an output control clock applied to the subsequent output gate electrode can be commonly applied. Solid-state imaging device. The solid-state imaging device according to claim 5,
A solid-state imaging device, wherein an output control clock controlled independently of an output control clock applied to the subsequent output gate electrode can be applied to the plurality of middle output gate electrodes. The solid-state imaging device according to claim 5,
The middle stage output gate electrode is provided with n (where n is an integer of 2 or more),
A set of adjacent n columns of vertical shift registers is set, and information charges are selectively transferred from any one of the vertical shift registers of the set to a subsequent output gate electrode. Solid-state imaging device. In the control method of the solid-state imaging device according to any one of claims 5 to 7,
A control method for a solid-state imaging device, wherein information charges are discharged during vertical transfer by changing an output control clock applied in common with the subsequent output gate electrode.

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