JP2010021969A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify control for preventing generation of longitudinal streaks in an image by suppressing a dark current, that is generated during a signal charge holding term and variation thereof, in a solid-state imaging apparatus. <P>SOLUTION: A solid-state imaging apparatus includes: a pixel row 1 wherein pixels each having a photoelectric conversion part are disposed in one row; a shift gate 2 which is arrayed parallel to the pixel row, to which a shift pulse is applied and which controls passing of a signal charge amount generated in the pixel row; a stored pixel row 3 wherein stored pixels holding signal charges transferred via the shift gate are disposed in one row; a barrier gate row 4 for performing timing control so as to control a signal charge holding time in the stored pixel line; a CCD register 5 for sequentially transferring signal charges, in a predetermined direction, transferred from the barrier gate row; and a floating dispersion area 6 into which signals charges flow from a final stage of the CCD register; wherein signal charges are transferred from one or more different stored pixels to one transfer electrode of the CCD register in accordance with a resolution. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a signal charge transfer control unit in a solid-state imaging device including a CCD register that sequentially transfers signal charges output from a pixel column having a photoelectric conversion unit in a predetermined direction. For example, it is used for a line sensor.

  For example, a solid-state imaging device used for a line sensor includes a CCD register that sequentially transfers signal charges output from a pixel column having a photoelectric conversion unit in a predetermined direction. Conventionally, such a solid-state imaging device has a structure in which the signal charge from a pixel is held in an accumulation gate and the resolution is switched by controlling the signal charge holding time based on the timing of the accumulation gate and the barrier gate.

  However, in such a structure, a dark current is generated while the charge is held in the storage gate, and the dark current fluctuates. Therefore, the black reference (dark current output value) in the same bit is generated. Fluctuates, and vertical stripes occur as image signals.

  In addition, the solid-state imaging device disclosed in Patent Document 1 is arranged in a fixed direction and includes a pixel column including a plurality of pixels that generate signal charges by photoelectric conversion, and is arranged in parallel with the pixel column, and the pixel column is generated. A composite signal obtained by synthesizing at least two of the accumulation gate row including a plurality of accumulation gates for accumulating signal charges and at least two of the signal charges accumulated in each accumulation gate of the accumulation gate row at the time of low resolution. A CCD register for sequentially transferring charges is provided.

Further, in the solid-state imaging device disclosed in Patent Document 2, signal charges generated in pixels of one pixel column out of two pixel columns provided at a distance are transferred to the final stage of the first analog shift register. Each time it is transferred to the charge detection unit with the first transfer clock, a reset pulse is generated and discharged to the reset drain region, and the signal charge generated in the pixels of the other pixel column is shifted to the second analog shift. When the data is transferred to the final stage of the register, it is accumulated in the capacity of the charge detection unit at the timing of the second transfer clock, and the charge amount is read and output as an output signal from the output circuit. Thus, by discarding all signal charges in one pixel column and taking out only signal charges in the other pixel column, it is possible to read out the image with a resolution of 1/2 without causing image degradation.
JP 2007-74421 A JP 2001-54021 A

  The present invention has been made to solve the above-mentioned conventional problems, and suppresses dark current and its fluctuations that occur during a signal charge holding period before being transferred to a CCD register, thereby reducing the occurrence of vertical stripes in an image. An object of the present invention is to provide a solid-state imaging device capable of simplifying the control for preventing it.

  The solid-state imaging device according to the present invention includes a pixel row in which pixels having photoelectric conversion units are arranged in a row, a parallel arrangement of the pixel row, a shift pulse is applied, and a signal charge amount generated in the pixel row is passed. A shift gate to be controlled, a storage pixel column arranged in parallel with the shift gate and holding the signal charge transferred via the shift gate, and a signal charge holding in the storage pixel column A plurality of barrier gate rows that are controlled in timing so as to control time and a signal gate that is arranged in parallel adjacent to the barrier gate row and sequentially transfers signal charges transferred from the barrier gate row in a predetermined direction. A CCD register having a transfer electrode, wherein one transfer electrode of the CCD register includes from one or more different storage pixels depending on the resolution. No. charge is characterized in that it is transferred.

  According to the solid-state imaging device of the present invention, the dark current generated during the signal charge holding period before being transferred to the CCD register and its fluctuation are suppressed, and the control for preventing the occurrence of vertical stripes in the image is simplified. be able to.

  The present invention will be described below with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

<First Embodiment>
FIG. 1 is a plan view showing an example of a pattern arrangement by extracting a part of the line sensor according to the first embodiment of the solid-state imaging device of the present invention. Three sets having such a pattern arrangement are arranged corresponding to the RGB components of the imaging input. 2A and 2B show an example of a cross-sectional structure and a potential distribution of the semiconductor substrate in a cross section taken along line BB ′ in FIG.

1 and 2, reference numeral 1 denotes a pixel column. In this example, a photoelectric conversion unit having a P ⁺ NP structure (a structure in which a P ⁺ layer is formed on the surface of a PN photodiode formed on an N-type semiconductor substrate). Are arranged in a line. In FIG. 1, signal charges accumulated in the pixels are denoted by S1, S2,..., S8. Reference numeral 2 denotes a shift gate (SH), which is arranged in parallel with the pixel column 1 and is applied with a shift pulse for controlling the passage of the signal charge generated in the pixel column 1. The shift gate 2 allows the signal charge to pass while the shift pulse is at a high level ("High"). The low level ("Low") period of the shift pulse is set to a negative potential and is pinned. As a result, holes fill the interface of the pixel and recombine with the dark current (electrons), thereby making it possible to reduce the occurrence and fluctuation of the dark current.

Reference numeral 3 denotes an accumulation pixel array in which accumulation pixels are arranged in a line, which is arranged in parallel with the shift gate 2 and holds the signal charges transferred through the shift gate 2. At this time, as a storage pixel, for example, as shown in FIG. 2, a P ⁺ NP structure similar to that of the pixel in the pixel column 1 is provided, so that the hole of the pixel fills and recombines with dark current (electrons). Thus, the generation and fluctuation of dark current can be reduced. Reference numeral 4 denotes a barrier gate row (BG) in which barrier gates are arranged in a row. The barrier gate row (BG) is arranged adjacent to the storage pixel column 3 and controls the signal charge holding time in the storage pixel column 3. In this example, in the barrier gate row 4, a plurality of sets are repeatedly arranged with four adjacent barrier gates BG1, BG2, BG3, and BG4 related to the low-resolution operation described later as one set.

  A CCD register 5 is arranged adjacent to the barrier gate row 4 and sequentially transfers signal charges transferred from the storage pixel row 3 through the barrier gate row 4 in a predetermined direction. The CCD register 5 has a plurality of transfer electrodes, and signal charges from one storage pixel or signal charges from two or more different storage pixels flow into each transfer electrode according to the resolution. One of the clock pulses P1 and P2 is applied to the transfer electrode of each stage of the CCD register 5, and the clock pulse PA is applied to the transfer electrode of the last stage of the CCD register 5. Reference numeral 6 denotes a floating diffusion region in which signal charges flow from the final transfer electrode of the CCD register 5.

  Next, an outline of an operation example of the solid-state imaging device configured as described above will be described. Signal charges S1, S2,..., S8 photoelectrically converted in each pixel of the pixel column 1 are accumulated in each pixel. These signal charges S1, S2,..., S8 are transferred to and accumulated in the shift gate 2 when the shift gate 2 is opened. The signal charges S1, S2,..., S8 accumulated in the shift gate 2 are transferred to each accumulation pixel of the accumulation pixel column 3 and held in each accumulation pixel. The signal charges S1, S3,..., S8 held in the storage pixel column 3 are transferred to the CCD register 5 via the barrier gate column 4 and held therein. The path from the barrier gate array 4 to the CCD register 5 operates as follows according to the desired resolution.

  First, an operation example at the normal resolution will be specifically described with reference to FIG. 3 shows a shift pulse SH applied to the shift gate, each of the barrier gates BG1, BG2, BG3, BG4 of the barrier gate row 4 and clock pulses P1, P2, PA applied to the transfer electrodes of the CCD register 5, not shown. The timing of the reset pulse RS applied to the reset drain region and the voltage waveform of the signal output are shown.

  At the normal resolution, the signal charges S1, S2,..., S8 held in each storage pixel of the storage pixel column 3 are transferred to the CCD register 5 via the barrier gates BG1, BG2, BG3, BG4 of the barrier gate column 4. Sequentially transferred and held. The signal charges held in the CCD register 5 are sequentially transferred by a plurality of transfer electrodes and transferred from the final transfer electrode to the floating diffusion region 6. The signal charges S1, S2,..., S8 transferred to the floating diffusion region 6 are converted into signal voltages and output to the outside, and after being rearranged in a predetermined arrangement, an imaging signal is obtained.

  Specifically, first, the barrier gate BG1 becomes “High”, and the signal charges S1 and S5 are transferred to and held in the CCD register 5 and transferred by the CCD register 5 from the transfer electrode in the final stage to the floating diffusion region 6. Forwarded to Next, the barrier gate BG2 becomes “High”, and the signal charges S2 and S6 are transferred and held in the CCD register 5, transferred by the CCD register 5, and transferred from the transfer electrode at the final stage to the floating diffusion region 6. . Next, the barrier gate BG3 becomes “High”, and the signal charges S3 and S7 are transferred to and held in the CCD register 5, transferred by the CCD register 5, and transferred from the transfer electrode at the final stage to the floating diffusion region 6. . Next, the barrier gate BG4 becomes “High”, and the signal charges S4 and S8 are transferred to and held in the CCD register 5, transferred by the CCD register 5, and transferred from the transfer electrode at the final stage to the floating diffusion region 6. .

  On the other hand, at low resolution (1 / 2n: n is an integer), signal charges held in a plurality of adjacent storage pixels in the storage pixel column 3 are simultaneously transferred to the CCD register via the barrier gate column 4. The plurality of signal charges are added and held in the CCD register 5. The signal charges held in the CCD register 5 are sequentially transferred and transferred from the final transfer electrode to the floating diffusion region 6. The signal charge transferred to the floating diffusion region 6 is converted into a signal voltage and output to the outside, and after being rearranged in a predetermined arrangement, an imaging signal is obtained.

  First, an operation example at 1/2 resolution will be specifically described with reference to voltage waveforms shown in FIG. At 1/2 resolution, first, the barrier gates BG1 and BG2 are set to “High”, and the signal charges S1 and S2 and the signal charges S5 and S6 are clock pulses of the CCD register 5 through the barrier gates BG1 and BG2. Signals (S1 + S2) and (S5 + S6) are obtained by simultaneously transferring and adding to the transfer electrodes to which P1 is applied. The signal charges (S1 + S2) and (S5 + S6) held in the CCD register 5 are sequentially transferred and transferred from the final transfer electrode to the floating diffusion region 6.

  Next, the barrier gates BG3 and BG4 are set to “High”, and the signal charges S3 and S4 and the signal charges S7 and S8 are applied with the clock pulse P2 of the CCD register 5 through the barrier gates BG3 and BG4. Signal charges (S3 + S4) and (S7 + S8) are obtained by simultaneously transferring and adding to the transfer electrodes. The signal charges (S3 + S4) and (S7 + S8) held in the CCD register 5 are sequentially transferred and transferred from the final transfer electrode to the floating diffusion region 6.

  Next, an example of operation at 1/4 resolution will be specifically described with reference to voltage waveforms shown in FIG. At 1/4 resolution, first, the barrier gates BG3 and BG4 are set to “High”, and the signal charges S3 and S4 and the signal charges S7 and S8 are clock pulses of the CCD register 5 through the barrier gates BG3 and BG4. The signal charges (S3 + S4) and (S7 + S8) are obtained by simultaneously transferring and adding to the transfer electrode to which P2 is applied. Next, a clock pulse is applied to the CCD register to move the signal charge by one stage from the transfer electrode to which the clock pulse P2 is applied to the transfer electrode to which the clock pulse P1 is applied. Next, the barrier gates BG1 and BG2 become "High", and the signal charges (S1, S2) and (S5, S6) are applied with the clock pulse P1 of the CCD register 5 via the barrier gates BG1 and BG2. The signal charges (S1 + S2 + S3 + S4) and (S5 + S6 + S7 + S8) are obtained by simultaneously transferring and adding to the transfer electrodes.

  In the line sensor according to the first embodiment described above, the storage pixel column 3 having a pixel structure is arranged adjacent to the shift gate 2. Then, the timing of the “High” level of the shift pulse applied to the shift gate 2 is controlled, and the “Low” level is set to a negative potential. As a result, the dark current and its fluctuation generated during the signal charge holding period in the shift gate 2 and the storage pixel column 3 before being transferred to the CCD register 5 are suppressed, and the occurrence of vertical stripes in the image is prevented. Control can be simplified. As the absolute value of the “Low” level negative potential of the shift pulse is higher and the application period is longer, the generation and fluctuation of dark current can be suppressed.

  Further, at the time of low resolution, the number of signal charges that are simultaneously transferred and added according to the resolution is different, but by adding the signal charges by the CCD register 5, the clock frequency is not changed from that at the time of normal resolution. The signal charge can be read out at high speed. Therefore, a long sampling period (signal reference period, signal period) can be secured, and an effect of improving sensitivity by addition can be obtained.

  Further, since the dark output component (noise component) generated in the CCD register 5 is not added, the S / N ratio is improved. Further, since the signal charge can be held in the storage pixel column 3, the number of transfer stages of the CCD register 5 can be reduced, the signal charge can be transferred with a low clock amplitude, and the output timing can be realized in the same manner as the existing system. it can.

<Second Embodiment>
FIG. 6 is a plan view showing an example of a pattern arrangement by extracting a part of the line sensor according to the second embodiment of the solid-state imaging device of the present invention. Here, 11 is a first pixel column, 12 is a first shift gate, 13 is a first storage pixel column, 14 is a first barrier gate column, 15 is a first CCD register, and 21 is a second CCD register. A pixel column, 22 is a second shift gate, 23 is a second storage pixel column, 24 is a second barrier gate column, 25 is a second CCD register, and 6 is a floating diffusion region.

  In the second embodiment, adjacent pixels of the first and second pixel columns 11 and 21 are arranged in a staggered arrangement, for example, and each pixel column 11 and 21 is the same as the first embodiment described above. Similarly, the first and second shift gates 12 and 22, the first and second storage pixel columns 13 and 23, the first and second barrier gate columns, and the first and second CCD registers 15 and 25. Each is disposed in the opposite direction. The signal charges transferred by the first and second CCD registers 15 and 25 are added by the floating diffusion region 6. In the operation mode in which it is not necessary to add charges in the floating diffusion region 6, 1 of the transfer electrodes at the final stage of the second CCD register 25 is discharged so that the signal charges transferred by the second CCD register 25 can be discharged. A reset drain region 26 is arranged adjacent to the previous transfer electrode (transfer electrode to which the clock pulse P1 is applied). Three sets of such configurations are arranged corresponding to the RGB components of the imaging input.

  Similar to the first embodiment described above, the first and second shift gates 12 are supplied during the period when the shift pulse (SH) applied to the first and second shift gates 12 and 22 is at a high level ("High"). , 22 pass the signal charge. Similarly, the “Low” level period of the shift pulse is set to a negative potential and pinned. As a result, the generation and fluctuation of dark current can be reduced.

  One transfer electrode of the first and second CCD registers 15 and 25 has a signal charge from one storage pixel (at normal resolution) or a signal charge from two or more different storage pixels (at low resolution). Inflow. One of the clock pulses P1 and P2 is applied to the transfer electrodes of each stage of the first and second CCD registers 15 and 25, and the clock pulse PA is applied to the transfer electrodes of the last stage.

  Next, an outline of an operation example of the solid-state imaging device configured as described above will be described. The signal charges S1, S3,..., S15 photoelectrically converted in each pixel of the first pixel column 11 are accumulated in each pixel. These signal charges are transferred to and stored in the respective storage pixels of the first storage pixel column 13 after the first shift gate 12 is opened and transferred to the first shift gate 12. The signal charges held in the first accumulation pixel row 13 are transferred to the first CCD register 15 via the first barrier gate row 14 and held there. At this time, the first barrier gate row 14 and the first CCD register 15 operate as described later according to the desired resolution.

  Similarly to the above, the signal charges S2, S4,..., S16 photoelectrically converted in each pixel of the second pixel column 21 are accumulated in each pixel. These signal charges are transferred to the storage pixels of the second storage pixel column 23 and held after the second shift gate 22 is opened and transferred to the second shift gate 22. The signal charges held in the second accumulation pixel row 23 are transferred to the second CCD register 25 via the second barrier gate row 24 and held there. At this time, the second barrier gate row 24 and the second CCD register 25 operate as described later according to a desired resolution.

  First, an operation example at the normal resolution will be specifically described with reference to FIG. FIG. 7 shows the shift pulse SH applied to the first and second shift gates 12 and 22, the barrier gates BG1, BG2, BG3, BG4, first, The timing of the clock pulses P1, P2, PA, PB applied to the second CCD registers 15 and 25, the reset pulse RS applied to the reset drain region 26, and the voltage waveform of the signal output are shown.

  At the normal resolution, the signal charges S1, S3,..., S15 and S2, S4,..., S16 held in the respective storage pixels of the first and second storage pixel columns 13 and 23 are the first and second signals. The data are sequentially transferred to and held by the first and second CCD registers 15 and 25 via the barrier gates BG1, BG2, BG3, and BG4 of the barrier gate rows 14 and 24, respectively. The signal charges held in the first and second CCD registers 15 and 25 are sequentially transferred by the respective CCD registers and transferred from the transfer electrode at the final stage to the floating diffusion region 6. The signal charges S1, S3,..., S15 and S2, S4,..., S16 transferred to the floating diffusion region 6 are converted into signal voltages and output to the outside. It is done.

  Specifically, first, the barrier gates BG1 of the first and second barrier gate rows 14 and 24 are set to “High”, the signal charges S1 and S9 are transferred to the first CCD register 15, and the signal charges S2 and S10 are transferred to the first CCD register 15. Each of the data is transferred to and held in the second CCD register 25. Furthermore, these signal charges are sequentially transferred by the first and second CCD registers 15 and 25, and are alternately transferred from the final transfer electrode to the floating diffusion region 6. Next, the barrier gate BG2 of the first and second barrier gate rows 14 and 24 becomes "High", the signal charges S3 and S11 are in the first CCD register 15, and the signal charges S4 and S12 are in the second CCD. It is transferred to the register 25 and held. Furthermore, these signal charges are sequentially transferred by the first and second CCD registers 15 and 25, and are alternately transferred from the final transfer electrode to the floating diffusion region 6. Next, the barrier gate BG3 of the first and second barrier gate rows 14 and 24 becomes "High", the signal charges S5 and S13 are in the first CCD register 15, and the signal charges S6 and S14 are in the second CCD. Each is transferred to and held in the register 25. Furthermore, these signal charges are sequentially transferred by the first and second CCD registers 15 and 25, and are alternately transferred from the final transfer electrode to the floating diffusion region 6. Next, the barrier gates BG4 of the first and second barrier gate rows 14 and 24 become "High", the signal charges S7 and S15 are in the first CCD register 15, and the signal charges S8 and S16 are in the second CCD. Each is transferred to and held in the register 25. These signal charges are sequentially transferred by the first and second CCD registers 15 and 25, and are alternately transferred from the final transfer electrode to the floating diffusion region 6.

  On the other hand, at the time of low resolution (1 / 2n: n is an integer), signal charges held in a plurality of adjacent storage pixels in the first storage pixel column 13 are converted into the first barrier gate column. The signal charges are simultaneously transferred to the first CCD register 15 via 14, and the plurality of signal charges are added and held in the first CCD register 15. Similarly to the above, signal charges held in a plurality of adjacent storage pixels in the second storage pixel column 23 are simultaneously transferred to the second CCD register 25 via the second barrier gate column 24. The plurality of signal charges are added and held in the second CCD register 25. The signal charges held in the first and second CCD registers 15 and 25 are sequentially transferred by a plurality of transfer electrodes and transferred from the final transfer electrode to the floating diffusion region 6. The signal charge transferred to the floating diffusion region 6 is converted into a signal voltage and output to the outside, and after being rearranged in a predetermined arrangement, an imaging signal is obtained.

  First, an operation example at 1/2 resolution will be specifically described with reference to voltage waveforms shown in FIG. At the time of 1/2 resolution, first, the barrier gate BG1 becomes “High”, and the signal charges S1, S9 are transferred to and held in the transfer electrode to which the clock pulse P1 of the first CCD register 15 is applied, and the signal charge S2 , S10 is transferred to and held in the transfer electrode to which the clock pulse P1 of the second CCD register 25 is applied. The signal charges S1 and S9 held on the transfer electrode of the first CCD register 51 are sequentially transferred by a plurality of transfer electrodes and transferred from the final transfer electrode to the floating diffusion region 6. On the other hand, the signal charges S2 and S10 held in the transfer electrode to which the clock pulse P1 of the second CCD register 25 is applied are discharged to the reset drain region 26 while being sequentially transferred by the transfer electrodes of a plurality of stages. The

  Next, the barrier gate BG2 becomes “High”, the signal charges S3 and S11 are transferred to and held in the transfer electrode to which the clock pulse P1 of the first CCD register 15 is applied, and the signal charges S4 and S12 are second. The clock pulse P1 of the CCD register 25 is transferred to and held by the transfer electrode to which it is applied. The signal charges S3 and S11 held on the transfer electrodes of the first CCD register 15 are sequentially transferred by a plurality of transfer electrodes and transferred from the final transfer electrode to the floating diffusion region 6, but the second CCD. The signals S4 and S12 held in the transfer electrode of the register 25 are discharged to the reset drain region 26 while being sequentially transferred by the transfer electrodes of a plurality of stages.

  Next, the barrier gate BG3 becomes “High”, the signal charges S5 and S13 are transferred to and held in the transfer electrode to which the clock pulse P2 of the first CCD register 15 is applied, and the signal charges S6 and S14 are second. The clock pulse P2 of the CCD register 25 is transferred to and held by the clock electrode to which it is applied. The signal charges S5 and S13 held by the transfer electrodes of the first CCD register 15 are sequentially transferred by a plurality of transfer electrodes and transferred from the final transfer electrode to the floating diffusion region 6, but the second CCD. The signals S6 and S14 held in the transfer electrode of the register 25 are discharged to the reset drain region 26 while being sequentially transferred by the transfer electrodes of a plurality of stages.

  Next, the barrier gate BG4 becomes “High”, the signal charges S7 and S15 are transferred to and held in the transfer electrode to which the clock pulse P2 of the first CCD register 15 is applied, and the signal charges S8 and S16 are second. The clock pulse P2 of the CCD register 25 is transferred to and held by the transfer electrode. The signal charges S7 and S15 held at the transfer electrode of the first CCD register 15 are transferred from the transfer electrode at the final stage to the floating diffusion region 6, but the signals held at the transfer electrode of the second CCD register 25 are transferred. S8 and S16 are discharged to the reset drain region 26 while being sequentially transferred by a plurality of stages of transfer electrodes.

  Next, an example of operation at 1/4 resolution will be specifically described with reference to voltage waveforms shown in FIG. At 1/4 resolution, the barrier gates BG1 and BG2 are simultaneously set to “High”, and the signal charges S1 and S3, S9 and S11, and S2 and S4, and S10 and S12 pass through the barrier gates BG1 and BG2. 1 is transferred to the transfer electrode to which the clock pulse P1 of the CCD register 15 is applied and the transfer electrode to which the clock pulse P1 of the second CCD register 25 is applied, and is added to each other, and the signal charges (S1 + S3) and (S9 + S11), and (S2 + S4) and (S10 + S12) are obtained. The signal charges (S1 + S3) and (S9 + S11) held by the transfer electrode of the first CCD register 15 are sequentially transferred by a plurality of transfer electrodes and transferred from the final transfer electrode to the floating diffusion region 6. However, the signal charges (S2 + S4) and (S10 + S12) held by the transfer electrodes of the second CCD register 25 are discharged to the reset drain region 26 while being sequentially transferred by a plurality of transfer electrodes. Is done.

  Next, the barrier gates BG3 and BG4 simultaneously become "High", and the signal charges S5 and S7, S13 and S15, S6 and S8, and S14 and S16 pass through the barrier gates BG3 and BG4 to the first CCD register. 15 are transferred to the transfer electrode to which the clock pulse P2 is applied and the transfer electrode to which the clock pulse P2 of the second CCD register 25 is applied, and are added, respectively, and signal charges (S5 + S7) and (S13 + S15), And (S6 + S8) and (S14 + S16) are obtained. The signal charges (S5 + S7) and (S13 + S15) held by the transfer electrode of the first CCD register 51 are sequentially transferred by a plurality of transfer electrodes and transferred from the final transfer electrode to the floating diffusion region 6. However, the signal charges (S6 + S8) and (S14 + S16) held by the transfer electrodes of the second CCD register 25 are discharged to the reset drain region 26 while being sequentially transferred by a plurality of transfer electrodes. Is done.

  Next, an example of operation at 1/8 resolution will be specifically described with reference to the voltage waveform shown in FIG. At 1/8 resolution, the barrier gates BG3 and BG4 are simultaneously set to "High", and the signal charges S5 and S7, S13 and S15, and S6 and S8, S14 and S16 are passed through the barrier gates BG3 and BG4. , And transferred to the transfer electrode to which the clock pulse P2 of the first CCD register 15 is applied and to the transfer electrode to which the clock pulse P2 of the second CCD register 25 is applied, respectively, and added to the signal charge (S5 + S7). (S13 + S15) and (S6 + S8) and (S14 + S16) are obtained. Next, a clock pulse is applied to the first and second CCD registers 15 and 25, and the signal charge is moved by one stage from the transfer electrode to which the clock pulse P2 is applied to the transfer electrode to which the clock pulse P1 is applied. . Next, the barrier gates BG1 and BG2 simultaneously become “High”, and the signal charges S1 and S3, S9 and S11, S2 and S4, and S10 and S12 pass through the barrier gates BG1 and BG2 to the first CCD register. 15 transfer pulses to which the clock pulse P1 is applied and the transfer electrode to which the clock pulse P1 of the second CCD register 25 is applied are transferred and added to each other, and signal charges (S1 + S3 + S5 + S7 + S9 + S11) + S13 + S15), (S2 + S4 + S6 + S8 + S10 + S12 + S14 + S16).

  The signals (S1 + S3 + S5 + S7 + S9 + S11 + S13 + S15) held at the transfer electrode of the first CCD register 15 are sequentially transferred by a plurality of transfer electrodes and floating from the last transfer electrode. The signal charges (S2 + S4 + S6 + S8 + S10 + S12 + S14 + S16), which are transferred to the diffusion region 6 but held by the transfer electrodes of the second CCD register 25, are sequentially transferred by a plurality of transfer electrodes. It is discharged to the reset drain region 26 during the transfer.

  According to the above-described line sensor according to the second embodiment, the storage pixel column having the pixel structure is arranged adjacent to the shift gate. Then, “High” level timing control and “Low” level negative potential setting of the shift pulse applied to the shift gate are performed. As a result, the dark current and its fluctuation generated during the signal charge holding period in the shift gate and the storage pixel column before being transferred to the CCD register are suppressed, and the control for preventing the vertical stripe in the image is simplified. Can be

  In addition, at low resolution, the number of signal charges that are transferred and added at the same time differs depending on the resolution. However, by adding signal charges using a CCD register, high-speed operation is possible without changing the clock frequency from that at normal resolution. Thus, it is possible to read out the signal charge. Therefore, a long sampling period (signal reference period, signal period) can be secured, and an effect of improving sensitivity by addition can be obtained.

  Further, since the dark output component (noise component) generated in the CCD register is not added, the S / N ratio is improved. Further, since the signal charge can be held in the storage pixel column, the number of transfer stages of the CCD register can be reduced, the signal charge can be transferred with a low clock amplitude, and the output timing can be realized in the same manner as in the existing system.

FIG. 3 is a plan view showing an example of a pattern arrangement by extracting a part of the line sensor according to the first embodiment of the solid-state imaging device of the present invention. The figure which shows an example of the cross-section in the cross section which follows the BB 'line in FIG. 1, and the electric potential distribution of a semiconductor substrate. The wave form diagram which shows the operation example at the time of normal resolution in the line sensor of FIG. The wave form diagram which shows the operation example at the time of 1/2 resolution in the line sensor of FIG. The wave form diagram which shows the operation example at the time of 1/4 resolution in the line sensor of FIG. FIG. 6 is a plan view showing an example of a pattern arrangement by extracting a part of a line sensor according to a second embodiment of the solid-state imaging device of the present invention. FIG. 7 is a waveform diagram showing an operation example at normal resolution in the line sensor of FIG. 6. FIG. 7 is a waveform diagram showing an operation example at 1/2 resolution in the line sensor of FIG. 6. FIG. 7 is a waveform diagram showing an operation example at 1/4 resolution in the line sensor of FIG. 6. The wave form diagram which shows the operation example at the time of 1/8 resolution in the line sensor of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel row, 2 ... Shift gate, 3 ... Storage pixel row, 4 ... Barrier gate row, 5 ... CCD register, 6 ... Floating diffusion area, 11 ... First pixel row, 12 ... First shift gate, 13 ... 1st accumulation pixel row, 14 ... 1st barrier gate row, 15 ... 1st CCD register, 21 ... 2nd pixel row, 22 ... 2nd shift gate, 23 ... 2nd accumulation pixel row, 24 ... second barrier gate row, 25 ... second CCD register, 26 ... reset drain region.

Claims (5)

A pixel row in which pixels having photoelectric conversion portions are arranged in a row;
A shift gate that is arranged in parallel with the pixel column, to which a shift pulse is applied, and that controls the passage of a signal charge amount generated in the pixel column;
An accumulation pixel column that is arranged in parallel with the shift gate, and in which the accumulation pixels that hold the signal charges transferred through the shift gate are arranged in a row;
A barrier gate row in which timing control is performed so as to control a signal charge holding time in the storage pixel row;
A CCD register that is arranged in parallel adjacent to the barrier gate row and has a plurality of transfer electrodes that sequentially transfer signal charges transferred from the barrier gate row in a predetermined direction;
A solid-state imaging device, wherein signal charges from one or two or more different accumulation pixels are transferred to one transfer electrode of the CCD register according to resolution.   2. The solid-state imaging device according to claim 1, wherein the shift gate allows a signal charge to pass while the shift pulse is at a high level, and the low level period of the shift pulse is set to a negative potential. The solid-state imaging device according to claim 1, wherein the storage pixel column has a P ⁺ NP semiconductor structure.   The barrier gate array simultaneously transfers signal charges from two adjacent storage pixels to the CCD register at the time of resolution for adding two pixels, and simultaneously transfers signal charges from two adjacent storage pixels at the resolution of adding four pixels. Is transferred to the CCD register, then the signal charge for two pixels is transferred by one transfer electrode by the CCD register, and then the signal charge for the remaining two pixels is transferred from the storage pixel to the CCD register. The solid-state imaging device according to any one of claims 1 to 3.   5. The solid-state imaging device according to claim 1, wherein the CCD register adds signal charges transferred from the two or more different accumulation pixels to one transfer electrode. 6.

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