JP2014216978A - Solid-state imaging device and imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To acquire a suitable image signal by suppressing influences to be exerted upon an accumulation signal by capacitive coupling which is formed between neighboring pixel rows in a solid-state imaging device where a plurality of pixel parts are arrayed in a two-dimensional shape, each pixel part including a photoelectric conversion part which is irradiated with light to generate electric charge.SOLUTION: When implementing a charge accumulation read-out operation for discharging signal charge accumulated in an accumulation part FD and reading out the signal charge accumulated in the accumulation part FD after the lapse of a charge accumulation period after the discharge, before the discharge in each row, previous discharge is implemented at least twice for discharging the electric charge from the accumulation part in an auxiliary manner and first previous discharge for an (n+1)th row is implemented before discharge of an n-th row ((n) is a natural number). Before the first previous discharge for the n-th row which is implemented just before the discharge of the n-th row, second previous discharge for the (n+1)th row.

Description

  The present invention relates to a solid-state imaging device including a photoelectric conversion unit that generates charges when irradiated with light, and an imaging apparatus including the solid-state imaging device.

  In recent years, in order to cope with high sensitivity and pixel miniaturization of solid-state imaging devices, a photoelectric conversion unit including a pair of electrodes and a photoelectric conversion layer sandwiched between these electrodes is provided above the silicon substrate, and generated in this photoelectric conversion layer A photoelectric conversion layer stacked type solid-state imaging device is drawing attention, in which a stored charge is transferred from one of the pair of electrodes to a silicon substrate and accumulated, and a signal corresponding to the accumulated charge is read by a signal readout circuit formed on the silicon substrate. ing.

  As such a solid-state imaging device, for example, in Patent Document 1, as shown in FIG. 11, a photoelectric conversion unit 201 and a floating diffusion FD (hereinafter simply referred to as FD) that accumulates charges generated in the photoelectric conversion unit 201. The output transistor 202 that outputs a voltage corresponding to the charge accumulated in the FD, the reset transistor 203 that resets the charge accumulated in the FD, and the signal output from the output transistor 202 are selectively output to the signal line. A solid-state imaging device has been proposed in which a large number of pixel portions 200 each including a selection transistor 204 are two-dimensionally arranged. This solid-state imaging device is a circuit having a so-called three-transistor structure in which no transistor is provided between the FD and the photoelectric conversion unit 201, and the FD and the photoelectric conversion unit 201 are electrically connected directly. is there.

  Here, in the solid-state imaging device as described above, the discharge and charge signal readout operations are sequentially performed for each row of the pixel unit 200. FIG. 12 shows the timing of the discharge operation and the charge signal reading operation of the pixel portion 200 in the nth to n + 2th rows.

  As shown in FIG. 12, at the start of the accumulation period, unnecessary charges are first discharged. The discharge is performed when the reset transistor 203 of the pixel portion 200 is turned on by the reset pulse RS and the charge accumulated in the FD is reset.

When the reset transistor 203 is turned off and discharging is completed, accumulation of electric charges in the FD starts from this point. When a predetermined charge accumulation period elapses, a selection pulse RW is output to the pixel portion 200, and the selection transistor 204 is turned on by this selection pulse RW, whereby the charge signal accumulated in the FD is output by the output transistor 202. It is converted into a voltage signal and output to the signal line as an accumulated signal. After that, the reset transistor 203 is turned on to reset the FD, and the reset potential of the FD is output to the signal line as a reset signal. By using the difference between the accumulated signal and the reset signal as an image signal, it is possible to acquire an image with less fixed pattern noise.

  As described above, the discharge operation for each row of the pixel unit 200 and the readout operation of the charge signal are sequentially scanned in the column direction of the pixel unit 200, whereby one frame of image signal is acquired.

JP 2011-54746 A International Publication No. 2012/137445

  Here, in the solid-state imaging device as described above, as shown in FIG. 11, due to parasitic capacitances such as the wiring of the pixel portion and the impurity region of the substrate, the capacitance cup between adjacent pixel portions 200 in different rows. A ring will occur. In particular, when the pixel portion is further miniaturized, the original capacitance of the pixel portion is reduced, and the layout is more severely limited. Therefore, the influence of capacitive coupling is inevitably increased.

  In particular, in the above-described three-transistor configuration, an FD is required for each pixel, and since no transistor is provided between the FD and the photoelectric conversion unit 201, the adjacent pixel units are electrically connected. The effect of capacitive coupling between 200 FDs tends to increase. This effect will be described.

  FIG. 13 shows drive and FD potential change with time when imaging is performed under the condition that uniform light is incident on all pixels in the solid-state imaging device shown in FIG. The solid line represents an ideal FD potential when there is no capacitive coupling, and the broken line represents a change in the potential of the FD when affected by capacitive coupling. The change in the FD potential of the pixel of interest with the change in the FD potential of the adjacent pixel is a feature when there is an influence of capacitive coupling.

  Each row discharges charges accumulated in the FD until the time of discharge in the drawing, and reads out signal charges accumulated in the FD during the accumulation period from discharge to read at the time of reading. Here, paying attention to the (n + 1) th row, the signal reading is completed at the time t1, and the potential of the FD becomes the reference potential. Thereafter, discharging is performed at time t2, accumulation is started after the potential of FD is set to the reference potential. Then, reading is performed at time t5, and a signal corresponding to the signal charge accumulated in the FD between time t2 and time t5 is output.

  On the other hand, when attention is paid to the n-th row, discharge is performed at time t3 before time t2, and accumulation is started. Then, reading is performed at time t4 after time t2. That is, the n + 1th row is discharged during the accumulation period of the nth row (between t3 and t4).

  Here, when the capacitive coupling between the n-th row and the n + 1-th row is large, the FD potential of the n-th row also changes with a large change in the FD potential of the (n + 1) -th row at time t2. When there is no capacitive coupling, the FD potential changes monotonously from time t3 to time t4, whereas when the capacitive coupling is large, the FD potential changes monotonically from time t3 to time t2, and then at time t2. The potential decreases once, and the FD potential increases from the potential by accumulation of signal charges until time t4. For this reason, when the signal in the n-th row is read at time t4, the signal level is lower than the original signal level as indicated by the dotted line, compared to the original signal level indicated by the solid line.

  Such an abnormality in the signal level is more conspicuous as the potential change when discharging is larger than the signal to be read. For this reason, this effect becomes more conspicuous as the light incident on the solid-state imaging device is larger and the accumulation period is shorter than the frame period. As a result, problems such as a decrease in S / N when the signal amount is small and a decrease in signal linearity with respect to the exposure period are caused.

  For example, in the solid-state imaging device described above, when a Bayer color filter is provided, red filters (R) and green filters (G) are alternately arranged in the column direction of the pixel unit 200. There will be a column of pixel portions and a column of pixel portions in which blue filters (B) and green filters (G) are alternately arranged.

  When such a solid-state imaging device is irradiated with Y light including R light and G light, the pixel unit 200 provided with the green filter is arranged in the same column as the pixel unit 200 provided with the red filter. In some cases, as shown in the upper part of FIG. 14, the discharge of the pixel unit 200 provided with the red filter reduces the potential of the FD of the pixel unit 200 provided with the green filter, and the magnitude of the charge signal G1. Will be smaller.

  On the other hand, when the pixel unit 200 provided with the green filter is in the same column as the pixel unit 200 provided with the blue filter, as shown in the lower part of FIG. Since no light is incident and the potential of the FD does not change, the discharge of the pixel portion 200 provided with the blue filter does not affect the potential of the FD of the pixel portion 200 provided with the green filter. A charge signal G2 larger than the charge signal G1 is acquired.

  That is, since the sensitivity of the pixel unit 200 provided with the green filter varies depending on the column of the pixel unit 200, the color balance is different from the original, and an appropriate image signal cannot be acquired.

  For example, in the solid-state imaging device described above, an afterimage is generated due to capacitive coupling. This effect will be described with reference to FIG.

  First, a case will be described in which 10,000 electrons are accumulated in the FD before discharge of each row and the coupling rate of adjacent rows is 1%. Note that the coupling rate is the degree of influence of a potential change between FDs of adjacent pixel portions 200. For example, when the coupling rate is 1%, the signal changes by 1% when the signal of the adjacent pixel changes. The coupling rate is determined by the ratio between the parasitic capacitance and the storage capacitance of the FD. The smaller the size of the pixel portion 200, the lower the degree of freedom of layout and the higher the coupling rate.

  First, 10,000 electrons accumulated in the FD of the n-th row by discharging the n-th row become zero. However, due to the subsequent discharge of the FD of the (n + 1) th row, the FD of the nth row is affected by the capacitive coupling, and 10000 electrons accumulated in the FD of the (n + 1) th row become zero. Accordingly, the potential corresponds to 1% of the number of (0-10000) electrons. That is, the FD in the nth row has a potential corresponding to −100 electrons. Then, since reading of the nth row is performed, a black sun afterimage corresponding to −100 electrons is generated from the nth row. Similarly, a black sun afterimage corresponding to −100 electrons is generated in the (n + 1) th row. In this way, an afterimage of accumulated charge amount × (−coupling ratio) occurs due to capacitive coupling between adjacent pixel rows.

  Therefore, in order to suppress the influence of capacitive coupling between adjacent pixel rows as described above, for example, as described in Patent Document 2, preliminary discharge, which is preliminary charge discharge, is performed before the discharge operation of each row. Can be considered. Hereinafter, an operation when this preliminary discharge is performed will be described.

  FIG. 16 shows the operation timing in the case of performing preliminary discharge on the (n + 1) th row before discharge on the nth row. As shown in FIG. 16, when the n + 1th row preliminary discharge is performed before the nth row discharge, the FD potential change at the time of the n + 1th row discharge is performed by performing the n + 1th row preliminary discharge. Since the size can be reduced, the influence of the discharge of the (n + 1) th row on the accumulated signal of the nth row can be reduced. Hereinafter, this effect will be described quantitatively with reference to FIG.

  First, a case where 10,000 electrons are accumulated in the FD before the preliminary discharge of each row and the coupling rate of the adjacent row is 1% will be described.

  First, 10,000 electrons accumulated in the FD of the (n + 1) th row by the preliminary discharge of the (n + 1) th row become zero. However, due to the preliminary discharge of the FD in the n + 2 row that is executed next, the FD in the n + 1 row is affected by the capacitive coupling, and the 10000 electrons accumulated in the FD in the n + 2 row become 0. Accordingly, the potential corresponds to -1% of the number of electrons of 10,000 electrons. That is, the FD in the (n + 1) th row has a potential corresponding to −100 electrons. In this state, when the (n + 1) th row is discharged next, the −100 electrons accumulated in the FD of the (n + 1) th row are affected by the capacitive coupling due to the discharge. A potential fluctuation corresponding to -1% of the number of electrons occurs. That is, an offset potential corresponding to one electron is added to the charge signal accumulated after the nth row is discharged.

  In this way, when the coupling rate is about 1% and is relatively low, an offset potential corresponding to one electron is only added to 10,000 stored signals, so FIG. If preliminary discharge is performed at the timing as shown, the influence of capacitive coupling between adjacent pixel rows can be sufficiently suppressed.

  However, when the coupling rate is relatively high, the above-described offset potential may become large and cause a problem. For example, the case where the coupling rate is 5% will be described with reference to FIG.

  First, 10,000 electrons accumulated in the FD of the (n + 1) th row by the preliminary discharge of the (n + 1) th row become zero. However, due to the preliminary discharge of the FD in the n + 2 row that is executed next, the FD in the n + 1 row is affected by the capacitive coupling, and the 10000 electrons accumulated in the FD in the n + 2 row become 0. Accordingly, the potential corresponds to −5% of the 10,000 electrons. That is, the FD in the (n + 1) th row has a potential corresponding to −500 electrons. Then, when the (n + 1) th row is discharged in this state, -500 electrons accumulated in the FD of the (n + 1) th row are affected by the capacitive coupling due to this discharge. A potential fluctuation corresponding to -5% of the number of electrons occurs. That is, an offset potential corresponding to 25 electrons is added to the charge signal accumulated after the nth row is discharged. Considering that generally the allowable range of noise is a potential fluctuation corresponding to 3 electrons, the offset potential corresponding to 25 electrons is very large and causes a problem.

That is, as shown in FIG. 15, even when the preliminary discharge of the (n + 1) th row is performed before the discharge of the nth row, as a result, the “discharged charge at the time of preliminary discharging” The quantity × (−coupling rate) ² ”is added as an offset, and cannot be ignored when the coupling rate is high.

  In view of the above circumstances, the present invention includes a solid-state imaging device capable of sufficiently suppressing the influence even when a capacitive coupling formed between adjacent pixel rows is relatively large, and the solid-state imaging device. An object is to provide an imaging device.

  The solid-state imaging device of the present invention includes a photoelectric conversion unit that generates a signal charge corresponding to the amount of incident light, a storage unit that stores the signal charge generated in the photoelectric conversion unit, and a signal charge stored in the storage unit. A signal charge that is stored in the storage unit, and includes a plurality of pixel units that are electrically connected to the photoelectric conversion unit, the power storage unit, and the input node of the output circuit. After the discharge, a charge accumulation read operation for reading the signal charges accumulated in the power storage unit when the charge accumulation period has elapsed is performed in a row sequence, and a preliminary operation from the power storage unit is performed before the discharge in each row. Preliminary discharge is performed at least twice, and the first preliminary discharge of the (n + 1) th row is performed before the discharge of the nth (n is a natural number) row, and the discharge is performed immediately before the discharge of the nth row. N + before the first preliminary discharge in the nth row And characterized in that performing the second preliminary discharge of row.

  In the solid-state imaging device of the present invention, a feedback control circuit that performs feedback control so that the power storage unit becomes a reference potential can be provided for each column of the pixel units.

  Further, the feedback control circuit can perform feedback control at the time of discharging, reading of signal charges, first preliminary discharging, and second preliminary discharging.

  In addition, at least one of the discharge, the reading of signal charges, the first preliminary discharge, and the second preliminary discharge and an operation other than the at least one operation are performed in different rows within one scanning period. Can be done at different times.

  In addition, a timing generator that outputs a pulse signal for controlling the timing of discharge, signal charge readout, first preliminary discharge, and second preliminary discharge is provided, and the timing generator is arranged within the scanning period of one row. A pulse signal for controlling the timing of at least one operation and a pulse signal for controlling the timing of an operation other than the at least one operation can be output at different timings.

  In addition, a shift register for controlling the timing of discharge, signal charge reading, first preliminary discharge, and second preliminary discharge can be provided for each operation.

  Further, the time for the first preliminary discharge or the second preliminary discharge can be made shorter than the discharge time.

  In addition, the pixel portion includes a first electrode partitioned in units of pixels and a second electrode provided to face the pixel electrode with the photoelectric conversion portion interposed therebetween. These pixel portions can be a common electrode.

  Moreover, the photoelectric conversion part can include an organic photoelectric conversion film.

  Further, the organic photoelectric conversion film can be common to all the pixel portions.

  Further, the signal charge from the photoelectric conversion unit can be a hole.

  In addition, the signal charge from the photoelectric conversion unit can be an electron.

  In addition, a protection circuit can be provided in the power storage unit.

  An imaging apparatus according to the present invention includes the solid-state imaging device according to the present invention.

  According to the solid-state imaging device and the imaging apparatus of the present invention, preliminary discharge, which is preliminary charge discharge from the power storage unit, is performed at least twice before discharging in each row, and the nth (n is a natural number) row Before discharge, the first preliminary discharge of the (n + 1) th row is performed, and the second preliminary discharge of the (n + 1) th row is performed before the first preliminary discharge of the nth row performed immediately before the discharge of the nth row. Since this is performed, a change in voltage of the FD in discharging the pixel portion of each row can be reduced. Thereby, for example, even when there is capacitive coupling in the n-th row and the n + 1-th row, the voltage change at the discharge of the n + 1-th row is small, so that the abnormality of the signal in the n-th row due to the capacitive coupling can be reduced. An appropriate image signal can be acquired. The effect of the preliminary discharge will be described in detail later.

The figure which shows the pixel part which comprises one Embodiment of the solid-state image sensor of this invention. Schematic cross-sectional view of an embodiment of a solid-state imaging device of the present invention The figure which shows the whole structure containing the peripheral circuit of the solid-state image sensor shown in FIG. The figure which shows an example of the timing of the 2nd preliminary | backup discharge | emission, 1st preliminary | backup discharge | emission, discharge | emission, and the reading of a charge signal in one Embodiment of the solid-state image sensor of this invention. The figure which shows the electric potential change of FD of the pixel part of each line of nth line-n + 3th line. The figure which shows an example of the relationship between the pulse signal output from a timing generator, and the operation | movement timing in each line of n-1 line-n + 1 line. The figure which shows the other example of the relationship between the pulse signal output from a timing generator, and the operation | movement timing in each line of n-1 line-n + 1 line. The figure which shows the positional relationship of the electrical storage part FD at the time of laying out the readout circuit of a pixel part by mirror image relation The figure which shows the electrical potential change of the electrical storage part FD at the time of only discharging, without performing preliminary discharge in the case of the positional relationship of the electrical storage part FD shown in FIG. The figure which shows the structure which provided the protection circuit in the electrical storage part FD. The figure which shows the structure and capacitive coupling of the pixel part of the conventional solid-state image sensor Timing chart for explaining discharge of conventional solid-state imaging device and reading of charge signal The figure for demonstrating the influence of the capacitive coupling in the conventional solid-state image sensor The figure for demonstrating the influence of the false signal by the capacitive coupling in the conventional solid-state image sensor The figure for demonstrating the influence of the afterimage by the capacitive coupling in the conventional solid-state image sensor The figure which shows an example of the operation timing in the case of performing preliminary discharge of the (n + 1) th row before discharge of the nth row The figure for demonstrating the influence of the afterimage by capacity | capacitance coupling at the time of performing preliminary discharge of the (n + 1) th row before discharge of the nth row The figure for demonstrating the influence of the afterimage by capacity | capacitance coupling at the time of performing preliminary discharge of the (n + 1) th row before discharge of the nth row

  Hereinafter, an embodiment of the solid-state imaging device of the present invention will be described with reference to the drawings. The solid-state imaging device of the present embodiment is characterized by preliminary discharge, which will be described in detail later. First, the configuration of the solid-state imaging device of the present embodiment will be described. FIG. 1 is a diagram illustrating a pixel unit constituting the solid-state imaging device of the present embodiment. The solid-state imaging device of the present embodiment has a large number of pixel portions 10 shown in FIG.

  As shown in FIG. 1, the pixel unit 10 includes a photoelectric conversion unit 11, a floating diffusion FD (corresponding to an accumulation unit) (hereinafter simply referred to as FD), an output transistor 12, a reset transistor 13, and a selection transistor 14. And. The output transistor 12, the reset transistor 13, and the selection transistor 14 are each composed of an n-channel MOS transistor. Note that the size of the pixel portion 10 is desirably 5 μm or less.

  The photoelectric conversion unit 11 includes a pixel electrode 104 (corresponding to the first electrode), a counter electrode 108 (corresponding to the second electrode) provided to face the pixel electrode 104, the pixel electrode 104, and the counter electrode. And a photoelectric conversion layer 107 provided between them.

  The pixel electrode 104 is a thin film electrode divided for each pixel unit 10 and is formed of a transparent or opaque conductive material such as ITO, aluminum, titanium nitride, copper, tungsten, or the like. The pixel electrode 104 collects charges generated in the photoelectric conversion layer 107 for each pixel unit 10.

  The counter electrode 108 is an electrode for applying a voltage to the photoelectric conversion layer 107 between the pixel electrode 104 and generating an electric field in the photoelectric conversion layer 107. Since the counter electrode 108 is provided on the light incident surface side of the photoelectric conversion layer 107 and needs to be transmitted through the counter electrode 108 and incident on the photoelectric conversion layer 107, the counter electrode 108 is transparent to the incident light. It is formed from a conductive material such as ITO. Note that the counter electrode 108 in the present embodiment is configured by one electrode common to all the pixel units 10, but may be configured to be divided for each pixel unit 10.

  The photoelectric conversion layer 107 includes an organic photoelectric conversion film or an inorganic photoelectric conversion film that absorbs incident light and generates charges according to the absorbed light quantity. Note that a function of a charge blocking layer or the like that suppresses charge injection from the electrode to the photoelectric conversion layer 107 between the photoelectric conversion layer 107 and the counter electrode 108 or between the photoelectric conversion layer 107 and the pixel electrode 104. A layer may be provided.

  In the pixel unit 10 of the present embodiment, a bias voltage is applied to the counter electrode 108 so that holes out of the charges generated in the photoelectric conversion layer 107 move to the pixel electrode 104 and electrons move to the counter electrode 108. Applied. As a bias voltage, a voltage higher than the power supply voltage Vdd (a voltage supplied to the drain of the output transistor 12 in FIG. 1, for example, 3 V) is used as a bias voltage so that the photoelectric conversion layer 107 exhibits sufficiently high sensitivity. It is desirable to use about 5-20V, for example 10V).

  The FD is an n-type impurity region that is electrically connected to the pixel electrode 104. Since the potential of the FD changes according to the amount of holes collected by the pixel electrode 104, the FD functions as a charge storage portion.

  The output transistor 12 converts the charge signal accumulated in the FD into a voltage signal and outputs it to the signal line SL. The gate terminal of the output transistor 12 is electrically connected to the FD, and the drain terminal is connected to the power supply voltage Vdd of the solid-state imaging device. The source terminal of the output transistor 12 is connected to the drain terminal of the selection transistor 14. The pixel unit 10 in the present embodiment is a so-called three-transistor circuit in which the FD, the pixel electrode 104 of the photoelectric conversion unit 11, and the gate terminal of the output transistor 12 are directly connected.

  The reset transistor 13 resets the potential of the FD to a reference potential. The FD is electrically connected to the drain terminal of the reset transistor 13 and the feedback control circuit 16 is connected to the source terminal.

  The feedback control circuit 16 includes an inverting amplifier 16a and a voltage source 16b that supplies a reference voltage RD. The signal line SL is connected to the inverting input terminal (−) of the inverting amplifier 16a, the voltage source 16b is connected to the non-inverting input terminal (+), and the feedback line FL is connected to the output terminal. The feedback line FL is connected to the source terminal of the reset transistor 13.

  When the reset pulse RS applied to the gate terminal of the reset transistor 13 becomes a high level, the reset transistor 13 is turned on, and electrons are injected from the source to the drain of the reset transistor 13. Then, due to the injection of electrons, the potential of the FD drops and the potential of the FD is reset to the reference potential. At this time, the potential of the FD is changed via the output transistor 12, the selection transistor 14, and the signal line SL. Input to the feedback control circuit 16.

  Then, based on the current potential of the FD and the reference voltage RD supplied from the voltage source 16b, the feedback control circuit 16 feedback-controls the potential of the FD, whereby the potential of the FD is maintained at a constant reference potential. . Thus, by performing feedback control of the potential of the FD, reset kTC noise of the reset transistor 13 can be reduced.

  One feedback control circuit 16 is provided for each column of the pixel units 10 and is shared by the plurality of pixel units 10 belonging to each column.

  The selection transistor 14 has a source terminal connected to the signal line SL, and selectively outputs a signal output from the output transistor 12 of each pixel unit 10 to the signal line SL provided for each column. belongs to. When the selection pulse RW applied to the gate terminal of the selection transistor 14 becomes a high level, the selection transistor 14 is turned on, whereby a signal output from the output transistor 12 of each pixel unit 10 is output to the signal line SL.

  FIG. 2 is a schematic cross-sectional view of a solid-state imaging device 100 in which a large number of pixel portions 10 shown in FIG. 1 are arranged two-dimensionally. In the following description, the same name and reference numeral are assigned to the same configuration as the pixel unit 10 shown in FIG.

  As shown in FIG. 2, the solid-state imaging device 100 includes a substrate 101, an insulating layer 102, a connection electrode 103, a pixel electrode 104, a connection portion 105, a connection portion 106, a photoelectric conversion layer 107, and a counter electrode. 108, a sealing layer 110, a color filter 111, a light shielding layer 113, a protective layer 114, a counter electrode voltage supply unit 115, and a readout circuit 116.

  The substrate 101 is a glass substrate or a semiconductor substrate such as Si. An insulating layer 102 is formed on the substrate 101. A plurality of pixel electrodes 104 and one or more connection electrodes 103 are formed on the surface of the insulating layer 102.

  The photoelectric conversion layer 107 generates electric charge according to the received light as described above. The photoelectric conversion layer 107 is provided so as to cover the plurality of pixel electrodes 104. The photoelectric conversion layer 107 has a constant film thickness on the pixel electrode 104, but there is no problem even if the film thickness changes outside the pixel portion (outside the effective pixel area).

  The counter electrode 108 is an electrode facing the pixel electrode 104 and is provided so as to cover the photoelectric conversion layer 107. The counter electrode 108 is formed up to the connection electrode 103 arranged outside the photoelectric conversion layer 107 and is electrically connected to the connection electrode 103.

  The connection unit 106 is embedded in the insulating layer 102 and is a plug or the like for electrically connecting the connection electrode 103 and the counter electrode voltage supply unit 115. The counter electrode voltage supply unit 115 is formed on the substrate 101 and applies a predetermined voltage to the counter electrode 108 via the connection unit 106 and the connection electrode 103. Note that the counter voltage supply unit 115 may be configured not directly on the substrate 101 but directly connected to an external power source.

  The read circuit 116 includes the FD, the output transistor 12, the reset transistor 13, and the selection transistor 14 shown in FIG. 1, and is wired by a metal wiring (not shown) in the insulating layer 102. The readout circuit 116 is provided on the substrate 101 corresponding to each of the plurality of pixel electrodes 104, and reads out a signal corresponding to the charge collected by the corresponding pixel electrode 104. Note that the reading circuit 116 is shielded from light by a light shielding layer (not shown) disposed in the insulating layer 102.

  The sealing layer 110 is provided so as to cover the counter electrode 108.

  The color filter 111 is formed at a position facing each pixel electrode 104 on the sealing layer 110. The light shielding layer 113 is formed in a region other than the region where the color filter 111 is provided on the sealing layer 110, and prevents light from entering the photoelectric conversion layer 107 formed outside the effective pixel region. As the color filter 111, for example, a Bayer color filter can be used. However, the color filter is not limited to this, and a complementary color filter or other known color filters can be used.

  The protective layer 114 is formed on the color filter 111 and the light shielding layer 113, and protects the entire solid-state imaging device.

  FIG. 3 is a diagram showing an overall configuration including peripheral circuits of the solid-state imaging device 100 shown in FIG. As shown in FIG. 3, the solid-state imaging device 100 according to the present embodiment includes a vertical driver 121, a control unit 122, a signal processing circuit 123, a horizontal driver 124, an LVDS 125, a serial conversion unit 126, and a pad 127. It has. The pixel area shown in FIG. 3 represents an area where the pixel portions 10 of the solid-state imaging device 100 shown in FIG. 2 are arranged.

  In the pixel region, a signal line SL for outputting a signal from the output transistor 12 of each pixel unit 10 and the feedback line FL described above are provided for each column of the pixel unit 10, and a switching pulse signal is output from the vertical driver 121. A scanning line GL is provided for each row. As described above, the feedback control circuit 16 is provided for each column of the pixel unit 10.

  The control unit 122 includes a timing generator (hereinafter referred to as TG) 128 and the like, outputs a frame synchronization signal VD and a row synchronization signal HD, and controls operations of the vertical driver 121 and the horizontal driver 124. It controls the readout of charge signals in the pixel unit 10.

  The vertical driver 121 outputs a reset pulse RS and a selection pulse RW to the reading circuit 116 via the scanning line GL based on the timing pulse signal output from the TG 128 of the control unit 122, and performs the operation of the reading circuit 116. It is something to control.

  In particular, the vertical driver 121 of the present embodiment performs a preliminary discharge, which is a preliminary charge discharge from the FD, twice before discharging the accumulated charge in the so-called conventional FD. Is to control.

  Based on the timing pulse signal output from the TG 128, the vertical driver 121 outputs a selection shift register 130 that outputs a selection pulse RW and a reset pulse RS for reading a charge signal, and a selection pulse RW and a reset for discharge. The discharge shift register 131 that outputs the pulse RS, the first preliminary discharge shift register 132 that outputs the selection pulse RW and the reset pulse RS during the first preliminary discharge, and the selection during the second preliminary discharge And a second preliminary discharge shift register 133 that outputs a pulse RW and a reset pulse RS. Note that the timing of the selection pulse RW and the reset pulse RS output from the shift registers 130 to 133 will be described in detail later.

  The signal processing circuit 123 is provided corresponding to each column of the reading circuit 116. The signal processing circuit 123 includes an ADC circuit that performs correlated double sampling (CDS) processing on the signals output from the corresponding columns and converts the processed signals into digital signals. The signal processed by the signal processing circuit 123 is stored in a memory provided for each column.

  The horizontal driver 124 performs control for sequentially reading out signals for one row of the pixel unit 10 stored in the memory of the signal processing circuit 123 and outputting the signals to the LVDS 125.

  The LVDS 125 transmits a digital signal in accordance with LVDS (low voltage differential signaling). The serial conversion unit 126 converts an input parallel digital signal into a serial signal and outputs it. The pad 127 is an interface used for input / output with the outside.

  Next, the operation of the solid-state imaging device 100 of this embodiment will be described.

  In the solid-state imaging device 100 of the present embodiment, the second preliminary discharge, the first preliminary discharge, the discharge, and the charge signal reading operation are sequentially performed for each row of the pixel unit 10. In addition, the second preliminary discharge, the first preliminary discharge, the discharge, and the charge signal reading operation for each row of the pixel unit 10 are sequentially scanned in the column direction of the pixel unit 10.

  FIG. 4 shows an example of timings of second preliminary discharge, first preliminary discharge, discharge, and charge signal readout in the nth row (n is a natural number) to the n + 3th row of the solid-state imaging device 100 of the present embodiment. . As described above, in the solid-state imaging device 100 according to the present embodiment, the second preliminary discharge, the first preliminary discharge, the discharge, and the readout of the charge signal are performed in the row order for each of the nth to n + 3th rows. .

  Here, a specific operation of the reading circuit 116 in the above-described second preliminary discharge, first preliminary discharge, discharge, and reading will be described.

  At the time of the second preliminary discharge, the reset pulse RS and the selection pulse RW for the second preliminary discharge are output from the second preliminary discharge shift register 133 of the vertical driver 121 to each row. Then, the reset transistor 13 of the pixel unit 10 is turned on by the reset pulse RS and the selection transistor 14 of the pixel unit 10 is turned on by the selection pulse RW. As a result, the FD is connected to the feedback control circuit 16 via the selection transistor 14, and the potential of the FD is feedback-controlled by the feedback control circuit 16 and reset to the reference potential.

  Next, at the time of the first preliminary discharge, the reset pulse RS and the selection pulse RW for the first preliminary discharge are output from the first preliminary discharge shift register 132 of the vertical driver 121 to each row. The Then, similarly to the second preliminary discharge, the reset transistor 13 of the pixel unit 10 is turned on by the reset pulse RS, the selection transistor 14 of the pixel unit 10 is turned on by the selection pulse RW, and the potential of the FD is feedback controlled again. And reset to the reference potential.

  Next, at the time of discharge, a discharge reset register RS and a selection pulse RW are output from the discharge shift register 131 of the vertical driver 121 to each row. Similarly to the first and second preliminary discharges, the reset transistor 13 of the pixel unit 10 is turned on by the reset pulse RS, and the selection transistor 14 of the pixel unit 10 is turned on by the selection pulse RW. The potential is feedback controlled and reset to the reference potential.

  Next, after a discharge is performed as described above, a selection pulse RW is output to each row from the read shift register 130 of the vertical driver 121 when a predetermined charge accumulation period has elapsed. Then, the selection transistor 14 is turned on by this selection pulse RW, whereby the charge signal stored in the FD is converted into a voltage signal by the output transistor 12 and output as a storage signal to the signal line SL.

  Thereafter, a reset pulse RS is output from the readout shift register 130 to each row, and the reset transistor 13 of the pixel portion 10 is turned on by this reset pulse RS, and the potential of the FD is again feedback controlled to be reset to the reference potential. . Then, a signal immediately after the reset transistor 13 is turned off and the reset is completed is output to the signal line SL as a reset signal. The signal processing circuit 123 calculates the difference between the accumulated signal and the reset signal, and using this difference as an image signal makes it possible to acquire an image with less fixed pattern noise and reset kTC noise.

  As described above, in the present embodiment, feedback control is performed in any of the second preliminary discharge, the first preliminary discharge, and the discharge, but the reference is made so that no offset is added to the charge signal in the discharge. While it is necessary to perform feedback control so as to be as close to the potential as possible, the second preliminary discharge or the first preliminary discharge is performed after that, and thus it is allowed even if it is slightly deviated from the reference potential. it can. Accordingly, the feedback control time for the second preliminary discharge or the first preliminary discharge may be set shorter than the time for the feedback control for discharge. Thereby, the discharge time and the read time can be set longer, and the S / N of the image signal can be improved. Note that the feedback control time can be controlled by adjusting the ON time of the reset pulse RS and the selection pulse RW.

  Next, the second preliminary discharge, the first preliminary discharge, the discharge and the charge signal reading operation timing in each of the nth to n + 3th rows and the potential change of the FD of the pixel portion 10 in each row will be described.

  In the solid-state imaging device 100 of the present embodiment, as shown in FIG. 4, the first preliminary discharge of the (n + 1) th row is performed before the discharge of the nth row and the first preliminary discharge of the nth row is performed. And the second preliminary discharge in the (n + 1) th row is controlled. Similarly, the first preliminary discharge of the (n + 2) th row is performed before the discharge of the (n + 1) th row, and the second preliminary discharge of the (n + 2) th row is performed before the first preliminary discharge of the (n + 1) th row. So that the first preliminary discharge in the (n + 3) th row is performed before the discharge in the (n + 2) th row, and the second preliminary discharge in the (n + 3) th row is performed before the first preliminary discharge in the (n + 2) th row. Be controlled.

  That is, in the period between the first preliminary discharge and the discharge of a predetermined row, the first preliminary discharge of the next row is performed, and the first preliminary discharge and the second preliminary discharge of the predetermined row are Control is performed so that the second preliminary discharge of the next row is performed during the interval.

  FIG. 5 shows the potential change of the FD of the pixel portion 10 in each row when the timing of each operation in each row is controlled as described above.

  Here, uniform light is irradiated to the solid-state imaging device 100 by the LED at time t0, and 10000 electrons are accumulated in the FD before the preliminary discharge of each row, and the coupling rate of adjacent rows is The case of 5% will be described.

  First, 10,000 electrons accumulated in the FD of the nth row by the second preliminary discharge of the nth row become zero. However, due to the second preliminary discharge of the FD of the (n + 1) th row to be executed next, the FD of the nth row is affected by the capacitive coupling, and 10000 electrons accumulated in the FD of the (n + 1) th row are reduced to 0. As the number of electrons increases, the potential corresponds to -5% of the number of electrons of 10,000 electrons. That is, the FD in the n-th row has a potential corresponding to −500 electrons.

  Next, by the first preliminary discharge in the n-th row, the potential of the FD in the n-th row is changed from a potential corresponding to −500 electrons to a potential corresponding to 0 electrons, that is, a reference potential. However, due to the first preliminary discharge of the FD of the (n + 1) th row to be executed next, the FD of the nth row is affected by the capacitive coupling, and the potential of the FD of the (n + 1) th row corresponds to −500 electrons. As the potential changes from the potential to the reference potential, the potential corresponds to −5% of the −500 electrons. That is, the FD in the nth row has a potential corresponding to 25 electrons.

  Next, by discharging the nth row, the potential of the FD of the nth row changes from the potential corresponding to 25 electrons to the reference potential. Then, accumulation of signal charges is started from the start of the discharge. At this time, the n + 1-th row FD is discharged, and the n-th row FD is affected by the capacitive coupling, so that the potential of the n + 1-th row FD changes from the potential corresponding to 25 electrons to the reference potential. As a result, potential fluctuation corresponding to −5% of the 25 electrons occurs. That is, an offset potential corresponding to −1.25 electrons is added to the charge signal accumulated after the nth row is discharged.

  Thus, even when the coupling rate is about 5% and relatively high, the offset potential corresponding to −1.25 electrons can be suppressed with respect to 10,000 accumulated signals.

  That is, the first preliminary discharge in the (n + 1) th row is performed before the discharge in the nth row, and the second preliminary discharge is performed before the first preliminary discharge in the nth row. The potential can be made sufficiently small.

  The above description centered on the FD potential change of the pixel unit 10 in the n-th row, but the same applies to the (n + 1) -th to n + 3-th rows.

In the present embodiment, the preliminary discharge is performed twice before the discharge of each row. However, the preliminary discharge is not limited to two times, and may be performed three times or more. By performing preliminary discharge j times, the influence of the capacitive coupling of the optical signal charge of a predetermined frame can be set to (−coupling ratio) ^{(j + 1)} . For example, if the optical signal charge of the frame is a size corresponding to 100,000 electrons and the coupling rate is 10%, if preliminary discharge is performed four times, 100,000 × (−0 .1) ⁵ = −1, which can be suppressed to an offset potential corresponding to −1 electron.

  As described above, the effect of the present invention increases as the coupling rate increases. In particular, when the size of the pixel portion 10 is 5 μm or less, the coupling rate increases to a degree that cannot be ignored. It is remarkable.

  In addition, even when a color filter such as a Bayer array is provided for the solid-state imaging device as described above, the sensitivity of the pixel unit provided with the green filter does not differ depending on the column of the pixel unit. Color balance image signals can be acquired.

  Next, the operation of the TG 128 of the control unit 122 for performing the second preliminary discharge, the first preliminary discharge, the discharge, and the reading as described above will be described. The TG 128 periodically outputs a pulse signal in accordance with the timing of the second preliminary discharge, the first preliminary discharge, the discharge and the reading of each row. As described above, the pulse signal output from the TG 128 is input to the read shift register 130, the discharge shift register 131, the first preliminary discharge shift register 132, and the second preliminary discharge shift register 133. Each shift register outputs a reset pulse RS and a selection pulse RW to each row at a preset timing based on the input pulse signal.

  FIG. 6 shows the relationship between the pulse signal output from the TG 128 and the operation timing in each of the n−1 to n + 1 rows. In FIG. 6, it is assumed that time elapses from left to right in the upper stage and then elapses from left to right in the lower stage.

  As shown in FIG. 6, the TG 128 performs, for example, the second preliminary ejection pulse signal PR2, the first preliminary ejection pulse signal PR1, the ejection pulse signal R, and the readout pulse signal S in this order. Output. These four types of pulse signals are output during each scanning period and input to each shift register, and each shift register is input to each row at the logical product timing of the input pulse signal and a preset timing. A reset pulse RS and a selection pulse RW are output.

  In this embodiment, since a shift register is provided for each operation, operations having different timings for a plurality of rows can be performed in parallel during one scanning period.

  In FIG. 6, the second preliminary ejection pulse signal PR2, the first preliminary ejection pulse signal PR1, the ejection pulse signal R, and the readout pulse signal S are output from the TG 128 in this order. It is not necessarily limited to this order. FIG. 7 shows an example in which four types of pulse signals are output from the TG 128 in the other order. In FIG. 7, the TG 128 outputs the read pulse signal S, the discharge pulse signal R, the first preliminary discharge pulse signal PR1, and the second preliminary discharge pulse signal PR2. That is, FIG. 7 shows an example in which four types of pulse signals are output from the TG 128 in the reverse order to the example shown in FIG. Also in the example shown in FIG. 7, as described above, each shift register outputs the reset pulse RS and the selection pulse RW to each row at the logical product timing of the input pulse signal and a preset timing. Also in this case, the operation of each row is always performed in the order of the second preliminary discharge, the first preliminary discharge, the discharge, and the reading. Further, the first preliminary discharge of the (n + 1) th row is performed before the discharge of the nth row, and the second preliminary discharge of the (n + 1) th row is performed before the first preliminary discharge of the nth row. As described above, the timing is set in each shift register.

  Note that the output order of the four types of pulse signals output from the TG 128 is not limited to the order shown in FIGS. 6 and 7, but may be other orders. In the example shown in FIG. 6 and FIG. 7, the TG 128 outputs all four types of pulse signals at different timings. However, the present invention is not limited to this, and at least one of the four types of pulse signals is output. May be output at a timing different from the timing of other pulse signals. Thus, as described above, operations with different timings for a plurality of rows can be performed in parallel during one scanning period. However, also in this case, the operation of each row is performed in the order of the second preliminary discharge, the first preliminary discharge, the discharge, and the reading, and further, the first spare of the (n + 1) th row before the discharge of the nth row. The timing is set in each shift register so that the discharge is performed and the second preliminary discharge of the (n + 1) th row is performed before the first preliminary discharge of the nth row.

  In the solid-state imaging device 100 of the present embodiment, the readout circuit of each pixel unit 10 may be laid out in a pattern having periodicity in the pixel unit column direction.

  For example, when the readout circuit of the pixel unit 10 is laid out in a mirror image relationship, the readout circuit is laid out in a pattern of 2 row periods in the column direction, and the coupling capacitance between adjacent pixels is also 2 row periods.

  That is, as shown in the schematic diagram of FIG. 8, for example, the capacitive coupling between the pixel units 10 in the nth row (odd row) and the n + 1th row (even row) is relatively large, and the n + 1th row (even row). ) And the (n + 2) -th row (odd-numbered row) pixel portions 10 are relatively small in capacitive coupling. Further, the capacitive coupling between the pixel portions 10 of the (n + 2) th row (odd row) and the (n + 3) th row (even row) becomes relatively large.

  FIG. 9 shows the potential change of the FD when only discharging is performed as in the prior art without performing the preliminary discharging described above in such a configuration. The figure shows the time variation of the drive and FD potential when imaging is performed under conditions where uniform light is incident on all pixels. A solid line in FIG. 9 indicates an ideal potential change when there is no capacitive coupling, and a dotted line indicates an actual potential change. According to the magnitude of the capacitive coupling shown in FIG. 8, as shown in FIG. 9, the influence of the discharge of the (n + 1) th row on the potential of the FD of the pixel portion 10 of the nth row and the discharge of the (n + 3) th row are the discharges of the (n + 2) th row. Although the influence on the potential of the FD of the pixel unit 10 is large, the influence of the discharge of the (n + 2) th row on the potential of the FD of the pixel unit 10 of the (n + 1) th row is small. As a result, the even-numbered lines n + 1 and n + 3 can obtain an output almost equal to the case without capacitive coupling, while the odd-numbered lines n and n + 2 have no capacitive coupling. The output will be very different. That is, even when uniform light is incident on the pixel units 10 from the nth row to the n + 3th row, the magnitudes of the charge signals read out by the odd-numbered pixel units 10 and the even-numbered pixel units 10 are different. The horizontal stripes appear every other line on the read image.

  On the other hand, if the first and second preliminary discharges are performed at the timing described in the solid-state imaging device of the above embodiment, the influence of the capacitive coupling described above can be suppressed. Occurrence can be prevented.

  Further, the readout circuit of the pixel unit 10 is not limited to the 2-row cycle, and may be laid out in a pattern of, for example, a 3-row cycle or a 4-row cycle. In short, as long as the capacitive coupling formed between adjacent pixels in the column direction is a pattern that periodically changes in the column direction, it may be laid out in any periodic structure. The effect of the present invention becomes remarkable.

  In the solid-state imaging device 100 of the above embodiment, the reset transistor 13, the output transistor 12, and the selection transistor 14 are configured by n-channel MOS transistors, and holes are collected by the pixel electrode 104. Not limited to this, the reset transistor 13, the output transistor 12, and the selection transistor 14 are configured by p-channel MOS transistors, the electrons are collected by the pixel electrode 104, and a charge signal corresponding to the amount of the electrons is supplied to the p-channel MOS transistor. Reading may be performed by the signal reading circuit 116 configured as described above.

  As described in the above embodiment, holes are collected by the pixel electrode 104 and read out by the signal readout circuit 116 constituted by an n-channel MOS transistor, or electrons are collected by the pixel electrode 104 as described above. When this is configured to be read by the signal readout circuit 116 configured by a p-channel MOS transistor, electrons are collected by the pixel electrode and read by a signal readout circuit configured by an n-channel MOS transistor. Compared to the case, the voltage amplitude of the FD is large. For this reason, since the potential change of the FD at the time of discharge when the first and second preliminary discharges are not performed is large, the influence of the capacitive coupling on the signal charge of the FD of the adjacent pixel is large. The effect of the second preliminary discharge can be obtained more remarkably.

  However, in such a configuration, the potential of the FD may increase too much and the circuit may be destroyed. Therefore, as shown in FIG. 10, a configuration in which the protection circuit 17 is provided in the FD may be used. Since the number of components of the readout circuit 116 increases, the coupling rate increases. However, according to the present embodiment, there is no problem because it is possible to suppress deterioration in image quality due to the coupling rate.

  In addition, the solid-state imaging device of the above-described embodiment can be used for various imaging devices. Examples of the imaging device include a digital camera, a digital video camera, an electronic endoscope, and a camera-equipped mobile phone.

DESCRIPTION OF SYMBOLS 10 Pixel part 11 Photoelectric conversion part 12 Output transistor 13 Reset transistor 14 Selection transistor 16 Feedback control circuit 16a Inversion amplifier 16b Voltage source 17 Protection circuit 100 Solid-state image sensor 104 Pixel electrode 107 Photoelectric conversion layer 108 Counter electrode 111 Color filter 121 Vertical driver 122 Control unit 124 Horizontal driver 128 Timing generator 130 Read shift register 131 Discharge shift register 132 First preliminary discharge shift register 133 Second preliminary discharge shift register

Claims (14)

A photoelectric conversion unit that generates a signal charge corresponding to the amount of incident light, a storage unit that stores the signal charge generated in the photoelectric conversion unit, and an output that outputs a voltage corresponding to the signal charge stored in the storage unit A plurality of pixel units that are electrically connected to the photoelectric conversion unit, the power storage unit, and an input node of the output circuit,
Discharging the signal charges accumulated in the accumulating unit, and performing the charge accumulating / reading operation for sequentially reading out the signal charges accumulated in the accumulating unit when the charge accumulating period has elapsed after the ejection,
Before each discharge in each row, at least twice a preliminary discharge, which is a preliminary charge discharge from the power storage unit,
In addition, before the discharge of the nth (n is a natural number) row, the first preliminary discharge of the (n + 1) th row is performed, and the first reserve of the nth row performed immediately before the discharge of the nth row A solid-state imaging device characterized in that the second preliminary discharge in the (n + 1) th row is performed before discharge.   The solid-state imaging device according to claim 1, wherein a feedback control circuit that performs feedback control so that the power storage unit has a reference potential is provided for each column of the pixel units.   3. The solid state according to claim 2, wherein the feedback control circuit performs the feedback control at the time of the discharge, reading of the signal charge, the first preliminary discharge, and the second preliminary discharge. Image sensor.   At least one operation of the discharge, reading of the signal charge, the first preliminary discharge, and the second preliminary discharge is different from the operation other than the at least one operation within a scanning period of one row. The solid-state imaging device according to any one of claims 1 to 3, wherein the solid-state imaging device is performed at different timing in a row. A timing generator for outputting a pulse signal for controlling the timing of the discharge, reading of the signal charge, the first preliminary discharge and the second preliminary discharge;
The timing generator uses different timings for the pulse signal for controlling the timing of the at least one operation and the pulse signal for controlling the timing of the operation other than the at least one operation within a scanning period of one row. The solid-state imaging device according to claim 4, wherein the solid-state imaging device outputs the signal.   6. A shift register for controlling the timing of the discharge, reading of the signal charge, the first preliminary discharge and the second preliminary discharge is provided for each operation. The solid-state image sensor of Claim 1.   7. The solid-state imaging device according to claim 1, wherein a time of the first preliminary discharge or the second preliminary discharge is shorter than the time of the discharge. The pixel unit includes a first electrode partitioned in pixel units and a second electrode provided to face the pixel electrode with the photoelectric conversion unit interposed therebetween,
The solid-state imaging device according to claim 1, wherein the second electrode is a common electrode for all the pixel portions.   The solid-state imaging device according to claim 1, wherein the photoelectric conversion unit includes an organic photoelectric conversion film.   The solid-state imaging device according to claim 9, wherein the organic photoelectric conversion film is common to all the pixel portions.   The solid-state imaging device according to claim 1, wherein a signal charge from the photoelectric conversion unit is a hole.   The solid-state imaging device according to claim 1, wherein the signal charge from the photoelectric conversion unit is an electron.   The solid-state imaging device according to claim 1, wherein a protection circuit is provided in the power storage unit.   An imaging apparatus comprising the solid-state imaging device according to claim 1.

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