JP2017011514A - Solid-state image pickup device and driving method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device, having a focus detection function, and driving method therefor, capable of suppressing degradation in a signal level resulting from an arrangement place in a pixel region of a pixel for AF.SOLUTION: In a pixel region in which a plurality of photoelectric conversion components are provided, the photoelectric conversion components which are among the plurality of photoelectric conversion components include: a pixel region into which a part of light subjected to pupil division is launched and in which other light subjected to pupil division is launched into other photoelectric conversion components of the plurality of photoelectric conversion components; a signal read-out component which amplifies a signal read out from the photoelectric conversion component with a predetermined amplification factor and outputs the signal. The predetermined amplification factor is changed according to a place in which the photoelectric conversion components are positioned in the pixel region.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a solid-state imaging device having a focus detection function and a driving method thereof.

  Patent Document 1 includes an imaging pixel for acquiring an image forming signal and an AF pixel for acquiring an autofocus (AF) signal, and includes an image signal and an AF signal. A solid-state imaging device that can be acquired simultaneously is disclosed.

  Further, in Patent Document 2, each pixel has two photoelectric conversion units, and a pair of output signals from these two photoelectric conversion units are used as AF signals, and output signals from these two photoelectric conversion units are used. There is disclosed a solid-state imaging device that is used as an image signal by adding.

JP 2000-156823 A JP 2014-222863 A

  However, in the solid-state imaging devices described in Patent Document 1 and Patent Document 2, when the AF pixel is arranged at a location separated from the center of the pixel area, one of the two AF pixels that are paired is used for AF. The output signal level from the pixel may decrease. As a result, the detection accuracy of the phase difference signal is lowered, and the AF accuracy may be deteriorated.

  An object of the present invention is to provide a solid-state imaging device and a driving method thereof that can suppress a decrease in signal level caused by an arrangement location of AF pixels in a pixel region.

  According to an aspect of the present invention, a pixel region in which a plurality of photoelectric conversion units are provided, and a part of the pupil-divided light is incident on a part of the plurality of photoelectric conversion units. The other photoelectric conversion units of the plurality of photoelectric conversion units amplify the pixel area where other light divided by the pupil enters and the signals read from the photoelectric conversion units with a predetermined amplification factor and output There is provided a solid-state imaging device, wherein the predetermined amplification factor is changed according to a location where the photoelectric conversion unit is located in the pixel region.

  According to another aspect of the present invention, a first photoelectric conversion element that detects light in a first pupil region, and a signal charge that is generated by the first photoelectric conversion element are transferred to the first photoelectric conversion element. A first pixel having a floating diffusion portion and a focus detection pixel that is paired with the first pixel and detects light in a second pupil region different from the first pupil region. 2 photoelectric conversion elements and a second pixel having a second floating diffusion portion to which signal charges generated in the first photoelectric conversion element are transferred, and the first floating diffusion portion A solid-state imaging device is provided in which a capacitance value and a capacitance value of the second floating diffusion portion are different.

  According to still another aspect of the present invention, a pixel region in which a plurality of photoelectric conversion units are provided, and a part of the photoelectric conversion units of the plurality of photoelectric conversion units has a pupil-divided one. A solid-state imaging device having a pixel region in which light of a portion is incident and other light that is divided into pupils is incident on another photoelectric conversion portion of the plurality of photoelectric conversion portions, from the photoelectric conversion portion There is provided a method for driving a solid-state imaging device, wherein the read signal is amplified by changing an amplification factor according to a location where the photoelectric conversion unit is located in the pixel region.

  According to the present invention, it is possible to suppress a decrease in signal level due to the arrangement location of the AF pixels in the pixel region and improve AF accuracy.

1 is a circuit diagram illustrating a schematic configuration of a solid-state imaging device according to a first embodiment of the present invention. 1 is a circuit diagram illustrating a pixel configuration of a solid-state imaging device according to a first embodiment of the present invention. 2A and 2B are a plan view and a cross-sectional view illustrating a structure of an AF pixel of the solid-state imaging device according to the first embodiment of the present invention. It is a graph which shows the example of the output signal from the pixel for AF. It is a circuit diagram which shows schematic structure of the solid-state imaging device by 2nd Embodiment of this invention. It is a circuit diagram which shows schematic structure of the solid-state imaging device by 3rd Embodiment of this invention. It is a circuit diagram which shows schematic structure of the solid-state imaging device by 4th Embodiment of this invention. It is a circuit diagram which shows schematic structure of the solid-state imaging device by 5th Embodiment of this invention. It is a figure explaining operation | movement of the solid-state imaging device by 5th Embodiment of this invention. It is a circuit diagram which shows schematic structure of the solid-state imaging device by 6th Embodiment of this invention. It is sectional drawing which shows the structure of the pixel of the solid-state imaging device by 6th Embodiment of this invention. It is a block diagram which shows the structure of the imaging system by 7th Embodiment of this invention.

  Hereinafter, a solid-state imaging device, a driving method thereof, and an imaging system according to preferred embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
A solid-state imaging device and a driving method thereof according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram illustrating a schematic configuration of the solid-state imaging device according to the present embodiment. FIG. 2 is a circuit diagram illustrating a pixel configuration of the solid-state imaging device according to the present embodiment. FIG. 3 is a plan view and a cross-sectional view showing the structure of the AF pixel of the solid-state imaging device according to the present embodiment. FIG. 4 is a graph showing an output signal from the AF pixel.

  First, the structure of the solid-state imaging device 100 according to the present embodiment will be described with reference to FIGS. 1 to 3.

  As shown in FIG. 1, the solid-state imaging device 100 according to the present embodiment includes a pixel region 10, a vertical scanning circuit 20, a column readout circuit 30, a horizontal transfer circuit 50, and a horizontal scanning circuit 70. . In this specification, the signal processing circuit unit including the column readout circuit 30 and the horizontal transfer circuit 50 may be referred to as a signal readout unit.

  The pixel region 10 is provided with a plurality of pixels P arranged in a matrix over a plurality of rows and columns. FIG. 1 shows a pixel region 10 in which pixels P are arranged in a matrix of 3 columns × 6 rows for the sake of simplification, but the number of rows and columns constituting the pixel region 10 is as follows. It is not particularly limited. Further, in FIG. 1, for convenience of explanation, a column number is x and a row number is y, and each pixel is given a Pxy symbol. For example, the pixel P located in the first column and the fourth row is denoted as P14, and the pixel P located in the third column and the fifth row is denoted as P35.

  As shown in FIG. 2, each pixel P includes a photoelectric conversion element 12, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. The photoelectric conversion element 12 is, for example, a photodiode. The anode of the photoelectric conversion element 12 is connected to the ground voltage line, and the cathode of the photoelectric conversion element 12 is connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. A connection node between the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 forms a floating diffusion section (hereinafter referred to as “FD section”). In the figure, the parasitic capacitance of the FD portion is expressed as a floating diffusion capacitance 14. Note that the capacitance value of the floating diffusion capacitor 14 is the sum of the junction capacitance of the diffusion layer constituting the drain of the transfer transistor M1 and the source of the reset transistor M2 and the gate capacitance of the amplification transistor M3. The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to the power supply voltage line. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4.

  Each column of the pixel region 10 is provided with a vertical output line 16 extending in the column direction. The vertical output lines 16 are connected to the sources of the selection transistors M4 of the pixels Pxy arranged in the column direction, respectively, and form a common signal line for these pixels Pxy. A current source 18 and a column readout circuit 30 are connected to the vertical output line 16. An example of the current source 18 is the transistor M5 shown in FIG.

  In each row of the pixel region 10, a control signal line 22 extending in the row direction is arranged. Each control signal line 22 forms a common signal line for the pixels Pxy arranged in the row direction. The control signal line 22 is connected to the vertical scanning circuit 20. Each control signal line 22 includes a transfer gate signal line, a reset signal line, and a row selection signal line (all not shown). The transfer gate signal line is for outputting the transfer gate signal PTX from the vertical scanning circuit 20 to the pixel P, and is connected to the gate of the transfer transistor M1 of the corresponding pixel P. The reset signal line is for outputting a reset signal PRES from the vertical scanning circuit 20 to the pixel P, and is connected to the gate of the reset transistor M2 of the corresponding pixel P. The row selection signal line is for outputting a row selection signal PSEL from the vertical scanning circuit 20 to the pixel P, and is connected to the gate of the selection transistor M4 of the corresponding pixel P.

  As shown in FIG. 1, the column readout circuit 30 has an input capacitor 32, a feedback capacitor 34, a differential amplifier circuit 36, transistors M6, M7, M8, a storage capacitor 38, 40 is included. The non-inverting input terminal of the differential amplifier circuit 36 is connected to the vertical output line 16 via the input capacitor 32. A feedback capacitor 34 is connected between the non-inverting input terminal and the output terminal of the differential amplifier circuit 36. A voltage Vref is applied to the inverting input terminal of the differential amplifier circuit 36. As a result, a column amplifier including the differential amplifier circuit 36, the input capacitor 32, and the feedback capacitor 34 is configured. The output terminal of the differential amplifier circuit 36 is connected to the holding capacitor 38 via the transistors M6 and M7 and to the holding capacitor 40 via the transistors M6 and M8, respectively. The holding capacitors 38 and 40 are for temporarily holding signals read from the pixels P. The transistors M6, M7, and M8 are controlled by control signals input from the terminals 131, 132, and 133 to the control node, respectively.

  The horizontal transfer circuit 50 includes a differential amplifier circuit 52, horizontal output lines 54 and 56, holding capacitors 58 and 60, and transistors M9, M10, M11, and M12. The transistors M9 and M10 are provided corresponding to each column of the pixel region 10, respectively. A connection node between the transistor M7 and the storage capacitor 38 in each column of the column readout circuit 30 is connected to the horizontal output line 54 via the transistor M9. A connection node between the transistor M8 and the storage capacitor 40 in each column of the column readout circuit 30 is connected to the horizontal output line 56 via the transistor M10. A holding capacitor 58 is connected to the horizontal output line 54. A holding capacitor 60 is connected to the horizontal output line 56. One of the horizontal output lines 54 and 56 is connected to the non-inverting input terminal of the differential amplifier circuit 52, and the other is connected to the inverting input terminal of the differential amplifier circuit 52. A reset voltage Vres can be applied to the horizontal output lines 54 and 56 through the transistors M11 and M12. A horizontal scanning circuit 70 is connected to the control nodes of the transistors M9 and M10 in each column. The transistors M11 and M12 are controlled by a control signal input from the terminal 134 to the control node.

  Here, in the solid-state imaging device 100 according to the present embodiment, at least a part of the pixels Pxy constituting the pixel region 10 is configured by pixels (AF pixels) for acquiring a focus detection signal (AF signal). ing. There are various modes of arrangement of AF pixels. Here, pupil division is performed in the vertical direction, and signals in one pupil region are detected by pixels in the fifth row (pixels P15, P25, and P35). It is assumed that the signal of the other pupil region is detected by the pixels in the sixth row (pixels P16, P26, P36). In the following description, the AF pixel arranged in the fifth row is referred to as “S1 pixel”, and the AF pixel arranged in the sixth row is referred to as “S2 pixel”.

  The S1 pixel and the S2 pixel have a structure shown in FIG. 3, for example. An interlayer insulating film 112 and a microlens 114 are disposed on a semiconductor substrate 110 provided with a photodiode as the photoelectric conversion element 12. In the interlayer insulating film 112, a light shielding film 116 including an opening 118 provided in the S1 pixel portion and an opening 120 provided in the S2 pixel portion is provided. Note that an imaging pixel portion (not shown) other than the S1 pixel and the S2 pixel is provided with one opening portion (not shown) including a region corresponding to the opening portions 118 and 120. The openings 118 and 120 are arranged at positions symmetrical with respect to the center of the opening in the imaging pixel. That is, the opening 118 is disposed below the center of the S1 pixel unit, and the opening 120 is disposed above the center of the S2 pixel unit. As a result, one of the images formed on the pixel P by the light beams from the two pupil positions that are symmetrical about the optical axis can be detected by the S1 pixel, and the other can be detected by the S2 pixel.

  In this specification, the vertical direction corresponds to the vertical direction of the captured image in one example, and is the column direction in terms of the pixel arrangement of the pixel region 10. Further, the left and right directions correspond to the horizontal direction of the photographed image in one example, and are the row direction in relation to the pixel arrangement of the pixel region 10.

  In the solid-state imaging device 100 according to the present embodiment, the floating diffusion capacitance 14 of the S1 pixel and the floating diffusion capacitance 14 of the S2 pixel are different in at least a part of the paired S1 pixel and S2 pixel. In other words, in at least a part of the paired S1 pixel and S2 pixel, the floating diffusion capacitor 14 in the pixel in which the opening of the light shielding film 116 is located closer to the center of the pixel region 10 than the center of the pixel. The capacitance value is smaller than the other capacitance value. In the above example in which the S1 pixel shown in FIG. 3 is arranged in the fifth column and the S2 pixel shown in FIG. 3 is arranged in the sixth column, the floating diffusion capacitance 14 of the FD portion in the S2 pixel is the FD in the S1 pixel. It is smaller than the floating diffusion capacitance 14 of the part.

  Next, the driving method of the solid-state imaging device according to the present embodiment will be described with reference to FIGS.

  First, the high-level transfer gate signal PTX and the reset signal PRES are output from the vertical scanning circuit 20 to the pixel Pxy via the control signal line 22, and the transfer transistor M1 and the reset transistor M2 are turned on. As a result, the power supply voltage is applied to the photoelectric conversion element 12 via the transfer transistor M1 and the reset transistor M2, and the potential of the photoelectric conversion element 12 is reset. After performing the reset operation of the photoelectric conversion element 12, the transfer gate signal PTX and the reset signal PRES are set to low level, and the photoelectric conversion element 12 is disconnected from the power supply voltage. As a result, the photoelectric conversion element 12 starts a signal charge accumulation operation corresponding to the amount of incident light.

  After a predetermined accumulation period, a high level reset signal PRES is output from the vertical scanning circuit 20 to the pixel Pxy via the control signal line 22 to turn on the reset transistor M2. As a result, the power supply voltage is applied to the FD portion via the reset transistor M2, and the potential of the FD portion, that is, the floating diffusion capacitor 14 is reset. After performing the reset operation of the FD unit, the reset signal PRES is set to a low level to disconnect the FD unit from the power supply voltage. Thereby, the reset operation of the FD unit is completed.

  Next, a high level selection signal PSEL is output from the vertical scanning circuit 20 via the control signal 22, and the selection transistor M4 is turned on. The amplification transistor M3 is in a state where a bias current is supplied from the current source 18 (transistor M5) via the selection transistor M4, and forms a source follower circuit. As a result, a signal (reset signal) corresponding to the reset voltage of the FD unit is output to the vertical output line 16 via the selection transistor M4.

  The reset signal output to the vertical output line 16 is input to the column readout circuit 30 and is amplified by the differential amplifier circuit 36 with a gain (amplification factor) corresponding to the capacitance ratio between the input capacitor 32 and the feedback capacitor 34. Are held in the holding capacitor 38 via the transistors M6 and M7.

  Next, a high-level transfer gate signal PTX is output from the vertical scanning circuit 20 via the control signal 22, and the transfer transistor M1 is turned on. As a result, the signal charge generated and accumulated in the photoelectric conversion element 12 is transferred to the FD portion via the transfer transistor M1. As a result, the FD portion becomes a voltage obtained by superimposing the voltage corresponding to the amount of the signal charge transferred to the FD portion and the floating diffusion capacitance 14 on the reset voltage. As a result, a signal (photoelectric conversion signal) corresponding to the amount of signal charge transferred to the FD unit is output to the vertical output line 16 via the selection transistor M4.

  The photoelectric conversion signal output to the vertical output line 16 is input to the column readout circuit 30, amplified by the differential amplifier circuit 36 with a gain corresponding to the capacitance ratio of the input capacitor 32 and the feedback capacitor 34, and then the transistor M6. , M8 and held in the holding capacitor 40.

  The above operation is performed simultaneously in each column for each row, and for example, reset signals and photoelectric conversion signals from the pixels P11, P21, and P31 are held in the corresponding holding capacitors 38 and 40, respectively.

  Next, after driving the transistors M11 and M12 and resetting the potentials of the horizontal output lines 54 and 56, the horizontal scanning circuit 70 sequentially outputs a high-level control signal for each column and is held in the holding capacitors 38 and 40. Are sequentially read out to the horizontal output lines 54 and 56. As a result, a differential signal between the photoelectric conversion signal and the reset signal is output from the output terminal of the differential amplifier circuit 52 to the output terminal 135. Reading of the reset signal and the photoelectric conversion signal to the horizontal output lines 54 and 56 is performed by sequentially outputting a control signal for controlling the transistors M9 and M10 from the horizontal scanning circuit 70 for each column. By performing the difference calculation between the electric conversion signal and the reset signal by the differential amplifier circuit 52, it is possible to cancel a noise signal caused by characteristic variations such as a threshold voltage of the amplification transistor M3 in the pixel portion, and an S / N ratio. A high output signal can be obtained.

  The series of readout operations are sequentially performed for each row of the pixel region 10 to acquire an image signal and an AF signal.

  The above readout operation is the same for the S1 pixel and S2 pixel which are AF pixels. However, depending on the arrangement location of the S1 pixel and the S2 pixel, an output signal having a sufficient level may not be obtained from one of the S1 pixel and the S2 pixel.

  FIG. 4A is a graph showing output signal levels from these pixels when a pair of S1 pixels and S2 pixels are arranged at the center of the pixel region 10. As shown in the figure, when the S1 pixel and the S2 pixel are arranged in the central portion of the pixel region 10, the S1 signal from the S1 pixel and the S2 signal from the S2 pixel are substantially the same level, which is lower than the floor noise level b. Is big enough. Therefore, the phase difference signal a1 can be accurately detected from the peak signal position of the S1 signal and the peak position of the S2 signal.

  However, as the S1 and S2 pixels are arranged closer to the upper or lower portion of the pixel region 10, the light vignetting by the light shielding film 116 increases, and the difference between the output level of the S1 signal and the output level of the S2 signal increases. That is, as the shift of the incident angle of the light incident on the pixel P with respect to the normal direction increases, the output signal level of the S1 pixel disposed above the central portion of the pixel region 10 decreases, and the central portion The output signal level increases as the S1 pixel is arranged on the lower side. On the contrary, the output signal level is higher for the S2 pixel arranged above the central part of the pixel region 10, and the output signal level is smaller for the S2 pixel arranged below the central part.

  Therefore, as in the solid-state imaging device according to the present embodiment, for example, when the S1 pixel and the S2 pixel are arranged in the fifth and sixth rows below the pixel region 10, the S1 signal and the S2 signal For example, as shown in FIG. That is, the output level of the S1 signal is higher than that in FIG. 4A, and the output level of the S2 signal is lower than that in FIG. 4A. When the output level of the S2 signal decreases to near the floor noise level b, the error in detecting the peak position of the S2 signal increases, the detection accuracy of the phase difference signal a2 decreases, and consequently the AF accuracy increases. It will get worse.

  Therefore, in the solid-state imaging device 100 according to the present embodiment, the capacitance value of the floating diffusion capacitor 14 in the FD portion of the S2 pixel in the portion (hereinafter also referred to as the peripheral portion) separated from the central portion of the pixel region 10 is set in the S1 pixel. It is smaller than the capacitance value of the floating diffusion capacitor 14 in the FD portion. As described above, the voltage of the FD unit is obtained by superimposing the voltage obtained by converting the signal charge transferred from the photoelectric conversion unit 12 according to the capacitance value of the floating diffusion capacitor 14 on the reset voltage. That is, as the floating diffusion capacitance 14 is smaller, the change in the voltage of the FD portion accompanying the change in the signal charge, and thus the output level of the photoelectric conversion signal increases.

  Therefore, by making the capacitance value of the floating diffusion capacitor 14 of the FD portion in the S2 pixel smaller than the capacitance value of the floating diffusion capacitor 14 of the FD portion in the S1 pixel, the output gain from the S2 pixel is set to the output gain from the S1 pixel. Can be larger. Thereby, as shown in FIG. 4C, for example, the output level of the S2 signal can be made sufficiently higher than the floor noise level b to improve the SN ratio, and the detection accuracy of the phase difference signal a3 is improved. be able to.

  The capacitance value of the floating diffusion capacitor 14 of the S2 pixel is desirably determined as appropriate so that the output level of the S2 signal is sufficiently higher than the floor noise level b. Since it is sufficient that the S1 signal and the S2 signal can accurately detect the peak signal positions of these signals, the peak heights of these signals are not necessarily the same.

  In the case where a plurality of S2 pixels are provided between the central portion and the lower portion of the pixel region 10, only at least S2 pixels in which the output level reduction affects the detection accuracy of the phase difference signal among the plurality of S2 pixels What is necessary is just to make the capacity | capacitance 14 small. Alternatively, the floating diffusion capacitance 14 may be changed continuously or stepwise so that the floating diffusion capacitance 14 becomes smaller in the S2 pixel lower than the S2 pixel in the center of the pixel region 10.

  In addition, although the case where the S1 pixel and the S2 pixel shown in FIG. 3 are arranged below the central portion of the pixel region 10 has been described as an example here, the S1 pixel and the S2 pixel are disposed below the central portion of the pixel region 10. When arranged on the upper side, the relationship between the S1 pixel and the S2 pixel is reversed. That is, in this case, the capacitance value of the floating diffusion capacitor 14 of the S1 pixel is made smaller than the capacitance value of the floating diffusion capacitor 14 of the S2 pixel.

  Further, when pupil division is performed in the horizontal direction, similarly, one of the S1 pixel and the S2 pixel on the right side of the pixel region 10 is reduced in size, and the S1 pixel and the S1 pixel on the left side of the pixel region 10 are reduced. What is necessary is just to make the other floating diffusion capacitance 14 of S2 pixels small.

  As described above, the floating diffusion capacitance 14 is the sum of the junction capacitance of the diffusion layer constituting the drain of the transfer transistor M1 and the source of the reset transistor M2 and the gate capacitance of the amplification transistor M3. Therefore, in order to reduce the floating diffusion capacitance 14, the size of some or all of these transistors may be reduced.

  As described above, according to the present embodiment, it is possible to suppress a decrease in signal level due to the arrangement location of the AF pixels in the pixel region and improve AF accuracy.

[Second Embodiment]
A solid-state imaging device and a driving method thereof according to the second embodiment of the present invention will be described with reference to FIG. Components similar to those of the solid-state imaging device according to the first embodiment shown in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof is omitted or simplified. FIG. 5 is a circuit diagram illustrating a schematic configuration of the solid-state imaging device according to the present embodiment.

  As shown in FIG. 5, the solid-state imaging device 100 according to the present embodiment is the same as the solid-state imaging device 100 according to the first embodiment shown in FIG. 1 except that the configuration of the column readout circuit 30 is different. That is, the column readout circuit 30 of the solid-state imaging device 100 according to the present embodiment further includes an input capacitor 42 configured to be connected in parallel to the input capacitor 32. The column amplification unit includes a differential amplification circuit 36, input capacitors 32 and 42, a feedback capacitor 34, and a transistor M13. By switching the conduction state of the transistor M13 connected in series to the input capacitor 42, the input capacitor 42 can be connected in parallel to the input capacitor 32, or the input capacitor 42 can be disconnected from the input capacitor 32. The transistor M13 is controlled by a control signal input from the terminal 136 to the control node.

  In the solid-state imaging device 100 according to the first embodiment, the gain of the column amplification unit is defined by the capacitance ratio between the capacitance C1 of the input capacitance 32 and the capacitance C3 of the feedback capacitance 34, that is, C1 / C3. On the other hand, in the solid-state imaging device 100 according to the present embodiment, the gain of the column amplification unit can be switched depending on the conduction state of the transistor M13. That is, when the transistor M13 is in the off state, the gain of the differential amplifier circuit 36 is C1 / C3. On the other hand, when the transistor M13 is in the ON state, the gain of the differential amplifier circuit 36 is the capacitance ratio between the combined capacitance of the capacitance C1 of the input capacitance 32 and the capacitance C2 of the input capacitance 42 and the capacitance C3 of the feedback capacitance 34, (C1 + C2) / C3. In this sense, the transistor M13 is a control unit that controls the amplification factor of the column amplification unit. For example, when C1 = C2 = C3, the gain of the differential amplifier circuit 36 is 1 when the transistor M13 is turned off, and the gain of the differential amplifier circuit 36 is 2 when the transistor M13 is turned on. .

  Therefore, the output level of the S2 signal can be increased by setting the transistor M13 to the off state when reading the signal from the S1 pixel and setting the transistor M13 to the on state when reading the signal from the S2 pixel. it can. As a result, for example, as shown in FIG. 4C, the S2 signal output level can be made sufficiently higher than the floor noise level b to improve the SN ratio, and the detection accuracy of the phase difference signal a3 can be improved. can do.

  In the solid-state imaging device 100 according to the present embodiment, the floating diffusion capacitance 14 of the S2 pixel does not necessarily need to be smaller than the floating diffusion capacitance 14 of the S1 pixel. The floating diffusion capacitance 14 of the S2 pixel may be the same as the floating diffusion capacitance 14 of the S1 pixel, or may be smaller than the floating diffusion capacitance 14 of the S1 pixel. In the solid-state imaging device 100 according to the present embodiment, if the floating diffusion capacitance 14 of the S2 pixel is made smaller than the floating diffusion capacitance 14 of the S1 pixel, a synergistic effect can be obtained.

  As described above, according to the present embodiment, it is possible to suppress a decrease in signal level due to the arrangement location of the AF pixels in the pixel region and improve AF accuracy.

[Third Embodiment]
A solid-state imaging device according to a third embodiment of the present invention will be described with reference to FIG. The same components as those of the solid-state imaging device according to the first and second embodiments shown in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof is omitted or simplified. FIG. 6 is a circuit diagram illustrating a schematic configuration of the solid-state imaging device according to the present embodiment.

  As shown in FIG. 6, the solid-state imaging device 100 according to the present embodiment is the same as the solid-state imaging device 100 according to the first embodiment shown in FIG. 1 except that the configuration of the column readout circuit 30 is different. That is, the column readout circuit 30 of the solid-state imaging device 100 according to the present embodiment further includes the holding capacitors 44 and 46 and the transistors M14 and 15 in each column. The storage capacitor 44 is connected to the output terminal of the differential amplifier circuit 36 via the transistors M14 and M6. The holding capacitor 46 is connected to the output terminal of the differential amplifier circuit 36 through transistors M15 and M6. The transistors M14 and M15 are controlled simultaneously with the transistors M7 and M8 by a control signal input from the terminals 132 and 133 to the control node, respectively.

  The horizontal transfer circuit 50 of the solid-state imaging device 100 according to the present embodiment further includes transistors M16 and M17 and an AND circuit 62 in each column. A connection node between the transistor M14 and the storage capacitor 44 in each column of the column readout circuit 30 is connected to the horizontal output line 54 via the transistor M16. A connection node between the transistor M15 and the storage capacitor 46 in each column of the column readout circuit 30 is connected to the horizontal output line 56 via the transistor M17. The output terminal of the AND circuit 62 is connected to the control nodes of the transistors M16 and M17. A control signal from the horizontal scanning circuit 70 and a control signal from the terminal 141 are input to the AND circuit 62. Note that separate control signals are input from the terminals 141, 142, and 143 to the AND circuits 62 in each column.

  In the solid-state imaging device 100 according to the present embodiment, the reset signal output from the column readout circuit 30 is also held in the holding capacitor 44 via the transistors M6 and M14. The photoelectric conversion signal output from the column readout circuit 30 is also held in the holding capacitor 46 via the transistors M6 and M15.

  When the reset signal and photoelectric conversion signal are read out to the horizontal output lines 54 and 56, the control signal input from the terminal 141 to the AND circuit 62 is appropriately controlled, and the horizontal output from the holding capacitors 38, 40, 44, and 46 is performed. The gain for reading to the lines 54 and 56 is determined. The gain when reading signals from the holding capacitors 38, 40, 44, 46 to the horizontal output lines 54, 56 is determined by the capacity division ratio. Here, it is assumed that the storage capacitors 38 and 40 have a capacitance value C4, the storage capacitors 44 and 46 have a storage capacitance C5, and the storage capacitors 58 and 60 have a capacitance value C6.

  When reading the S1 signal, a high-level control signal is input from the horizontal scanning circuit 70 and a low-level control signal is input from the terminal 141. As a result, the transistors M9 and M10 are turned on, and the transistors M16 and M17 remain off. In other words, the capacitance value of the storage capacitor that holds the S1 signal viewed from the horizontal output lines 54 and 56 side is C4. Therefore, the read gain from the storage capacitor 38 to the horizontal output line 54 and the read gain from the storage capacitor 40 to the horizontal output line 56 are both C4 / (C4 + C6).

  On the other hand, when reading the S2 signal, a high level control signal is input from the horizontal scanning circuit 70 and a high level control signal is also input from the terminal 141. As a result, the transistors M9 and M10 are turned on, and the transistors M16 and M17 are also turned on. That is, the capacitance value of the storage capacitor that holds the S2 signal viewed from the horizontal output lines 54 and 56 side is C4 + C5. Therefore, the read gain from the holding capacitors 38 and 44 to the horizontal output line 54 and the read gain from the holding capacitors 40 and 46 to the horizontal output line 56 are both (C4 + C5) / (C4 + C5 + C6).

  In this sense, the transistors M16 and M17 and the AND circuit 62 are control units that control the amplification factor by changing the capacitance value of the storage capacitor when signals are read out to the horizontal output lines 54 and 56.

  For example, if C4 = C5 = C6, the read gain when reading the S1 signal is ½, while the read gain when reading the S2 signal is 2/3, and the read gain of the S2 signal is It can be made larger than the read gain of the S1 signal. As a result, for example, as shown in FIG. 4C, the S2 signal output level can be made sufficiently higher than the floor noise level b to improve the SN ratio, and the detection accuracy of the phase difference signal a3 can be improved. can do.

  When a signal is read out from the pixel P in the second column or the third column, the control signal is input to the terminal 142 or the terminal 143 instead of inputting the control signal to the terminal 141. The rest is the same as the read operation in the first column.

  In the solid-state imaging device 100 according to the present embodiment, the floating diffusion capacitance 14 of the S2 pixel does not necessarily need to be smaller than the floating diffusion capacitance 14 of the S1 pixel. The floating diffusion capacitance 14 of the S2 pixel may be the same as the floating diffusion capacitance 14 of the S1 pixel, or may be smaller than the floating diffusion capacitance 14 of the S1 pixel. In the solid-state imaging device 100 according to the present embodiment, if the floating diffusion capacitance 14 of the S2 pixel is made smaller than the floating diffusion capacitance 14 of the S1 pixel, a synergistic effect can be obtained.

  As described above, according to the present embodiment, it is possible to suppress a decrease in signal level due to the arrangement location of the AF pixels in the pixel region and improve AF accuracy.

[Fourth Embodiment]
A solid-state imaging device and a driving method thereof according to the fourth embodiment of the present invention will be described with reference to FIG. Constituent elements similar to those of the solid-state imaging device according to the first to third embodiments shown in FIGS. 1 to 6 are denoted by the same reference numerals, and description thereof is omitted or simplified. FIG. 7 is a circuit diagram illustrating a schematic configuration of the solid-state imaging device according to the present embodiment.

  The solid-state imaging device 100 according to the present embodiment further includes an output circuit 80 connected to the output terminal of the differential amplifier circuit 52. The output circuit 80 includes a differential amplifier circuit 88, input capacitors 82 and 84, a feedback capacitor 86, and a transistor M18. The output circuit 80 is an output amplifier that amplifies a signal output from the solid-state imaging device 100.

  The non-inverting input terminal of the differential amplifier circuit 88 is connected to the output terminal of the differential amplifier circuit 52 via the input capacitor 82. A feedback capacitor 86 is connected between the non-inverting input terminal and the output terminal of the differential amplifier circuit 88. The input capacitor 84 is configured to be connectable in parallel to the input capacitor 82. By switching the conduction state of the transistor M18 connected in series to the input capacitor 84, the input capacitor 84 can be connected to the input capacitor 82 in parallel, or the input capacitor 84 can be disconnected from the input capacitor 82. The transistor M18 is controlled by a control signal input from the terminal 137 to the control node.

  The gain of the differential amplifier circuit 88 is determined by the ratio between the input capacitance and the feedback capacitance. Here, it is assumed that the capacitance values of the input capacitor 82, the input capacitor 84, and the feedback capacitor 86 are C7, C8, and C9, respectively.

  When reading the S1 signal, the transistor M18 is turned off. Thereby, the gain of the differential amplifier circuit 88 becomes C7 / C9. On the other hand, when reading the S2 signal, the transistor M19 is turned on. As a result, the gain of the differential amplifier circuit 88 is (C7 + C8) / C9.

  In this sense, the transistor M19 is a control unit that controls the amplification factor of the signal output from the solid-state imaging device 100.

  For example, if C7 = C8 = C9, the gain when reading the S1 signal is 1, whereas the gain when reading the S2 signal is 2, and the gain when reading the S2 signal is read as the S1 signal. It can be larger than the gain at the time. As a result, for example, as shown in FIG. 4C, the S2 signal output level can be made sufficiently higher than the floor noise level b to improve the SN ratio, and the detection accuracy of the phase difference signal a3 can be improved. can do.

  In the solid-state imaging device 100 according to the present embodiment, the floating diffusion capacitance 14 of the S2 pixel does not necessarily need to be smaller than the floating diffusion capacitance 14 of the S1 pixel. The floating diffusion capacitance 14 of the S2 pixel may be the same as the floating diffusion capacitance 14 of the S1 pixel, or may be smaller than the floating diffusion capacitance 14 of the S1 pixel. In the solid-state imaging device 100 according to the present embodiment, if the floating diffusion capacitance 14 of the S2 pixel is made smaller than the floating diffusion capacitance 14 of the S1 pixel, a synergistic effect can be obtained.

  As described above, according to the present embodiment, it is possible to suppress a decrease in signal level due to the arrangement location of the AF pixels in the pixel region and improve AF accuracy.

[Fifth Embodiment]
A solid-state imaging device according to a fifth embodiment of the present invention will be described with reference to FIGS. Constituent elements similar to those of the solid-state imaging device according to the first to fourth embodiments shown in FIGS. 1 to 7 are denoted by the same reference numerals, and description thereof is omitted or simplified. FIG. 8 is a circuit diagram illustrating a schematic configuration of the solid-state imaging device according to the present embodiment. FIG. 9 is a diagram for explaining the operation of the solid-state imaging device according to the fifth embodiment of the present invention.

  In the first to fourth embodiments, the solid-state imaging device that outputs the sensor signal as an analog signal has been described as an example. However, the present invention can also be applied to a solid-state imaging device that incorporates an AD conversion unit in a chip and outputs a sensor signal as a digital signal. In this embodiment, an application example to a solid-state imaging device that outputs a sensor signal as a digital signal will be described.

  As shown in FIG. 8, the solid-state imaging device 100 according to the present embodiment includes a comparator 90, a column memory 92, and transistors M19 and M20 in each column of the column readout circuit 30. Further, a ramp signal generation circuit 94, a counter circuit 96, and a timing generator 98 are further provided. These elements constituting the column readout circuit 30 constitute an AD conversion unit.

  One input terminal of the comparator 90 is connected to the vertical output line 16. A column amplification unit similar to those in the first to fourth embodiments may be provided between the vertical output line 16 and the comparator 90. The other input terminal of the comparator 90 is connected to the ramp signal generation circuit 94 via the transistor M19 and via the transistor M20. The transistors M19 and M20 are controlled by control signals input from the terminals 138 and 139 to the control node, respectively.

  The output terminal of the comparator 90 is connected to the column memory 92. A counter circuit 96 is connected to the column memory 92. The column memory 92 is connected to the horizontal output line 54. The horizontal scanning circuit 70 is connected to the column memory 92. An output circuit 80 is connected to the horizontal output line 54. A timing generator 98 is connected to the vertical scanning circuit 20, the ramp signal generation circuit 94 and the counter circuit 96.

  The pixel signal output from the pixel P is input to one input terminal of the comparator 90 via the vertical output line 16. A ramp signal having a predetermined slope is input from the ramp signal generation circuit 94 to the other input terminal of the comparator 90. The ramp signal generation circuit 94 outputs two ramp signals 151 and 152 having different inclinations as shown in FIG. 9, for example. The ramp signal generation circuit 94 is designed such that the ramp signals 151 and 152 begin to fall in synchronization with the output of the clock pulse 156 from the timing generator 98 to the counter circuit 96. One of the ramp signals 151 and 152 output from the ramp signal generation circuit 94 is selected by the transistors M19 and M20 and input to the other input terminal of the comparator 90. The counter circuit 96 counts the clock pulses 156 input from the timing generator 98 and outputs the value to the column memory 92.

  The comparator 90 compares the signal level between the pixel signal 153 output from the pixel P and the ramp signals 151 and 152. The comparator 90 changes the signal level of the output signal when the magnitude relationship between the pixel signal 153 and the ramp signals 151 and 152 is switched. The column memory 92 that has detected the change in the output signal from the comparator 90 records the output values (count values 154 and 155) from the counter circuit 96 latched at this timing as digital codes. Thereafter, the horizontal scanning circuit 70 is operated, and the code recorded in the column memory 92 of each column is output from the output terminal 135 via the output circuit 80. Note that the processing in the output circuit 80 includes differential processing for subtracting the noise signal component from the photoelectric conversion signal component.

  In order to change the amplification factor of the output signal in the solid-state imaging device 100 that outputs the sensor signal as a digital signal, the slopes of the ramp signals 151 and 152 may be changed. The gentler the slope of the ramp signal, the larger the count value until the output signal of the comparator 90 is inverted, that is, the gain can be increased.

  Accordingly, the ramp signal used when reading the S1 signal is the ramp signal 151, and the ramp signal used when reading the S2 signal is the ramp signal 152, so that the gain when reading the S2 signal is read when the S1 signal is read. Can be larger than the gain. As a result, for example, as shown in FIG. 4C, the S2 signal output level can be made sufficiently higher than the floor noise level b to improve the SN ratio, and the detection accuracy of the phase difference signal a3 can be improved. can do.

  In the solid-state imaging device 100 according to the present embodiment, the capacitance value of the floating diffusion capacitor 14 in the FD portion in the S2 pixel does not necessarily need to be smaller than the capacitance value of the floating diffusion capacitor 14 in the FD portion in the S1 pixel. The floating diffusion capacitance 14 of the S2 pixel may be the same as the floating diffusion capacitance 14 of the S1 pixel, or may be smaller than the floating diffusion capacitance 14 of the S1 pixel.

  As described above, according to the present embodiment, it is possible to suppress a decrease in signal level due to the arrangement location of the AF pixels in the pixel region and improve AF accuracy.

[Sixth Embodiment]
A solid-state imaging device according to a sixth embodiment of the present invention will be described with reference to FIGS. 10 and 11. Constituent elements similar to those of the solid-state imaging device according to the first to fifth embodiments shown in FIGS. 1 to 9 are denoted by the same reference numerals, and description thereof is omitted or simplified. FIG. 10 is a circuit diagram illustrating a schematic configuration of the solid-state imaging device according to the present embodiment. FIG. 11 is a cross-sectional view illustrating the pixel structure of the solid-state imaging device according to the present embodiment.

  In the first embodiment, an example in which the pixel P having the circuit configuration illustrated in FIG. 2 is used and the S1 signal and the S2 signal are output from different pixels P (S1 pixel and S2 pixel) has been described. However, the pixel P is not necessarily configured by the pixel circuit illustrated in FIG. 2. For example, as illustrated in FIG. 10, each pixel P may have two subpixels. The pixel P having two subpixels can detect a pair of AF signals from these subpixels, and can also detect an image signal by adding the signals from the two subpixels.

  In FIG. 10, each pixel P has two photoelectric conversion elements Da and Db. The photoelectric conversion element Da is connected to the FD part via the transfer transistor Ma, and the photoelectric conversion element Db is connected to the FD part via the transfer transistor Mb. By arranging these photoelectric conversion elements Da and Db in different pupil regions, a signal output from the photoelectric conversion element Da and a signal output from the photoelectric conversion element Db can be used as a pair of AF signals. Moreover, the signal for an image can be acquired by adding the signal output from the photoelectric conversion element Da and the signal output from the photoelectric conversion element Db.

  FIG. 11 is a diagram schematically showing a cross-sectional structure of a pixel P having two photoelectric conversion elements Da and Db. The microlens array is arranged to be reduced with respect to the pixel array in consideration of the difference in the incident angle of light to each pixel P in the pixel region 10. For this reason, in the peripheral part of the pixel region 10, the microlens 114 is arranged so as to be shifted with respect to the two photoelectric conversion elements Da and Db constituting one pixel P. The example of FIG. 11 is a schematic diagram of the pixel P at the right end of the pixel region 10, and the microlens 114 is arranged to be shifted to the left with respect to the photoelectric conversion elements Da and Db.

  For this reason, in particular, in the pixel P in the peripheral portion of the pixel region 10, the amount of incident light on the photoelectric conversion element (photoelectric conversion element Da) disposed on the center side of the pixel region 10 is disposed outside the pixel region 10. It becomes smaller than the amount of light incident on the photoelectric conversion element (photoelectric conversion element Db). As a result, the relationship between the output level of the signal output from the photoelectric conversion element Db and the output level of the signal output from the photoelectric conversion element Da is the output level of the S1 signal and the output of the S2 signal described in the first embodiment. It becomes the same as the relationship with the level.

  Therefore, by making the output gain when reading the signal from the photoelectric conversion element Da larger than the output gain when reading the signal from the photoelectric conversion element Db by the same method as in the second to fifth embodiments, Detection accuracy can be improved. When acquiring the image signal from the photoelectric conversion elements Da and Db, the output gain when reading the signal from the photoelectric conversion element Da is the same as the output gain when reading the signal from the photoelectric conversion element Db. Good.

  In the circuit configuration shown in FIG. 10, a part of the in-pixel readout circuit (reset transistor M2, amplification transistor M3, and selection transistor M4) is shared by two adjacent pixels P in the same column. An in-pixel readout circuit may be provided for the pixel.

  As described above, according to the present embodiment, it is possible to suppress a decrease in signal level due to the arrangement location of the AF pixels in the pixel region and improve AF accuracy.

[Seventh Embodiment]
An imaging system according to a seventh embodiment of the present invention will be described with reference to FIG. The same components as those of the solid-state imaging device according to the first to sixth embodiments shown in FIGS. 1 to 11 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 12 is a block diagram illustrating a configuration of the imaging system according to the present embodiment.

  The solid-state imaging device described in the first to sixth embodiments can be applied to various imaging systems. Examples of the imaging system include a digital still camera, a digital camcorder, and a surveillance camera.

  An imaging system 200 illustrated in FIG. 12 includes a solid-state imaging device 100, a lens 202 that forms an optical image of a subject on the solid-state imaging device 100, a diaphragm 204 that changes the amount of light passing through the lens 202, and protection of the lens 202. A barrier 206 is provided. The lens 202 and the diaphragm 204 are optical systems that collect light on the solid-state imaging device 100. The solid-state imaging device 100 is the solid-state imaging device 100 described in the first to sixth embodiments.

  The imaging system 200 also includes an output signal processing unit 208 that processes an output signal output from the solid-state imaging device 100. The output signal processing unit 208 performs AD conversion that converts an analog signal output from the solid-state imaging device 100 into a digital signal. In addition, the output signal processing unit 208 performs an operation of outputting image data after performing various corrections and compressions as necessary.

  The imaging system 200 further includes a buffer memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. Further, the imaging system 200 includes a recording medium 214 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading to the recording medium 214. Have Note that the recording medium 214 may be built in the imaging system 200 or detachable.

  The imaging system 200 further includes an overall control / arithmetic unit 218 that controls various arithmetic operations and the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the solid-state imaging device 100 and the output signal processing unit 208. Here, the timing signal or the like may be input from the outside, and the imaging system 200 only needs to include at least the solid-state imaging device 100 and the output signal processing unit 208 that processes the output signal output from the solid-state imaging device 100. .

  The solid-state imaging device 100 outputs a focus detection signal and an imaging signal based on a signal output from the focus detection pixel to the output signal processing unit 208. The output signal processing unit 208 uses the focus detection signal to detect whether or not it is in focus. The output signal processing unit 208 generates an image using the imaging signal. When the output signal processing unit 208 detects that it is not in focus, the overall control / calculation unit 218 drives the optical system in the direction of focusing. The output signal processing unit 208 again detects whether or not it is in focus again using the focus detection signal output from the solid-state imaging device 100. Thereafter, the solid-state imaging device 100, the output signal processing unit 208, and the overall control / calculation unit 218 repeat this operation until focusing is achieved.

  By applying the solid-state imaging device 100 according to the first to sixth embodiments, the detection accuracy of the focus detection signal obtained from the AF pixel can be improved. As a result, an imaging system capable of improving AF accuracy and acquiring a higher quality image can be realized.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications can be made.

  For example, in the above-described embodiment, the configuration in which the amplification factor is changed in each unit of the solid-state imaging device 100 has been described. However, the amplification factor set in each unit is not limited to two types but may be three or more types.

  In addition, the configurations described in the first to sixth embodiments have the same effect independently of each other, and a synergistic effect can be obtained by arbitrarily combining the configurations of two or more of these embodiments. It is also possible to obtain One solid-state imaging device may have a plurality of means for changing the amplification factor, and these may be used properly according to the location of the AF pixel.

  In the above-described embodiment, the solid-state imaging device including the pixel that acquires the image signal and the pixel that acquires the AF signal has been described. However, the pixel need not necessarily include the pixel that acquires the image signal. That is, the photoelectric conversion device used only for the purpose of acquiring the AF signal may be used.

  The output of the focus detection pixel shown in the above embodiment is not limited to focus detection, and may be used for measurement such as distance measurement and motion detection.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

DESCRIPTION OF SYMBOLS 10 ... Pixel region 20 ... Vertical scanning circuit 30 ... Column readout circuit 50 ... Horizontal transfer circuit 70 ... Horizontal scanning circuit 32, 42 ... Input capacity 34 ... Feedback capacity 36, 52 ... Differential amplification circuit 90 ... Comparator 92 ... Column memory 94: Ramp signal generation circuit 96 ... Counter circuit 98 ... Timing generator

Claims (10)

A pixel region in which a plurality of photoelectric conversion units are provided, and a part of the photoelectric conversion units of the plurality of photoelectric conversion units receives a part of pupil-divided light, and the plurality of photoelectric conversion units A pixel region where other light divided into pupils enters the other photoelectric conversion unit, and
A signal reading unit that amplifies the signal read from the photoelectric conversion unit at a predetermined amplification rate and outputs the amplified signal;
The solid-state imaging device, wherein the predetermined amplification factor is changed according to a location where the photoelectric conversion unit is located in the pixel region. The plurality of photoelectric conversion units are arranged in a portion separated from a central portion of the pixel region, and a pair of first and second photoelectric conversion units capable of detecting a pupil-divided signal, and the pixels A pair of third photoelectric conversion units and a fourth photoelectric conversion unit, which are arranged in the central part of the region and can detect a pupil-divided signal;
The signal read from the first photoelectric conversion unit and the signal read from the second photoelectric conversion unit are amplified with different amplification factors, and the signal read from the third photoelectric conversion unit is The solid-state imaging device according to claim 1, wherein the predetermined amplification factor is set so as to amplify the signal read from the fourth photoelectric conversion unit with the same amplification factor. The plurality of photoelectric conversion units are arranged over a plurality of rows,
The signal readout unit includes a column amplification unit provided to be connected to each column of the plurality of photoelectric conversion units,
The solid-state imaging device according to claim 1, wherein the predetermined amplification factor is changed by changing an amplification factor of the column amplification unit. The plurality of photoelectric conversion units are arranged over a plurality of rows,
The signal readout unit is provided connected to each column of the plurality of photoelectric conversion units, and has a storage capacitor that temporarily holds a signal read from the photoelectric conversion unit,
4. The solid-state imaging device according to claim 1, wherein the predetermined amplification factor is changed by changing a capacitance value of the storage capacitor. 5. The signal reading unit has an output amplifier that amplifies a signal to be output;
5. The solid-state imaging device according to claim 1, wherein the predetermined amplification factor is changed by changing an amplification factor of the output amplifier. 6. The signal reading unit includes an AD conversion unit that converts an analog signal read from the plurality of photoelectric conversion units into a digital signal,
4. The solid-state imaging device according to claim 1, wherein the predetermined amplification factor is changed by changing a gain when the analog signal is converted into the digital signal. 5. A pixel having the partial photoelectric conversion unit and the other photoelectric conversion unit;
When generating an image signal based on a signal obtained by adding a signal read from the some photoelectric conversion unit and a signal read from the other photoelectric conversion unit, the partial photoelectric conversion is performed. 7. The solid-state imaging device according to claim 1, wherein a signal read out from the unit and a signal read out from the other photoelectric conversion unit are amplified with the same amplification factor. A first pixel having a first photoelectric conversion element that detects light in a first pupil region, and a first floating diffusion portion to which signal charges generated in the first photoelectric conversion element are transferred;
A focus detection pixel that is paired with the first pixel, a second photoelectric conversion element that detects light in a second pupil region different from the first pupil region, and the first photoelectric conversion A second pixel having a second floating diffusion portion to which signal charges generated in the element are transferred,
The solid-state imaging device, wherein a capacitance value of the first floating diffusion portion is different from a capacitance value of the second floating diffusion portion. A solid-state imaging device according to any one of claims 1 to 8,
An image pickup system comprising: a signal processing unit that generates a focus detection signal based on the signal of the first pixel and the signal of the second pixel output from the solid-state image pickup device. A pixel region in which a plurality of photoelectric conversion units are provided, and a part of the photoelectric conversion units of the plurality of photoelectric conversion units receives a part of pupil-divided light, and the plurality of photoelectric conversion units The other photoelectric conversion unit is a driving method of a solid-state imaging device having a pixel region in which other light divided into pupils is incident,
A method for driving a solid-state imaging device, wherein a signal read from the photoelectric conversion unit is amplified by changing an amplification factor according to a location where the photoelectric conversion unit is located in the pixel region.

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