JP2014078870A - Solid-state imaging element and imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To appropriately remove reset kTC noise during reading in a solid-state imaging element.SOLUTION: A reading circuit includes: a first amplifier circuit 12 which is electrically connected to a pixel electrode 104 for collecting a signal charge generated in a photoelectric conversion layer 107; a charge accumulating section Cp arranged in an input terminal of the first amplifier circuit 12; a second amplifier circuit 15 whose input terminal is electrically connected to an output terminal of the first amplifier circuit 12; an accumulation switch transistor 13 which is electrically connected to the input terminal of the second amplifier circuit 15; a capacitance section 14 which is electrically connected to the accumulation switch transistor 13; a writing transistor 18 installed between the first amplifier circuit 12 and a first amplifier circuit driving current source 19; and a reset transistor 17 which is electrically connected to the pixel electrode 104.

Description

  The present invention relates to a solid-state imaging device including a photoelectric conversion unit that generates charges when irradiated with light, and an imaging apparatus including the solid-state imaging device.

  In recent years, video cameras, digital cameras, and the like are widely used. For these cameras, a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor) image sensor is used, but a CMOS image sensor is becoming the mainstream instead of a CCD from any viewpoint capable of high-speed driving. .

  Recently, the area per pixel is reduced due to the increase in the number of pixels, and the reduction in sensitivity due to the reduction in the area of the light receiving portion has become a serious problem. As a solid-state imaging device that solves this problem, an organic CMOS sensor using an organic photoelectric conversion film in a light receiving portion has been proposed (for example, see Patent Document 1). This organic CMOS sensor has a structure in which an organic photoelectric conversion film as a light receiving portion is provided above a readout circuit and these are electrically connected by metal wiring. Even if the pixel size is reduced, the area of the light receiving portion can be increased, so that the sensitivity is high.

  The readout circuit of the pixel portion used in these CMOS image sensors, including the organic CMOS sensor, is a readout circuit using three transistors (hereinafter referred to as a 3Tr readout circuit) and a readout circuit using four transistors (hereinafter referred to as a “transistor”). Generally, any one of 4Tr readout circuits) is used. These circuits will be described.

  Patent Document 1 proposes a 3Tr readout circuit. In this circuit, the light receiving unit and the floating diffusion node FD are electrically connected directly, and a reset transistor is provided so as to reset the FD. Since this structure does not transfer charges from the light receiving portion, there is an advantage that problems such as transfer noise and afterimage do not occur even when the light receiving portion is not completely depleted.

  However, this 3Tr readout circuit generally has a problem that it cannot remove the reset kTC noise generated at the time of resetting.

  The reason is that, in the 3Tr readout circuit, first, signal readout is performed in a state where charges generated by exposure are accumulated in the FD, and then signal readout is performed in a state where the FD is reset. The difference between the obtained signals is obtained. In this case, reset kTC noise that is temporally random is generated in each of the reset signal before exposure and the reset signal after exposure described above. That is, the charge signal accumulated in the FD includes reset kTC noise at the time of reset before exposure, and this reset kTC noise is correlated with the reset kTC noise included in the signal read at the time of reset after exposure. Therefore, even if these are subtracted, the reset kTC noise at the time of reset before exposure cannot be removed.

  As the readout circuit, not only the 3Tr readout circuit as described above but also a 4Tr readout circuit has been proposed.

  The 4Tr readout circuit has a structure in which a transfer transistor is provided between the light receiving unit and the floating diffusion node FD. The reset transistor is provided to reset the FD. In this 4Tr readout circuit, reset kTC noise that cannot be removed by the 3Tr readout circuit can also be removed. The reason is that, in the configuration of the 4Tr readout circuit, before reading out the charge signal accumulated in the light receiving unit, first, the FD is reset and the signal at the time of resetting is read out, and then the transfer transistor is turned on by exposure. Since the generated charge signal is transferred from the light receiving unit to the FD, and the charge signal after the transfer is read, the signal is read at the time of reset and the transferred charge signal is read after one reset. It is. Therefore, the reset kTC noise can be removed by subtracting them.

  However, if the 4Tr readout circuit cannot completely transfer all signal charges from the light receiving unit to the FD, problems such as incomplete transfer noise and afterimage occur. For this reason, in the 4Tr readout circuit, it is necessary that the light receiving portion is completely depleted.

JP 2011-228621 A

  However, in a stacked solid-state imaging device such as an organic CMOS sensor, since the light receiving unit and the signal readout circuit are connected by metal wiring, the light receiving unit cannot be completely depleted. For this reason, the 4Tr readout circuit described above cannot be applied, and reset kTC noise occurs.

  In view of the above circumstances, an object of the present invention is to provide a solid-state imaging device capable of appropriately removing the above-described reset kTC noise and an imaging device including the solid-state imaging device.

  The solid-state imaging device of the present invention is electrically connected to a photoelectric conversion layer that generates a signal charge corresponding to the amount of incident light, a pixel electrode that collects the signal charge generated in the photoelectric conversion layer, and the pixel electrode. A first amplifier circuit; a charge storage section provided at an input terminal of the first amplifier circuit; a second amplifier circuit whose input terminal is electrically connected to an output terminal of the first amplifier circuit; A first switch element electrically connected to an input terminal of the amplifier circuit, a capacitor part electrically connected to the first switch element, a first amplifier circuit, and a first amplifier circuit driving current source, A plurality of pixel portions each including a second switch element provided between and a readout circuit including a reset circuit electrically connected to the pixel electrode are two-dimensionally arranged.

  Further, in the solid-state imaging device of the present invention, the capacity of the capacitor part can be made larger than the capacity of the charge storage part.

  Further, the first amplifier circuit can be operated only when the second switch element is turned on.

  In addition, the first amplifier circuit and the second amplifier circuit can be configured by a source follower circuit.

  In addition, a first amplifier circuit driving current source can be provided for each column of the pixel portion.

  Further, the capacitor portion can be formed of a MOS (Metal Oxide Semiconductor) capacitor, an MIM (Metal-Insulator-Metal) capacitor, or a PIP (Poly-Insulator-Poly) capacitor.

  In addition, after performing the reset operation by the reset circuit, the reset potential is accumulated in the capacitor portion by turning on the first switch element and the second switch element, and then the signal charge is accumulated in the charge accumulation portion. By turning on the first switch element, a reset signal corresponding to the reset potential stored in the capacitor unit is read out through the second amplifier circuit, and then the second switch element is further turned on to further charge the charge storage unit. A control unit can be provided for controlling to read out an accumulated signal corresponding to the signal charge accumulated in the second amplifier circuit via the second amplifier circuit.

  Further, it is possible to provide a signal processing unit that acquires a pixel signal by subtracting the reset signal from the accumulated signal read by the control unit.

  Further, the current of the first amplifier circuit driving current source is larger than the current value of the second amplifier circuit driving current source provided for the signal line to which the output terminal of the second amplifier circuit is electrically connected. The value can be made smaller.

  Further, the signal charge can be a hole, and the readout circuit can be constituted by an nMOS.

  Further, the photoelectric conversion layer can include an organic photoelectric conversion film.

  Further, the organic photoelectric conversion film can be common to all the pixel portions.

  An imaging apparatus according to the present invention includes the solid-state imaging device according to the present invention.

  According to the solid-state imaging device and the imaging apparatus of the present invention, the readout circuit includes a first amplifier circuit electrically connected to the pixel electrode, a charge storage unit provided at an input terminal of the first amplifier circuit, A second amplifier circuit whose input terminal is electrically connected to the output terminal of the first amplifier circuit; a first switch element electrically connected to the input terminal of the second amplifier circuit; A capacitor portion electrically connected to the first switch element; a second switch element provided between the first amplifier circuit and the first amplifier circuit driving current source; and the pixel electrode electrically Since the charge storage unit is reset by the reset circuit, the second switch element is turned on to turn on the first amplifier circuit driving current source. The first amplifier circuit can be operated, and the first By turning on the switch element, without charge transfer, such as a 4Tr read circuit described above, it is possible to accumulate a reset potential to the capacitor portion.

  Then, after storing the signal charge in the charge storage unit, the reset signal stored in the capacitor unit is read out via the second amplifier circuit by turning on the first switch element, and then Since the stored signal corresponding to the signal charge stored in the charge storage section can be read out via the second amplifier circuit by further turning on the second switch element, the reset signal is subtracted from the stored signal. Thus, the reset kTC noise can be appropriately removed.

  In addition, when the reset signal is read from the capacitor section or the accumulated signal is read from the charge storage section, the charge transfer operation is not performed as in the 4Tr readout circuit described above. Problems such as defects do not occur.

  Further, in the solid-state imaging device of the present invention, when the capacitance of the capacitor is larger than that of the charge storage unit, noise due to the second amplifier circuit can be ignored.

  In addition, since the first amplifier circuit can be operated only when the second switch element is turned on, when the first amplifier circuit is not used, the second switch element is turned off and the first amplifier circuit is turned on. Since the off operation can be performed, the power consumption of the first amplifier circuit can be reduced.

  In addition, when the first amplifier circuit and the second amplifier circuit are configured by source follower circuits, the areas of the first amplifier circuit and the second amplifier circuit can be reduced.

  Further, when the first amplifier circuit driving current source is provided for each column of the pixel portion, the first amplifier circuit driving current source can be shared by a plurality of pixel portions. Compared with the case where the first amplifier circuit driving current source is provided every time, the area per pixel can be reduced.

  Further, when the capacitor is formed by a MOS (Metal Oxide Semiconductor) capacitor, an MIM (Metal-Insulator-Metal) capacitor, or a PIP (Poly-Insulator-Poly) capacitor, the capacitor is formed from an impurity region. Compared with the case where it does, the influence of the incident of the leaked light to the capacitor portion can be reduced, and the dark current can also be reduced.

  Further, the current of the first amplifier circuit driving current source is larger than the current value of the second amplifier circuit driving current source provided for the signal line to which the output terminal of the second amplifier circuit is electrically connected. When the value is made smaller, the power consumption of the first amplifier circuit driving current source can be reduced.

  In addition, when the signal charge stored in the charge storage unit is a hole and the readout circuit is composed of an nMOS, the influence of dark current can be reduced.

The figure which shows the pixel part which comprises one Embodiment of the solid-state image sensor of this invention. Schematic cross-sectional view of an embodiment of a solid-state imaging device of the present invention The figure which shows the whole structure containing the peripheral circuit of the solid-state image sensor shown in FIG. The figure which shows the operation | movement sequence in the pixel part of the predetermined line in one Embodiment of the solid-state image sensor of this invention. Timing chart for explaining the operation of the pixel portion of one embodiment of the solid-state imaging device of the present invention

  Hereinafter, an embodiment of the solid-state imaging device of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating a circuit configuration of one pixel unit among a large number of pixel units constituting the solid-state imaging device of the present embodiment. The solid-state imaging device of the present embodiment has a large number of pixel portions 10 shown in FIG.

  As shown in FIG. 1, the pixel unit 10 includes a photoelectric conversion unit 11, a charge storage unit Cp, a first amplifier circuit 12, and a storage switch transistor 13 (corresponding to a first switch element in the claims). , Capacitor 14, second amplifier circuit 15, selection transistor 16, reset transistor 17 (corresponding to the reset circuit in the claims), and write transistor 18 (corresponding to the second switch element in the claims) And. The node PD and the floating diffusion node Fd are input nodes of the first and second amplifier circuits 12 and 15, respectively.

  In the present embodiment, the first amplifier circuit 12, the storage switch transistor 13, the second amplifier circuit 15, the selection transistor 16, the reset transistor 17, and the write transistor 18 are each composed of an n-channel MOS transistor. It is configured.

  The photoelectric conversion unit 11 includes a pixel electrode 104, a counter electrode 108 provided to face the pixel electrode 104, and a photoelectric conversion layer 107 provided between the pixel electrode 104 and the counter electrode 108.

  The pixel electrode 104 is an electrode divided for each pixel unit 10 and is formed of a transparent or opaque conductive material such as ITO, aluminum, or titanium nitride. The pixel electrode 104 collects charges generated in the photoelectric conversion layer 107 for each pixel unit 10.

  The counter electrode 108 is an electrode for applying a voltage to the photoelectric conversion layer 107 between the pixel electrode 104 and generating an electric field in the photoelectric conversion layer 107. Since the counter electrode 108 is provided on the light incident surface side of the photoelectric conversion layer 107 and needs to be transmitted through the counter electrode 108 and incident on the photoelectric conversion layer 107, the counter electrode 108 is transparent to the incident light. It is formed from a conductive material such as ITO. Note that the counter electrode 108 in the present embodiment is configured by one electrode common to all the pixel units 10, but may be configured to be divided for each pixel unit 10. In this embodiment, it is assumed that a positive bias voltage is applied to the counter electrode 108 and holes are collected by the pixel electrode 104.

  The photoelectric conversion layer 107 includes an organic photoelectric conversion film or an inorganic photoelectric conversion film that absorbs incident light and generates charges according to the absorbed light quantity. Note that a function of a charge blocking layer or the like that suppresses charge injection from the electrode to the photoelectric conversion layer 107 between the photoelectric conversion layer 107 and the counter electrode 108 or between the photoelectric conversion layer 107 and the pixel electrode 104. A layer may be provided.

  The node PD is an input node of the first amplifier circuit 12 and a node connecting the pixel electrode 104 and the readout circuit 116. Specifically, the node PD is a node in which the pixel electrode 104, the gate of the source follower circuit of the first amplifier circuit 12, and the drain of the reset transistor 17 are electrically connected. In order to connect the pixel electrode 104 and the readout circuit 116, an n-type impurity region is connected to the node PD. Therefore, the node PD cannot be completely depleted.

  The charge storage unit Cp is a charge storage unit connected to the node PD. The charge storage portion Cp is formed by the n-type impurity region of the node PD and the parasitic capacitance of the wiring. The potential of the node PD changes according to the amount of signal charges (electrons or holes) generated in the photoelectric conversion layer 107, collected in the pixel electrode 104, and accumulated in the charge accumulation unit Cp.

  The first amplifier circuit 12 has an input terminal electrically connected to the pixel electrode 104. The first amplifier circuit 12 is composed of a source follower circuit, and the drain terminal of the write transistor 18 is connected to the source terminal (output terminal). The source terminal of the write transistor 18 is connected to the power supply line L1, and a first amplifier circuit driving current source 19 is provided in the power supply line L1. The first amplifier circuit driving current source 19 is provided for operating the first amplifier circuit 12. When the write pulse applied to the gate terminal Write of the write transistor 18 becomes high level, the write transistor 18 is turned on. Only in this case, the first amplifier circuit driving current source 19 and the first amplifier circuit 12 are turned on. Accordingly, the first amplifier circuit 12 operates to output a desired signal from the output terminal of the first amplifier circuit 12. By controlling on / off of the write transistor 18 in this manner, the operation period of the first amplifier circuit 12 can be limited, and power consumption can be reduced.

  Further, the power supply line L1 and the first amplifier circuit driving current source 19 in the present embodiment are provided for each column of the pixel unit 10. That is, one first amplifying circuit driving current source 19 is commonly used for driving the first amplifying circuits 12 of the pixel units 10 in one column. Thus, by sharing the first amplifier circuit driving current source 19 in the plurality of pixel units 10 and not providing the current source in the pixel unit 10, the area of the pixel unit can be reduced.

  In addition, a second amplifier circuit driving current source 20 for operating the second amplifier circuit 15 is also provided for the signal line L2, but the capacitor unit 14 connected to the output terminal of the first amplifier circuit 12 is provided. Since the capacitance of the signal line L2 to which the second amplifier circuit 15 is connected is several pF, the current flowing through the first amplifier circuit driving current source 19 is at most several tens of fF. The value may be smaller than the current value supplied by the second amplifier circuit driving current source 20. This can also reduce power consumption.

  The floating diffusion node FD is connected to the gate of the second amplifier circuit 15 and is an input node of the second amplifier circuit 15. The floating diffusion node FD is also connected to the output of the first amplifier circuit 12.

  The storage switch transistor 13 is provided between the floating diffusion node FD and the capacitor unit 14. When the storage switch transistor 13 is turned on during the ON period of the first amplifier circuit 12, the output of the first amplifier circuit 12 is stored in the capacitor unit 14. Further, when the storage switch transistor 13 is turned on during the reading period, the signal stored in the capacitor unit 14 can be read out via the floating diffusion node FD and the second amplifier circuit 15.

  The capacitor 14 accumulates the signal voltage output from the first amplifier circuit 12 as described above. The capacitor 14 is preferably formed of a metal oxide semiconductor (MOS) capacitor, a metal-insulator-metal (MIM) capacitor, or a poly-insulator-poly (PIP) capacitor. By forming the capacitor portion 14 with these capacitors, it is possible to reduce the influence of leakage light incident on the capacitor portion 14 and to reduce the dark current as compared with the case where the capacitor portion 14 is formed from an impurity region. .

  Further, it is desirable that the capacitor portion 14 be formed so that its capacitance is larger than that of the charge storage portion Cp. By controlling the capacitance in this way, noise caused by the storage switch transistor 13 and the second amplifier circuit 15 can be ignored. As a method of controlling the capacity of the capacitor unit 14, for example, the area of the electrodes constituting the capacitor unit 14 may be controlled.

  The second amplifier circuit 15 is composed of a source follower circuit, and outputs a signal corresponding to the potential of the floating diffusion node FD to the signal line L2. A selection transistor 16 is connected to the output terminal (source terminal) of the second amplifier circuit 15. When the selection transistor 16 is turned on, the second amplifier circuit 15 and the second amplifier circuit driving current source 20 connected to the signal line L2 are connected, whereby the second amplifier circuit 15 is connected. Operates and a signal is output from the output terminal (source terminal) of the second amplifier circuit 15. The signal line L2 and the second amplifier circuit driving current source 20 are provided for each column of the pixel unit 10.

  The selection transistor 16 has a source terminal connected to the signal line L2, and selectively outputs a signal output from the second amplifier circuit 15 of each pixel unit 10 to the signal line L2 provided for each column. It is for output. When the selection pulse applied to the gate terminal RW of the selection transistor 16 becomes high level, the selection transistor 16 is turned on, whereby the signal output from the second amplifier circuit 15 of each pixel unit 10 is output to the signal line L2. Is done.

  The reset transistor 17 resets the potential of the node PD to the reference potential. A node PD is electrically connected to the drain terminal of the reset transistor 17, and a reset power source is connected to the source terminal, and the reference voltage RD1 is supplied by the reset power source. When the reset pulse applied to the gate terminal RS1 of the reset transistor 17 becomes high level, the reset transistor 17 is turned on, and the potential of the node PD is lowered and reset to the reference potential RD1.

  FIG. 2 is a schematic cross-sectional view of a solid-state imaging device 100 in which a large number of pixel portions 10 shown in FIG. 1 are arranged two-dimensionally. In FIG. 2, the same name and reference numeral are assigned to the same configuration as the pixel unit 10 illustrated in FIG. 1.

  As shown in FIG. 2, the solid-state imaging device 100 includes a circuit board 101, a wiring layer 102, a connection electrode 103, a pixel electrode 104, a connection wiring 105, a connection unit 106, a photoelectric conversion layer 107, An electrode 108, a sealing layer 110, a color filter 111, a light shielding layer 113, a protective layer 114, a counter electrode voltage supply unit 115, and a readout circuit 116 are provided.

  The circuit board 101 is formed with a readout circuit 116 and is made of a semiconductor substrate such as Si. A wiring layer 102 is formed on the circuit board 101, and the readout circuit 116 and the pixel electrode 104 are connected by a connection wiring 105 formed in the wiring layer 102. Further, the above-described power supply line L1 and signal line L2 are also formed in the wiring layer 102. A plurality of pixel electrodes 104 and one or more connection electrodes 103 are formed on the surface of the wiring layer 102.

  The photoelectric conversion layer 107 generates electric charge according to the received light as described above. The photoelectric conversion layer 107 is provided so as to cover the plurality of pixel electrodes 104. The photoelectric conversion layer 107 has a constant film thickness on the pixel electrode 104, but there is no problem even if the film thickness changes outside the pixel portion (outside the effective pixel area).

  The counter electrode 108 is an electrode facing the pixel electrode 104 and is provided so as to cover the photoelectric conversion layer 107. The counter electrode 108 is formed up to the connection electrode 103 arranged outside the photoelectric conversion layer 107 and is electrically connected to the connection electrode 103.

  The connection unit 106 is embedded in the wiring layer 102 and is a plug or the like for electrically connecting the connection electrode 103 and the counter electrode voltage supply unit 115. The counter electrode voltage supply unit 115 is formed on the circuit board 101 and applies a predetermined voltage to the counter electrode 108 via the connection unit 106 and the connection electrode 103. Note that the counter voltage supply unit 115 may be configured not directly on the circuit board 101 but directly connected to an external power source.

  The read circuit 116 includes the charge storage unit Cp, the first amplifier circuit 12, the storage switch transistor 13, the capacitor unit 14, the second amplifier circuit 15, the selection transistor 16, and the reset transistor illustrated in FIG. 17, a write transistor 18, a node PD, and a floating diffusion node FD, which are wired by metal wiring in the wiring layer 102. The readout circuit 116 is provided on the circuit board 101 corresponding to each of the plurality of pixel electrodes 104, and reads out a signal corresponding to the charge collected by the corresponding pixel electrode 104.

  The sealing layer 110 is provided so as to cover the counter electrode 108.

  The color filter 111 is formed at a position facing each pixel electrode 104 on the sealing layer 110. The light shielding layer 113 is formed in a region other than the region where the color filter 111 is provided on the sealing layer 110, and prevents light from entering the photoelectric conversion layer 107 formed outside the effective pixel region. As the color filter 111, for example, a Bayer color filter can be used. However, the color filter 111 is not limited thereto, and a complementary color filter or other known color filters can be used.

  The protective layer 114 is formed on the color filter 111 and the light shielding layer 113, and protects the entire solid-state imaging device.

  FIG. 3 is a diagram showing an overall configuration including peripheral circuits of the solid-state imaging device 100 shown in FIG. As shown in FIG. 3, the solid-state imaging device 100 according to the present embodiment includes a vertical driver 121, a control unit 122, a signal processing circuit 123, a horizontal driver 124, an LVDS 125, a serial conversion unit 126, and a pad 127. It has. The pixel area shown in FIG. 3 represents an area where the pixel portions 10 of the solid-state imaging device 100 shown in FIG. 2 are arranged.

  The control unit 122 includes a timing generator and the like. The control unit 122 outputs a frame synchronization signal VD and a row synchronization signal HD, and controls the operations of the vertical driver 121 and the horizontal driver 124 to control signal charges in the pixel unit 10. It controls reading and the like.

  In particular, the control unit 122 of the present embodiment resets the capacitor unit 14 via the first amplifier circuit 12 by turning on the storage switch transistor 13 and the write transistor 18 after performing a reset operation by the reset transistor 17. After accumulating the potential and then accumulating the signal charge in the charge accumulating unit Cp, the reset potential accumulated in the capacitor unit 14 is read through the second amplifier circuit 15 by turning on the accumulation switch transistor 13, and thereafter , By further turning on the write transistor 18, the signal corresponding to the signal charge stored in the charge storage unit Cp is controlled to be read from the node PD via the first amplifier circuit 12 and the second amplifier circuit 15. It is. The above-described control by the control unit 122 will be described in detail later.

  The vertical driver 121 outputs a reset pulse and a selection pulse to the reading circuit 116 based on the control signal output from the control unit 122, thereby controlling a reset operation and a signal charge reading operation in the reading circuit 116. Is. Further, the vertical driver 121 in the present embodiment outputs an accumulation pulse for turning on / off the accumulation switch transistor 13 in the read circuit 116 and a write pulse for turning on / off the write transistor 18.

  The signal processing circuit 123 is provided corresponding to each column of the readout circuit 116. The signal processing circuit 123 includes an ADC circuit that performs correlated double sampling (CDS) processing on the signals output from the corresponding columns and converts the processed signals into digital signals. The signal processed by the signal processing circuit 123 is stored in a memory provided for each column.

  The horizontal driver 124 performs control for sequentially reading out signals for one row of the pixel unit 10 stored in the memory of the signal processing circuit 123 and outputting the signals to the LVDS 125.

  The LVDS 125 transmits a digital signal in accordance with LVDS (low voltage differential signaling). The serial conversion unit 126 converts an input parallel digital signal into a serial signal and outputs it. The pad 127 is an interface used for input / output with the outside.

  Next, the operation of the solid-state imaging device 100 of this embodiment will be described.

  In the solid-state imaging device 100 of the present embodiment, each row of the pixel unit 10 is sequentially scanned in the column direction, and a reset operation, a reset potential accumulation, a reset potential read operation, and a charge signal read operation are performed for each row. . FIG. 4 simply shows a sequence of each operation in the pixel unit 10 in a predetermined row. In FIG. 4, the reading period is shown to be relatively long for the sake of explanation, but actually the reading period is negligibly shorter than the accumulation period and the discharging period.

  As shown in FIG. 4, first, the node PD is reset at the time t1 at the beginning of the exposure period, and the reset potential is stored in the capacitor unit 14 via the first amplifier circuit 12 and the storage switch transistor 13.

  In the subsequent exposure period, signal charges generated in the photoelectric conversion unit 11 are accumulated in the charge accumulation unit Cp via the pixel electrode 104.

  When the exposure period ends, the reading period starts. In the reading period, the reset potential stored in the capacitor unit 14 at the time t2 is first read out, and a reset signal corresponding to the reset potential is transmitted via the floating diffusion node FD, the second amplifier circuit 15, and the selection transistor 16. Is read out to the signal line L 2, and the reset signal is acquired by the signal processing circuit 123.

  Next, at time t3, a signal voltage corresponding to the signal charge stored in the charge storage unit Cp is transmitted from the node PD through the first amplifier circuit 12, the floating diffusion node FD, the second amplifier circuit 15, and the selection transistor 16. The signal is read out to the signal line L2, and the accumulated signal is acquired by the signal processing circuit 123.

  Then, the signal processing circuit 123 acquires a pixel signal by subtracting the reset signal from the input accumulated signal.

  After the pixel signal is acquired by such a series of operations, each pixel unit 10 is in the discharge period until the start of the next exposure period.

  The above is the sequence of each operation in the pixel unit 10 in a predetermined row.

  Next, detailed operation control of the reading circuit 116 when the sequence shown in FIG. 4 is executed will be described with reference to FIG.

  First, as shown in FIG. 5, a reset pulse is supplied to the gate terminal RS1 of the reset transistor 17, whereby the reset transistor 17 is turned on to reset the node PD.

  Immediately after the reset pulse becomes low level, the write pulse is supplied to the gate terminal Write of the write transistor 18 and the storage pulse is supplied to the gate terminal St of the storage switch transistor 13. As a result, the write transistor 18 is turned on to operate the first amplifier circuit 12, and the storage switch transistor 13 is turned on, so that a reset signal corresponding to the reset potential of the node PD is supplied to the first amplifier circuit 12 and the storage switch. Accumulated in the capacitor 14 via the transistor 13.

  During the exposure period in which the reset transistor 17 is off, the signal charge generated in the photoelectric conversion unit 11 is accumulated in the charge accumulation unit Cp via the pixel electrode 104, and the potential of the node PD changes.

  Reading is performed in a reading period after a predetermined exposure period has elapsed. During the reading period, the second amplifier circuit 15 operates when the selection transistor 16 is turned on, and a signal corresponding to the potential of the floating diffusion node FD is read through the second amplifier circuit 15 and the selection transistor 16. Is output to the signal line L2.

  In the read period, the potential of the floating diffusion node FD becomes the reset potential stored in the capacitor unit 14 by turning on the storage switch transistor 13 while the write transistor 18 is initially turned off. This reset potential is read through the second amplifier circuit 15 and the selection transistor 16 and output to the signal line L2. The reset signal output to the signal line L2 is acquired by the signal processing circuit 123.

  Next, in a state where the storage switch transistor 13 and the selection transistor 16 are turned on, a write pulse is further supplied to the gate terminal Write of the write transistor 18 so that the write transistor 18 is also turned on. As a result, when the first amplifier circuit 12 is operated, an accumulation signal corresponding to the signal charge accumulated in the charge accumulation unit Cp from the node PD becomes the first amplification circuit 12, the floating diffusion node FD, the second The data is read through the amplifier circuit 15 and the selection transistor 16 and output to the signal line L2. Then, the accumulated signal output to the signal line L2 is acquired by the signal processing circuit 123.

  The signal processing circuit 123 obtains a pixel signal by subtracting the accumulated signal and the reset signal obtained in this way.

  In addition, after the accumulated signal is read out in the pixel unit 10 as described above, a reset pulse is further supplied to the gate terminal RS1 of the reset transistor 17, whereby the reset transistor 17 is also turned on. The node PD, the floating diffusion node FD, and the capacitor unit 14 are reset.

  After the exposure / reading is completed by such a series of operations, each pixel unit 10 is in the discharge period until the start of the next exposure period.

  A series of operations as described above are sequentially performed for each row of the pixel unit 10, and an image signal of the first frame is acquired.

  Then, the image signal of the second frame is acquired again by performing the same series of operations as described above, and then the image signal of each frame is sequentially acquired by sequentially repeating the same processing.

  According to the solid-state imaging device 100 of the above-described embodiment, the reset operation of the node PD is performed by the reset transistor 17, and then the storage switch transistor 13 and the write transistor 18 are turned on by the first amplifier circuit driving current source 19. Since the first amplifier circuit 12 can be operated, a reset potential can be accumulated in the capacitor unit 14 without charge transfer as in the 4Tr readout circuit described above.

  At the time of reading, by turning on the storage switch transistor 13, a reset signal corresponding to the reset potential stored in the capacitor unit 14 is read through the second amplifier circuit 15, and then the write transistor 18 is further turned on. Thus, the accumulated signal corresponding to the signal charge accumulated in the charge accumulating unit Cp during the exposure period can be read out from the node PD via the second amplifier circuit 15, and reset by subtracting the reset signal from the accumulated signal. kTC noise can be appropriately removed.

  Further, when the reset signal is read from the capacitor unit 14 or the accumulated signal is read from the node PD, the charge transfer operation as in the above-described 4Tr read circuit is not performed. The problem does not occur.

  The switching noise associated with the on / off operation of the storage switch transistor 13 can be ignored because it is sufficiently small because the capacitance of the capacitor portion 14 is larger than the capacitance of the charge storage portion Cp.

  In the solid-state imaging device 100 of the above-described embodiment, a positive bias voltage is applied to the counter electrode 108 and holes are collected by the pixel electrode 104. However, the present invention is not limited to this. May be applied to collect electrons by the pixel electrode 104.

  In the solid-state imaging device 100 of the above embodiment, an nMOS is used for each transistor of the readout circuit 116. However, a pMOS may be used.

  Although the reset transistor is turned off during the discharging period at the drive timing described above, it may be turned on.

  In the case of collecting holes with the pixel electrode, a protection circuit for preventing the potential of the node PD from being excessively increased may be provided. As a result, a failure due to an excessive increase in the potential of the node PD can be suppressed.

  In addition, the solid-state imaging device of the above-described embodiment can be used for various imaging devices. Examples of the imaging device include a digital camera, a digital video camera, an electronic endoscope, and a camera-equipped mobile phone.

DESCRIPTION OF SYMBOLS 10 Pixel part 11 Photoelectric conversion part 12 1st amplifier circuit 13 Accumulation switch transistor 14 Capacity | capacitance part 15 2nd amplifier circuit 16 Selection transistor 17 Reset transistor 18 Transistor 19 Current source 100 for amplifier circuit drive Current source 100 for amplifier circuit drive Solid Image sensor 104 Pixel electrode 107 Photoelectric conversion layer 116 Read circuit 122 Control unit 123 Signal processing circuit FD Floating diffusion node L1 Power supply line L2 Signal line Cp Charge storage unit PD Input node of the first amplifier circuit

Claims (13)

A photoelectric conversion layer that generates a signal charge according to the amount of incident light;
A pixel electrode that collects signal charges generated in the photoelectric conversion layer;
A first amplifier circuit electrically connected to the pixel electrode, a charge storage portion provided at an input terminal of the first amplifier circuit, and an input terminal electrically connected to an output terminal of the first amplifier circuit A second amplifying circuit connected to the first amplifying circuit; a first switching element electrically connected to an input terminal of the second amplifying circuit; a capacitance unit electrically connected to the first switching element; A pixel unit including a second switch element provided between one amplifier circuit and a first amplifier circuit driving current source and a readout circuit including a reset circuit electrically connected to the pixel electrode; A solid-state imaging device, wherein a plurality of two-dimensional arrays are arranged.   The solid-state imaging device according to claim 1, wherein a capacity of the capacitor section is larger than a capacity of the charge storage section.   3. The solid-state imaging device according to claim 1, wherein the first amplifier circuit operates only when the second switch element is turned on. 4.   4. The solid-state imaging device according to claim 1, wherein the first amplifier circuit and the second amplifier circuit are configured by a source follower circuit. 5.   5. The solid-state imaging device according to claim 1, wherein the first amplifier circuit driving current source is provided for each column of the pixel portion. 6.   6. The capacitor according to claim 1, wherein the capacitor is formed of a metal oxide semiconductor (MOS) capacitor, a metal-insulator-metal (MIM) capacitor, or a poly-insulator-poly (PIP) capacitor. The solid-state image sensor of Claim 1.   After performing the reset operation by the reset circuit, the first switch element and the second switch element are turned on to store a reset potential in the capacitor unit, and then the signal charge is stored in the charge storage unit. After the accumulation, by turning on the first switch element, a reset signal corresponding to the reset potential accumulated in the capacitor unit is read out through the second amplifier circuit, and then the second switch element is 7. A control unit that further controls to read an accumulated signal corresponding to a signal charge accumulated in the charge accumulating unit through the second amplifier circuit when turned on. The solid-state image sensor of any one of Claims.   The solid-state imaging device according to claim 7, further comprising a signal processing unit that acquires a pixel signal by subtracting the reset signal from the accumulated signal read by the control unit.   The current of the first amplifier circuit driving current source is larger than the current value of the second amplifier circuit driving current source provided for the signal line to which the output terminal of the second amplifier circuit is electrically connected. 9. The solid-state imaging device according to claim 1, wherein the value is smaller. The signal charge is a hole;
The solid-state imaging device according to claim 1, wherein the readout circuit is configured by an nMOS.   The solid-state imaging device according to claim 1, wherein the photoelectric conversion layer includes an organic photoelectric conversion film.   The solid-state imaging device according to claim 11, wherein the organic photoelectric conversion film is common to all the pixel portions.   An imaging apparatus comprising the solid-state imaging device according to claim 1.

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