JP2004040148A - Solid-state imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging element realizing random access reading without the need for a complicated image processing circuit. <P>SOLUTION: The solid-state imaging element comprising: a pixel section 2 partitioned into blocks in the unit of a positive number; horizontal and vertical shift registers 32, 41 provided with output terminals each provided to number of pixels of an integer multiple of the unit block; a CDS circuit 31 for storing imaging signals outputted by scanning of the vertical shift register 41; an output port 6 for outputting the imaging signals outputted form the CDS circuit 31; and a block unit image processing circuit 8 having a memory 81 and applying image processing to the imaging signals outputted from the output port 6, and is provided with an external input means 5 for setting a prescribed random access read area of the pixel section 2; and vertical and horizontal address control means 33, 42 for outputting horizontal and vertical addresses of the prescribed random access read area to the horizontal and vertical shift registers 32, 41. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a solid-state imaging device, and more particularly, to a CMOS image sensor capable of performing random access reading without complicated signal processing.
[0002]
[Prior art]
FIG. 4 is a schematic plan view showing a conventional solid-state imaging device.
5A and 5B are timing charts for explaining the operation of the conventional solid-state imaging device. FIG. 5A shows a field start signal, FIG. 5B shows a vertical clock, and FIG. 5C shows a horizontal clock. is there.
As shown in FIG. 4, the conventional solid-state imaging device includes a pixel section 2, a vertical shift register 41, a horizontal output circuit 10, an output port 6 for outputting a signal from the horizontal output circuit 10, an AD converter 7, , A solid-state image sensor called a CMOS image sensor, which includes a block unit image processing circuit 8 including a field memory 11 and an image processed signal output port 9.
[0003]
The pixel unit 2 includes a large number of pixels arranged in a two-dimensional matrix. Each pixel photoelectrically converts incident subject light to generate a charge corresponding to the amount of incident light, and transfers the charge. The storage unit includes a storage unit that stores the data, and an output transistor that outputs a potential change due to the charge from the storage unit to the outside of the pixel at a predetermined timing as an imaging signal.
[0004]
The horizontal output circuit 10 includes a CDS (Correlated Double Sampling: correlated double sampling) circuit 31 and a horizontal shift register 32.
The CDS circuit 31 removes noise of the imaging signal output from the pixel unit 2, and the horizontal shift register 32 selects a pixel column of the pixel unit 2 and outputs an imaging signal.
[0005]
The AD converter 7 converts an analog signal output from the output port 6 into a digital signal. After storing the digital signal converted by the AD converter 7 in the field memory 11, the block unit image processing circuit 8 performs code conversion by JPEG or the like.
At the time of normal reading, an imaging signal is output to the output port 6. Note that the AD converter 7 and the block unit processing circuit 8 may be formed on a single chip in a CMOS image sensor. From an external circuit (not shown), vertical and horizontal clock pulses having a predetermined timing are output to the vertical and horizontal shift registers 41 and 32, respectively.
[0006]
Next, reading of a conventional solid-state imaging device will be described.
Here, the start position of the vertical shift register 41 and the horizontal shift register 32 is the lower left end.
As shown in FIGS. 5A and 5B, a vertical clock pulse is output from an external circuit (not shown) to the vertical shift register 41 based on the field start signal. Thus, the lowermost row register of the vertical shift register 41 is set to “1”, and the registers other than the lowermost row are set to “0” to select the pixel of the lowermost row.
[0007]
Next, the imaging signal output from the pixel in the lowermost row is subjected to noise cancellation in the CDS circuit 31, and is then stored in a memory in the CDS circuit 31.
Subsequently, as shown in FIG. 5C, a horizontal clock pulse is output to the horizontal shift register 32 after a predetermined timing of outputting the vertical clock pulse from the external circuit (not shown). In this way, the leftmost column CDS circuit 31 is selected, one horizontal clock pulse is sent from the external circuit (not shown) to the horizontal shift register 32, and the position of "1" in the shift register is shifted rightward by one column from the leftmost column. After moving in order, the imaging signal in the bottom row is stored in the memory of the CDS circuit 31, and then output from the output port 6. When the above operation is completed, the register of the horizontal shift register 32 is reset to “0”.
[0008]
Next, one vertical clock pulse is output from the external circuit (not shown) to the vertical shift register 41, and the register is moved upward one by one from the bottom row. Do. Then, all the registers of the horizontal shift register 32 and the vertical shift register 41 are reset to “0”, and the operation for one field is performed.
After all the analog imaging signals output from the output port 6 are converted into digital signals by the AD converter 7, the signals are stored in the field memory 11 of the block unit image processing circuit 8. For reading out the image signal stored in the field memory 11, the image signal is output from the block unit image processing circuit 8 to the image processed signal output port 9.
[0009]
The random access is performed by a processing circuit at the subsequent stage of the block-based image processing circuit 8, and a necessary area of all the image pickup signals stored in the field memory 11 is selectively processed.
[0010]
[Problems to be solved by the invention]
However, when random access is performed, as described above, since all image signals are fetched into the field memory 11 and selective image processing is performed, the signal processing in the block unit image processing circuit 8 takes a considerable time. And the configuration of the block unit image processing circuit 8 becomes complicated.
[0011]
The present invention has been made in view of the above problems, and has as its object to provide a random-access-readable solid-state imaging device that does not require a complicated image processing circuit.
[0012]
[Means for Solving the Problems]
The present invention includes a pixel portion in which a plurality of imaging pixels are formed in a matrix, and the imaging pixels are divided by an integer multiple of a unit block, and an output terminal corresponding to each pixel of the unit block in a row direction. A vertical shift register, a horizontal shift register having an output terminal corresponding to each pixel of the unit block in the column direction, and noise canceling of the row direction imaging signal output by vertical scanning of the vertical shift register. After performing the operation, a CDS circuit that accumulates an image signal, an output port that outputs the image signal output from the CDS circuit by horizontal scanning of the horizontal shift register, and a memory are output from the output port. A solid-state imaging device comprising: a block-based image processing circuit for performing image processing from the imaging signal; External input means for setting a predetermined random access read area, vertical address control means for outputting a vertical address of the predetermined random access read area to the vertical shift register in units of a preset block, And a horizontal address control means for outputting a horizontal address of an access read area to the horizontal shift register in the unit of the preset block.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
A solid-state imaging device according to an embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a schematic plan view illustrating a solid-state imaging device according to an embodiment of the present invention.
FIG. 2 is an enlarged view of the horizontal shift register unit.
3A and 3B are timing charts of the solid-state imaging device according to the embodiment of the present invention. FIG. 3A is a field start signal supplied to the vertical clock control circuit 43 and the horizontal address control circuit 34, and FIG. FIG. 3C is a diagram showing a horizontal clock pulse. The same components as those of the conventional example are denoted by the same reference numerals, and the description thereof will be omitted.
As shown in FIG. 1, a solid-state imaging device 1 according to an embodiment of the present invention includes a pixel unit 2, a horizontal shift register unit 3, a vertical shift register unit 4, and an external signal input circuit, which are divided into predetermined blocks. 5, an output port 6, an AD converter 7, a block unit image processing circuit 8, and an image processed signal output port 9.
[0014]
As shown in FIG. 1, it is assumed that the pixel unit 2 has 8 × 8 pixels as a basic block unit and is divided by an area that is an integral multiple of the basic block unit. It is a region surrounded by the range up to the eyes and the range from the C-th column to the D-th column. When m ₀ , m, m ₁ , n ₀ , n, and n ₁ are positive integers and the upper left end of the pixel unit 2 is a start position, each of the A-th row, the B-th row, and the last row is When represented by a matrix of pixels, the pixel rows are 8 × m ₀ pixel rows, 8 × (m ₀ + m) pixel rows, and 8 × (m ₀ + m + m ₁ ) pixel rows below the start position, and the C column, D column each of th column and the last column, 8 × _{n 0} pixel-th column from the start position to the _{right, 8 × (n 0 + n} ) pixel th column and _{8 × (n 0 + n +} n 1) is the pixel-th column.
[0015]
As shown in FIGS. 1 and 2, the horizontal shift register unit 3 includes a CDS circuit 31, a horizontal shift register 32, a horizontal address control circuit 33, and a horizontal address control circuit 34, and selects a column and outputs a signal. Output and horizontal address control at random access.
The horizontal shift register 32 has an input terminal for reading an image signal for every eight pixels. The horizontal address control circuit 33 has an output terminal corresponding to the input terminal of the horizontal shift register 32 for every eight pixels.
The horizontal address control circuit 34 outputs a signal indicating a random access read start position to the horizontal shift register 32.
[0016]
The vertical shift register unit 4 includes a vertical shift register 41, a vertical address control circuit 42, and a vertical clock control circuit 43, and performs row selection, pixel control, and address control during random access.
The vertical address control circuit 42 has a configuration similar to that of the horizontal address control circuit 33, and outputs a signal indicating the read start position of the random access area to the vertical shift register 41.
The vertical clock control circuit 43 outputs a signal indicating a random access read start position to the vertical shift register 42, similarly to the horizontal address control circuit 34.
[0017]
The external signal input circuit 5 outputs a signal in a read range of the random access read area.
The block unit image processing circuit 8 has a memory 81 smaller than the conventional field memory 11.
Here, since it is assumed that signal processing is performed in units of 8 × 8 pixel basic blocks, the memory 81 only needs to have a storage amount of at least 8 rows or 16 rows which is twice as large. When the pixel unit 2 is a VGA (640 × 480 pixels), the capacity of the memory 81 is about 1.7% to 3.3% of the case where one field of the VGA is stored. Few.
[0018]
Next, a random access operation of the solid-state imaging device according to the embodiment of the present invention will be described with reference to FIG.
As shown in FIG. 3A, the vertical clock pulse and the horizontal clock pulse are output from the vertical clock control circuit 43 and the horizontal address control circuit 34 to the vertical shift register 41 and the horizontal shift register 32 based on the field start signal.
At this time, all the registers of the vertical shift register 41 and the horizontal shift register 32 are 0.
[0019]
As shown in FIG. 3B, one vertical clock pulse is output from the vertical clock control circuit 43 to the vertical shift register 41, and at the same time, the vertical shift register 41 corresponds to the (8 × m ₀ ) pixel row in row A in the random access readout area. An address signal is output from the external signal input circuit 5 to an output terminal of the vertical address control circuit. At this time, as shown in FIG. 3D, the register of the vertical shift register 41 becomes “1”. Other registers are “0”. After the imaging signal output from the (8 × m ₀ ) pixel row is subjected to noise cancellation by the CDS circuit 31, it is stored in a memory in the CDS 31 circuit.
[0020]
As shown in FIGS. 3C and 3E, one horizontal clock pulse is output from the horizontal address control circuit 34 to the horizontal shift register 32, and at the same time, the 8 × n ₀ pixel column of the C-th column in the random access readout area is output. An address signal is output from the external signal input circuit 5 to an output terminal of the horizontal address control circuit 33 corresponding to the eye. At this time, the register of the horizontal shift register 32 becomes “1”. Other registers are “0”. Then, every time one horizontal clock pulse is sent, the position of the register “1” is horizontally scanned up to the 8 × (n ₀ + n) pixel column of the D column, and the imaging signal is output from the output port 6.
Then, the imaging signal output from the output port 6 is converted into a digital signal by the AD converter 7 and then stored in the memory 81 of the block unit image processing circuit 8.
[0021]
Next, one vertical clock pulse is output from the vertical shift register 41 shown in FIG. 3B, and the register position “1” of the vertical shift register 41 is lowered by one. That is, the register position “1” is set to the 8 × (m ₀ +1) pixel row.
After the imaging signal output from the 8 × (m ₀ +1) -th pixel row is subjected to noise cancellation by the CDS circuit 31, it is stored in a memory in the CDS 31 circuit.
Next, in the same manner as described above, the horizontal scanning is performed from the (8 × n ₀ ) pixel column to the 8 × (n ₀ + n) pixel column, and the image pickup signal is output from the output port 6. Then, the imaging signal output from the output port 6 is converted into a digital signal by the AD converter 7 and then stored in the memory 81 of the block unit image processing circuit 8.
[0022]
The block unit image processing circuit 8 starts processing when accumulating the imaging signals for eight pixel rows, and outputs a block imaging image of the random access read area from the image processed signal output port 9. After that, the memory 81 is reset and waits for the input of the next imaging signal.
The above vertical and horizontal scans are sequentially performed to process all the imaging signals in the random access readout area output from the output port 6, and a block image of the random access readout area is output from the image processed signal output port 9.
[0023]
As described above, according to the embodiment of the present invention, since the pixel unit 2 has 8 × 8 pixels as a basic block unit and is divided by an area which is an integral multiple of this basic block unit, the pixel unit 2 performs processing in block units. Therefore, the configuration of the block-based image processing circuit 8 is simplified, and high-speed processing can be performed. Further, since image processing is performed by reading only the random access read area, a large-scale memory is not required, so that high-speed processing can be performed.
In the embodiment of the present invention, 8 × 8 pixels are used as a basic block unit. However, when p is a positive integer, a solid-state imaging device having an image processing circuit using (p × p) pixels as a basic block unit Needless to say, the present invention can also be applied to
[0024]
【The invention's effect】
According to the present invention, a plurality of imaging pixels are formed in a matrix, and the imaging pixels are divided by an integer multiple of a unit block, and an output terminal corresponding to each pixel of the unit block in a row direction. A vertical shift register including: a horizontal shift register including, in a column direction, an output terminal corresponding to each pixel of the unit block; and a noise of the imaging signal in the row direction output by vertical scanning of the vertical shift register. A CDS circuit for accumulating an image signal after canceling, an output port for outputting the image signal output from the CDS circuit by horizontal scanning of the horizontal shift register, and a memory; A block-based image processing circuit that performs image processing from the imaging signal to be processed. An external input means for setting a predetermined random access read area, a vertical address control means for outputting a vertical address of the predetermined random access read area to the vertical shift register in a predetermined block unit, And a horizontal address control means for outputting the horizontal address of the random access read area to the horizontal shift register in the preset block unit. Can be simplified, and high-speed processing can be performed. Further, since image processing is performed by reading only the random access read area, a large-scale memory is not required, so that high-speed processing can be performed.
[Brief description of the drawings]
FIG. 1 is a schematic plan view showing a solid-state imaging device according to an embodiment of the present invention.
FIG. 2 is an enlarged view of a horizontal shift register unit.
3A and 3B are timing charts of the solid-state imaging device according to the embodiment of the present invention, wherein FIG. 3A shows a field start signal, FIG. 3B shows a vertical clock pulse, and FIG. 3C shows a horizontal clock pulse. is there.
FIG. 4 is a schematic plan view showing a conventional solid-state imaging device.
FIGS. 5A and 5B are timing charts for explaining the operation of the conventional solid-state imaging device. FIG. 5A shows a field start signal, FIG. 5B shows a vertical clock pulse, and FIG. 5C shows a horizontal clock pulse. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Solid-state image sensor, 2 ... Pixel part, 3 ... Horizontal shift register part, 31 ... CDS circuit, 32 ... Horizontal shift register, 33 ... Horizontal address control circuit, 34 ... Horizontal address control circuit, 4 ... Vertical shift register part, 41 vertical shift register, 42 vertical address control circuit, 43 vertical clock control circuit, 5 external signal input circuit, 6 output port, 7 AD converter, 8 block unit image processing circuit, 81 memory, 9 … Image processed signal output port

Claims (1)

A pixel portion in which a plurality of imaging pixels are formed in a matrix, and the imaging pixels are divided by an integer multiple of a unit block;
A vertical shift register having an output terminal corresponding to each pixel of the unit block in the row direction;
A horizontal shift register having an output terminal corresponding to each pixel of the unit block in the column direction;
A CDS circuit that accumulates an imaging signal after performing noise cancellation on the imaging signal in the row direction output by the vertical scanning of the vertical shift register;
An output port for outputting the image signal output from the CDS circuit by horizontal scanning of the horizontal shift register;
A solid-state imaging device having a memory, and a block-based image processing circuit that performs image processing from the imaging signal output from the output port;
External input means for setting a predetermined random access readout area among all the imaging areas of the pixel unit,
Vertical address control means for outputting a vertical address of the predetermined random access read area to the vertical shift register in a unit of a preset block;
A solid-state imaging device, comprising: a horizontal address control unit that outputs a horizontal address of the predetermined random access read area to the horizontal shift register in the unit of the preset block.

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