JPH08149361A - Digital camera - Google Patents

Abstract

PURPOSE: To attain the input of a still image with high image quality by applying A/D conversion to outputs of full pixel image pickup elements, storing the converted signal to a memory, and using a microprocessor to conduct video signal processing in terms of software. CONSTITUTION: All information obtained by an image pickup element is used for information by one pattern at the same time by using the image pickup element (full pixel image pickup element) 101 capable of providing outputs of all pixels for one field period. Then the output of the full pixel image pickup element 101 is A/D-converted and stored in a frame memory 105, and a microprocessor 107 is used to apply processing to a video signal in terms of software thereby attaining high image quality video signal processing in excess of the capability of a moving image digital signal processor DSP 109. Then generated high image quality still image data are outputted without being converted into an analog signal. Furthermore, an adder 108 converts full pixel data into interlace scanning data and the converted data are given to the DSP 109, from which moving image data are obtained and the data are given to a D/A converter 110, from which analog signal data are obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital camera used for inputting image data into a computer or the like.

[0002]

2. Description of the Related Art A conventional digital camera will be described below with reference to the drawings.

FIG. 7 shows a conventional computer image input system. Reference numeral 701 is a video camera that outputs an analog video signal based on a standard such as NTSC or PAL, 702 is a video signal transmission cable, and 703 is a video signal transmission cable.
A capture board that converts the analog video signal into digital data and stores the digital data. The capture board extracts a synchronization signal from the video signal, generates a clock synchronized with the video signal, a PLL circuit 704, a decoder circuit 705 that converts the video signal into three primary color signals (hereinafter, referred to as RGB signals), A / D converter 706,
The buffer memory 707 stores RGB signals.

FIG. 8 shows the structure of another prior art. 801
Numeral 802 is a personal computer input dedicated camera equipped with a digital interface, numeral 802 is a cable for a personal computer peripheral equipment connection standard interface represented by SCSI, and numeral 803 is a personal computer. PC input camera 8
The configuration of 01 is as follows.

Reference numeral 804 denotes an image sensor, 805 an A / D converter for converting an image sensor output signal into digital data, and 806 processing the image sensor signal to convert it into a video signal composed of a luminance signal and a color signal. Is a DSP that
Reference numeral 807 denotes a memory that stores the output signal of the DSP.
Reference numeral 808 denotes a connection interface unit with a peripheral device connection standard interface for a personal computer represented by SCSI. As the image sensor 804 and the DSP 806, those for moving images which are widely available due to problems such as cost are used.

[0006]

However, in the above configuration, the method of converting the analog signal of the general video camera shown in FIG. 7 into digital data by the capture board provided on the computer side is the capture method. Because the board is costly and the video camera that outputs the interlaced signal is used, 1
Since the number of lines on the screen is only half the number of lines on the image sensor, it is not optimal for still image input in terms of image quality.

Further, in the camera provided with the digital interface as shown in FIG. 8, since it is digitally connected, it is more advantageous in image quality than the system of FIG. 7, but
Since the image pickup device and the signal processing unit are for moving images, this is also not optimal for still image input.

The present invention solves the above problems and provides a digital camera which realizes high-quality still image input, and can further improve the image quality of still image input in a capture board type input system. The purpose is to provide.

[0009]

According to the present invention, by using an image pickup device capable of outputting all pixels in one field period (referred to as an all-pixel image pickup device), all information of the image pickup device can be obtained at the same time. Used as screen information. Then, the output of the all-pixel image sensor is A / D converted and stored in a memory, and a video signal processing is performed by a microprocessor in a software manner so that a digital signal processor for moving images (hereinafter, referred to as DS).
High-quality video signal processing, which cannot be done by P) is performed. Then, the generated high quality still image data is output without being converted into an analog signal.

Also, a conventional moving picture DSP for outputting a moving picture.
The adder converts all pixel data into interlaced scan data and inputs it to the DSP to obtain moving image data.
The moving image data is output as an analog signal by the D / A converter.

Further, all pixel data stored in the memory are input to the DSP so as to be interlaced between the fields, and an analog signal having no time difference between the fields is output. This makes it possible to obtain a complete frame image even when an image is captured by an analog signal.

[0012]

With the above structure, high-quality still image data can be obtained without increasing the cost. Also,
The analog signal also becomes a signal suitable for still image input, and the image quality of still images can be improved even in the system using the conventional capture board.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a digital camera of this embodiment. First, the high-quality still image mode will be briefly described.

In FIG. 1, reference numeral 101 denotes an all-pixel image pickup element, which outputs signals of all lines in one field period by simultaneously outputting signals of two lines. An image sensor driving unit 102 drives the all-pixel image sensor. Reference numeral 103 denotes a sync signal generator that generates a sync signal. An A / D converter 104 converts an image sensor output signal into digital data (hereinafter referred to as all pixel data). A frame memory 105 stores all pixel data. Reference numeral 106 is a memory controller, which is based on the synchronization signal
Control 5 A microprocessor 107 processes all pixel data stored in the frame memory 105 to generate high-quality still image data on the frame memory 105. A digital interface 111 outputs the still image data to the outside.

Next, the analog signal output will be briefly described. In FIG. 1, the all-pixel image sensor 101 outputs signals of all pixels in one field period by simultaneously outputting signals of two lines. Image sensor driving unit 102
Drives the all-pixel image sensor. Sync signal generator 103
Generate a synchronization signal. The A / D converter 104 is
The image sensor output signal is converted into digital data (referred to as all pixel data). The adder 108 adds two adjacent lines of all the pixel data and converts them into an interlaced scan signal. The DSP 109 processes the interlaced scan signal and generates moving image data including a luminance signal and a color signal. The D / A converter 110 converts the moving image data into an analog signal.

The operation of each unit will be described in detail below. FIG. 2 is a schematic diagram showing the relationship between the pixels of the all-pixel image sensor and the output signals. In FIG. 2, the photodiode 2
The signal charge is transferred from 01 to the vertical transfer CCD 202,
Then, it is transferred to the horizontal transfer CCDs 203 and 204.
Then, the output amplifiers 205 and 206 simultaneously output two lines as a voltage signal. In the A field,
First, the first line and the second line are simultaneously output. B
In the field, after the first line is output from the output amplifier 205, the second and third lines are simultaneously output. Therefore, if you add two lines that are output simultaneously,
It is possible to generate an interlaced signal between both fields. In normal operation, the interlaced signal is always input to the DSP, and a normal interlaced video signal is output from the analog signal output. In either case, the data of all pixels can be stored in the field memory.

Next, the operation when the still image recording operation is performed will be described. In FIG. 1, the timing of recording a still image is designated by an external switch or the like. At that time, all pixel data is stored in the frame memory 105, but it is desirable to output a still image from the analog signal output in order to confirm what image has been input. In that case, data is sent from the frame memory 105 to the DSP 109, and still image data is output from the DSP 109. The situation is shown in FIG.

The signals output from the all-pixel image pickup device 301 are converted into digital data by the A / D converter 302 and stored in the frame memory 303. The frame memory 303 has two storage areas 304 and 305,
The odd lines are stored in 304 and the even lines are stored in 305. For the stored data, the first and second lines are simultaneously output in the A field, and the second and third lines are simultaneously output in the B field.
The output data is added to two lines by the adder 306 and sent to the DSP 307. By this operation, DSP
Data interlaced between the A field and the B field is input to 307, and a normal interlaced video signal is output from the DSP 307. The signals of the two fields are data at the same time, and if the two fields are taken in and combined, a complete frame still image can be obtained. Therefore, a complete frame still image can be obtained even when the image is captured by the conventional capture board, and thus a still image of higher image quality than that of the conventional camera can be obtained.

Next, the high-quality still image processing will be described. The still image obtained from the analog signal has a frame amount (all pixels) in the sense of the data amount, but the processing is that the signal processed for a moving image has two fields, so that all pixel imaging is performed. Not all pixel data obtained from the device can be effectively used for still images. For example, since two lines are added, the vertical spatial frequency characteristic is deteriorated. Further, since the processing is performed with the interlaced signal, the vertical spatial frequency characteristic correction (vertical aperture correction) cannot be sufficiently performed up to the high frequency range.
Further, the band of the color signal is suppressed to 1/4 of the luminance signal. In order to solve these problems, it is necessary to drastically change the processing contents, but it is not cost effective to develop a dedicated LSI. Further, since it is still image processing, there is little problem even if the processing time is long.
Therefore, still image processing is performed by software processing by a microprocessor. The soft processing provides a degree of freedom in selecting the combination of the image quality and the processing time, and the output form is not limited to the luminance and color signals, and can be easily the three primary color signals (RGB signals). Since the processing is performed by the microprocessor, it is desirable that the frame memory that stores all pixel data can be used as a work area when the processing of the microprocessor is performed and that the processed data can also be stored. Therefore, the frame memory is
It can be used as a normal RAM that can be randomly accessed by the microprocessor.

FIG. 4 shows an example of the structure of the frame memory of the present invention. The frame memory 401 is the SAM port 40
2, line buffer 403, DRAM cell 404, RA
It is composed of an M port 405. A / D converter 40
All pixel data output from No. 6 is SAM port 402
Are sequentially input to the line buffer 403.
The data in the line buffer 403 is collectively transferred to the DRAM cell 404. MPU4 for RAM port 405
11 and the digital interface 412 are connected. The MPU can randomly access the DRAM cell 404 from the RAM port. With this configuration, video input,
Alternatively, the MPU 411 can randomly access the frame memory 401 while outputting a video. In addition, the selector 410 is connected to the output of the DSP 408 and the frame memory 401.
Output is input to the D / A converter 409.
The high-quality still image processing is sequentially performed in units of 6 to 12 lines. That is, three types of data areas, that is, after processing, during processing, and before processing, are generated with the line as a boundary. By switching the D / A converter input between the frame memory output and the DSP output by the selector 410 during the processing and after the processing, the progress of the processing can be confirmed by a monitor using an analog signal.

A more specific structure is shown in FIG. The frame memory uses two 4M bit VRAMs each having 512 columns × 512 rows × 16 bits. 501 and 502 are it. For all pixel data input from the A / D converter 503, odd lines are VRAM 501 and even lines are V
It is stored in the RAM 502. All pixel data is horizontal 640
It consists of dots and vertical 480 lines, and one pixel is 8
Is a bit. The pixel data is combined into two 16-bit data by the 8-16 converter 504,
Input to VRAM. That is, the memory controller 505, which has 320 words per line, advances the row address by two when data of 320 words in the horizontal direction is input. This gives 512 columns x 512 rows of 320 columns of DRAM cells x
All pixel data is stored every other row in the area of 480 rows. The remaining area is used as a microprocessor. The luminance signal data generated by the still image processing is stored in the VRAM 501 and the color signal data is generated in the VRAM 5
It is input to 02. The luminance signal data of the first line is stored in the area where all pixel data of the first line was stored, and the color signal data of the first line is stored in the area where all pixel data of the second line was stored. In this way, the VRAM 501 320
The luminance signal data is stored in the VRAM 50 in the area of columns × 480 rows.
The color signal data is generated in the area of 320 columns × 480 rows of 2. These data are converted to the 8-16 converter 504 again.
640 × 4 when converted into 8-bit data and output
80 luminance signal data and 640 × 480 color signal data. If the data amount of the color signal is halved, 51
2M bit VRAM2 with 2 columns × 512 rows × 8 bits
4Mbit VRAM to pursue high image quality
It is desirable to have two configurations. Further, when generating RGB signals instead of luminance signals and color signals, two 4M bits are indispensable. However, when generating RGB signals, normal images cannot be viewed even if the processing process is monitored with analog signals.

Next, the digital moving image mode of the additional function will be described with reference to FIG. The DSP 601 outputs moving image data composed of a luminance signal and two types of color difference signals. The moving image data is transferred to the frame memory 6 via the selector 602.
It is input to 03. The selector 602 has a function of selecting the output signal of the DSP and the frame memory 603 of the selector 410 in FIG. 4 and inputting it to the D / A converter.
The function of inputting the output of P to the frame memory 603 is added. The memory controller 604 controls the data input to the frame memory 603, spatially thins out the input moving image data in accordance with an instruction from the microprocessor 605, and outputs R of the frame memory 603.
Output from AM port, digital interface 6
Input to 06. The data of one screen of the moving image data (luminance and color signal of one field) is about 2 M bits (when the color signal data is calculated as half of the luminance signal data), and the data amount per second is 120 M bits. 4 Mbyte / sec SCSI2 for digital interface
Then, data of almost all fields can be transferred by thinning out to 1/4. However, the digital moving images used on a personal computer are often 160 × 120, 30 frames. At this time, the amount of data on one screen is 230K bits, which is 1
It is about 7 Mbits per second. If it is about this level, it can be sent even with a serial interface. By adopting the serial interface, the cable connecting to the personal computer can be simplified and the handling can be facilitated.

The frame memory is not limited to the dual port memory provided with the line buffer, and a normal 1-port DRAM may be used. However, in this case, input and output cannot be performed at the same time, so
It is not possible to confirm the still image processing by analog output.
However, as for the digital moving image mode, if two memories of 512 columns × 512 rows × 16 bits are used as in FIG. 5, one memory can store one field of moving image data. By performing input and output alternately with each memory, the same effect as VRAM can be achieved. Considering the cost, it is better to use DRAM.

[0025]

As described above, according to the present invention, the information amount of a still image is doubled by using the all-pixel image pickup device, and the still image processing is performed by the software processing, which greatly increases the cost. It is possible to obtain a high-quality still image without causing Further, since an analog signal with no time difference can be output in two fields, a still image with higher image quality than before can be obtained even in the conventional image capturing system using the capture board.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a digital camera of the present invention.

FIG. 2 is a schematic diagram showing a configuration of an all-pixel image sensor used in the same embodiment.

FIG. 3 is a block diagram of a frame memory when outputting an analog still image in the embodiment.

FIG. 4 is a block diagram showing a configuration of a frame memory in the embodiment.

FIG. 5 is a block diagram showing a detailed configuration of a frame memory in the embodiment.

FIG. 6 is a block diagram of a frame memory in a digital moving image mode in the embodiment.

FIG. 7 is a block diagram showing a configuration of a conventional digital camera.

FIG. 8 is a block diagram showing a configuration of a conventional digital camera.

[Explanation of symbols]

 101 All-Pixel Image Sensor 102 Image Sensor Driver 103 Synchronous Signal Generator 104 A / D Converter 105 Frame Memory 106 Memory Controller 107 Microprocessor 108 Adder 109 Digital Signal Processor 110 D / A Converter 111 Digital Interface

Claims (11)

[Claims] 1. An image sensor capable of outputting signals of all pixels in one field period, an A / D converter for converting an output signal of the image sensor into digital data, a memory for storing the digital data, and the digital data. A high-speed microprocessor that processes
An adder for adding two adjacent lines of the digital data and converting it into interlaced scan data, a digital signal processor for processing the interlaced scan data and converting it into moving image data, and a digital interface for outputting data from the memory to the outside. A digital camera comprising: a D / A converter for converting the output of the digital signal processor or the data stored in the memory into an analog signal; and a memory controller for controlling the memory. 2. The digital camera according to claim 1, wherein the image pickup device has two output terminals and outputs signals of two lines at the same time. 3. The memory provides a storage area for digital data, a work area used when a microprocessor performs processing, and stores generated still image data in an area including the digital data storage area. The digital camera according to claim 1, wherein the digital camera is a randomly accessible memory. 4. The memory separately stores an even line and an odd line of digital data, and outputs two adjacent lines by changing the combination between the first field and the second field,
The digital camera according to claim 1, wherein the digital camera is input to an adder. 5. The memory is a dual port memory having two ports, one port having a serial buffer so that the two ports can be independently accessed, and the other port being a randomly accessible memory. The digital camera according to claim 1. 6. The memory is composed of two memories capable of storing data for one screen, and while inputting data to one of the two memories, outputting the data from the other memory enables input and output. The digital camera according to claim 1, wherein the outputs are performed simultaneously. 7. The digital memory according to claim 1, wherein the memory is a randomly accessible memory that stores moving image data output from a digital signal processor, spatially thins out the moving image data, and outputs the thinned moving image data to a digital interface. camera. 8. The digital camera according to claim 1, wherein the digital interface is a serial interface that outputs data in 1-bit units in time series. 9. The memory controller, when receiving a data transfer command from the microprocessor, generates address and control signals so as to autonomously thin out and output the data in the memory as specified. The digital camera according to claim 1. 10. The digital camera according to claim 1, wherein the still image and moving image data includes a luminance signal and two types of color difference signals. 11. The digital camera according to claim 1, wherein the still image data is composed of three primary color signals of a red signal, a green signal and a blue signal.