JPH06326937A - Picture signal converter - Google Patents

Abstract

PURPOSE:To attain the display of high quality free from a sense of physical disorder by making a boundary quiet by outputting the D/A converted signal of interpolated picture data as a displaying picture signal when an address skip is generated. CONSTITUTION:The 1st decoder 4 decodes a master screen television(TV) signal and outputs the decoded signal to a signal processing circuit 27 and the 1st synchronizing separator circuit 6 as the 1st RGB signal 3. Thereby the circuit 6 outputs the 1st synchronizing signal 5 to a reading address generating counter 8. The counter 8 generates reading address data 7 and outputs the data to a picture memory 18 and a writing/reading address comparing circuit 20. The 2nd decoder 11 outputs a slave screen TV signal. The memory 18 outputs corresponding picture data to an information interpolating circuit 24 based upon writing address data 16. A signal synthesizing circuit 27 synthesizes interpolated picture data 23 outputted from the circuit 24 and the 1st RGB signal 3 to generate a synthetic RGB signal 26.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal conversion device, and more particularly to an image signal conversion device used for a display device capable of displaying two different images on the same screen.

Conventionally, a dual-screen television has been proposed which displays two screens on one display screen. With the recent trend toward higher quality and larger screens of images, there is a demand for higher quality of the displayed image even on the child screen displayed in the parent screen of a two-screen television.

[0003]

2. Description of the Related Art In a dual-screen television that displays two screens on the same display screen at the same time, the timing is based on a parent screen video signal corresponding to a screen (hereinafter referred to as a parent screen) displayed over the entire display screen. By displaying and displaying the screen displayed on a part of the parent screen (hereinafter referred to as the child screen) once in the image memory and outputting in synchronization with the display timing of the parent screen, two screens are simultaneously displayed. It is displaying.

[0004]

By the way, since the scanning cycle of the main screen and the scanning cycle of the sub-screen are generally different, for example, the read timing with respect to the image memory for storing the image data of the sub-screen is earlier than the write timing. In the case of (the reading scanning frequency is high), although the image data to be displayed this time should be read, the image data used for the previous display will be read.

More specifically, as shown in FIG. 6, the upper half of the display screen of the child screen is the display screen (new screen) corresponding to the image data to be displayed this time, but the lower half is the previous screen. The display screen becomes the same display screen (old screen) as the display, and the boundary slowly moves to the lower part of the screen at a speed according to the difference between the writing scanning frequency and the reading scanning frequency (Fig. 6 (a) →
(B) → (c)).

Similarly, when the writing timing of the image data of the small screen is earlier than the reading timing (= the writing scanning frequency is high), the boundary between the new screen and the old screen is the writing scanning frequency and the reading scanning. It moves slowly above the screen at a speed that depends on the frequency difference.

In particular, in the case of a moving image display in which the new screen and the old screen are clearly different from each other, there is a problem in that the display quality is deteriorated, which is very annoying. Therefore, an object of the present invention is to provide an image signal conversion device capable of performing high-quality display even when two screens having different scanning frequencies are displayed on the same screen such as a two-screen television. .

[0008]

In order to solve the above problems, the present invention provides a second image signal having a first scanning frequency.
In an image signal conversion device for outputting as a display image signal for displaying at a scanning frequency, the first
Write address data generating means for separating a sync signal and generating and outputting write address data; first converting means for performing analog / digital conversion of the image signal to output image data; and the image data Storage means for storing based on the write address data and outputting based on the read address data corresponding to the second scanning frequency, and a comparison signal are output by comparing the write address data and the read address data. If the magnitude relation between the write address data and the read address data is reversed based on the comparing means and the comparison signal, at least one line of image data and the magnitude relation immediately before the magnitude relation is reversed. Is generated, interpolation image data is generated and output based on the image data for at least one line immediately after When the relationship is not reversed, the interpolation means for directly outputting the image data output from the storage means based on the read address data, the interpolation image data output from the interpolation means, or the digital / analog of the image data Second conversion means for performing conversion and outputting as the display image signal.

[0009]

According to the present invention, the write address data generating means separates the first synchronizing signal from the image signal having the first scanning frequency, generates the write address data and outputs the write address data to the storing means, and the first conversion. The means performs analog / digital conversion of the image signal and outputs the image data to the storage means.

As a result, the storage means stores the image data based on the write address data and outputs the image data to the interpolation means based on the read address data corresponding to the second scanning frequency. On the other hand, the comparison means compares the write address data and the read address data to output a comparison signal corresponding to the magnitude relationship between them to the interpolation means.

As a result of these, the interpolating means, based on the comparison signal, when the magnitude relationship between the write address data and the read address data is reversed, at least one line of image data immediately before the magnitude relationship is reversed, and The interpolated image data is generated and output based on the image data for at least one line immediately after the magnitude relationship is inverted, and when the magnitude relationship is not inverted, the image data output from the storage means is determined based on the read address data. Output as is. The second conversion means performs digital / analog conversion of the interpolated image data or the image data output from the interpolation means, and outputs it as a display image signal.

Therefore, when the magnitude relationship between the write address data and the read address data is reversed, that is,
When the address is overtaken, a signal obtained by digital-to-analog converting the interpolated image data is output as a display image signal, so that the border is less noticeable and display can be performed without discomfort.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described with reference to FIGS. FIG. 1 shows a schematic block diagram of the image display device.

The image display device 1 is a main screen television (TV).
A first decoder 4 which decodes the signal 2 and outputs it as a first RGB signal 3; a first sync separation circuit 6 which separates a vertical sync signal from the main screen television signal 2 and outputs a first sync signal 5; A read address generation counter 8 that is reset by the synchronization signal 5 and that generates and outputs the read address data 7 and a second decoder 11 that decodes the sub-screen television signal 9 and outputs it as the second RGB signal 10.
A second sync separation circuit 13 that separates a vertical sync signal from the small screen television signal 9 and outputs a second sync signal 12, and an A / D that analog / digital converts the second RGB signal 10 and outputs it as image data 14. The D converter 15 and the write address data 16 which is reset by the second synchronization signal 12 and generates and outputs the write address data 16, and the image data 14 based on the write address data 16 are stored. An image memory 18 that outputs corresponding image data 14 based on the read address data 7.
And a write / read address comparison circuit 20 for comparing the write address data 16 and the read address data 7 and outputting a comparison signal 19, and the image memory 1 based on the comparison signal 19.
8. The address magnitude inversion detection circuit 22 which detects that the write address and the read address of FIG. 8 are inverted (passing) and outputs the inversion detection signal 21, and the inversion detection signal 21.
When the magnitude relationship between the write address and the read address is inverted based on the above, the interpolated image data 23 is output based on the image data of one line immediately before the inversion and the image data of one line immediately after the inversion. , If the magnitude relationship is not reversed, the image data 1 input from the image memory 18
4 is output as it is, and the interpolated image data 23 or image data 14 output from the information interpolation circuit 24 are digital-to-analog converted to display R.
A D / A converter 25 for outputting as a GB signal 24,
A signal combining circuit 27 that combines the first RGB signal 3 and the display RGB signal 24 and outputs the combined RGB signal 26,
A monitor 28 that performs various displays based on the composite RGB signal 24 is provided.

FIG. 2 shows a detailed block diagram of the write / read address comparison circuit 20 and the address magnitude inversion detection circuit 22. The write / read address comparison circuit 20 compares the write address data 7 with the read address data 16, and if the write address data 7 is equal to or more than the read address data 16 (write address data ≧ read address data). A comparator that outputs “0” as the result signal 19 and outputs “1” as the comparison result signal 19 when the write address data 7 is smaller than the read address data 16 (write address data <read address data). It is configured with 30.

The address magnitude inversion detection circuit 22 compares the comparison result signal 1 of the comparator 30 of the write / read address comparison circuit 20.
9 for latching and holding 9 based on a clock signal (not shown), and a second register 32 for latching and holding the data held in the first register 31 based on the same clock signal as the first register 31. , An exclusive OR circuit (EOR) 34 for taking an exclusive OR of the data held in the first register 31 and the data held in the second register 32 and outputting an exclusive OR signal 33, and an exclusive OR signal And a third register 35 that latches 33, holds 33, and outputs as the inversion detection signal 21.

FIG. 3 shows a detailed block diagram of the information interpolation circuit 24. The information interpolation circuit 24 outputs the selection control signal 40 based on the inversion detection signal 21.
1 and the line delay circuit 42 for delaying the image data 14 from the image memory 18 for one horizontal period, and the average value of the image data 14 ₋₁ output from the line delay circuit 42 and the input image data 14 An averaging circuit 43 that outputs the interpolated image data 23 and a selector 44 that selectively outputs one of the interpolated image data 23 and the image data 14 based on the selection control signal 40 are configured.

Next, the operation will be described with reference to FIGS. The first decoder 4 receives the input parent screen television signal 2
Signal decoding circuit 2 as a first RGB signal 3 by decoding
7 and the first sync separation circuit 6. As a result, the first sync separation circuit 6 separates the vertical sync signal from the parent screen television signal 2 and outputs the first sync signal 5 to the read address generation counter 8.

The read address generation counter 8 is
The count value is reset by the first synchronization signal 5,
Read address data 7 according to a clock signal (not shown)
Is generated and output to the image memory 18 and the write / read address comparison circuit 20.

In parallel with these operations, the second decoder 11
Decodes the sub-screen television signal 9 and outputs it as the second RGB signal 10 to the A / D converter 15 and the second sync separation circuit 13. As a result, the second sync separation circuit 13
Separates the vertical synchronizing signal from the small screen television signal 9 and outputs the second synchronizing signal 12 to the write address generation counter 17.

The A / D converter 15 has a second R
The GB signal 10 is analog-to-digital converted and output as image data 14 to the image memory 18, the write address generation counter 17 is reset by the second synchronization signal 12, and the write address data 16 is generated in response to a clock signal (not shown). Is generated and output to the image memory 18 and the write / read address comparison circuit 20.

As a result, the image memory 18 stores the image data 14 input from the A / D converter 15 based on the write address data 16 and the corresponding image data 14 based on the read address data 7. Output to the interpolation circuit 24.

The operations of the write / read address comparison circuit 20 and the address magnitude inversion detection circuit 22 will now be described with reference to FIG. The case where the scanning frequency corresponding to the reading operation is slightly higher than the scanning frequency corresponding to the writing operation will be described below.

At time t ₀ , the image memory 18 writes the image data 14 at the address 1 based on the write address data 16 = 1 (address) input by the write address generation counter 17. Further, the image memory 14 reads the image data 14 from address 1 based on the read address data 7 = 1 (address) input by the read address generation counter 8 and outputs it to the information interpolation circuit 24.

At this time, the write address data 16 and the read address data 7 are stored in the write / read address comparison circuit 20.
In this case, since the write address data 16 and the read address data 7 are the same, "0" is output from the comparator 30 as the comparison signal 19. Thereafter, similarly, “0” is output from the comparator 30 as the comparison signal 19 until time t ₁ .

At time t ₁ , write address data 1
6 = 8 (address), read address data 7 = 9 (address), and when address overtaking occurs, the comparator 3
The comparison signal 19 which is an output of 0 immediately becomes "1".

As a result, the data held in the first register 31 becomes "1". On the other hand, the second register 32 is the data held in the first register 31 of the previous time, and therefore remains “0”.

Therefore, the exclusive OR circuit 34 has the first
Data held in register 31 = "1" and second register 3
The exclusive OR of the retained data of 2 = “0” is calculated and the time t
The exclusive OR signal 33 in ₂ becomes "1" and the first
A period in which the data held in the register 31 and the data held in the second register 32 are inverted, that is, from time t ₂ to time t
It becomes "1" during the period of ₃ . This causes the third register to
Outputs "1" as the time t ₃ during the to time t ₄ inversion detection signal 21, and operating the information interpolation circuit 24.

When the inversion detection signal 21 which is the output of the address magnitude inversion detection circuit 22 becomes "1", the information interpolation circuit 24 starts the operation of the line counter 41, and the output of the averaging circuit 23 side during one horizontal period. The selection control signal 40 (= “1”) corresponding to the selection is output to the selector 44.

At this time, the image data 14 (= B _{1 to} B _n ) from the image memory 18 is input to the line delay circuit 42 and delayed by one horizontal period, and the image data 14 _-1 (= A ₁ to B _n ).
It is output as A _n ). As a result, in the averaging circuit 23, as shown in FIG. 5, the average of the image data 14 _-1 one horizontal period (line) before and the image data 14 currently input is calculated, and the interpolated image data 23 (= C ₁ ˜C _n ).

Therefore, the address magnitude inversion detection circuit 2
The information interpolation circuit 24 outputs the interpolated image data 23 to the D / A converter 25 during one horizontal period after the inversion detection signal 21 which is the output of 2 becomes "1".

As a result, the address magnitude inversion detection circuit 22
At the timing when the output of “1” becomes “1”, that is, at the timing when the boundary line on the child screen due to the difference in scanning frequency between the parent screen and the child screen occurs, the signal combining circuit 27 uses the interpolated image data 23. 1 RGB signal 3 combined and combined RG
Since the B signal 26 is generated and displayed on the monitor 28, the boundary is not noticed and high-quality image display can be performed.

In the above description, the scanning frequency corresponding to the reading operation is slightly higher than the scanning frequency corresponding to the writing operation, but the scanning frequency corresponding to the reading operation corresponds to the writing operation. Even when the scanning frequency is slightly lower than the scanning frequency, high-quality image display can be similarly performed.

In the above embodiment, the averaging is performed using the image data of the lines before and after the address overtaking, but it is also possible to use the image data of a plurality of lines. .

[0035]

According to the present invention, when the magnitude relationship between the write address data and the read address data is inverted based on the comparison signal, the interpolating means is for at least one line immediately before the magnitude relationship is inverted. Image data and the image data for at least one line immediately after the magnitude relationship is inverted, and the interpolated image data is generated and output. When the magnitude relationship is not inverted, the interpolation image data is output from the storage means based on the read address data. The output image data is output as it is, and the second conversion means performs digital / analog conversion of the interpolated image data or image data output from the interpolation means and outputs it as a display image signal. If the magnitude relationship with the data is reversed, that is, if an address overtaking occurs, the interpolated image data is Analog-converted signal is output as the display image signal, the boundary can perform high-quality display without discomfort become inconspicuous.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an image display device.

FIG. 2 is a block diagram showing a detailed configuration of a write / read address comparison circuit and an address magnitude inversion detection circuit.

FIG. 3 is a block diagram showing a detailed configuration of an information interpolation circuit.

FIG. 4 is a timing chart illustrating operations of a write / read address comparison circuit and an address magnitude inversion detection circuit.

FIG. 5 is a timing chart explaining the operation of the information interpolation circuit.

FIG. 6 is an explanatory diagram of a conventional problem.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Image display device 2 ... Main screen television signal 3 ... First RGB signal 4 ... First decoder 5 ... First synchronization signal 6 ... First synchronization separation circuit 7 ... Read address data 8 ... Read address generation counter 9 ... Sub screen TV Signal 10 ... Second RGB signal 11 ... Second decoder 12 ... Second synchronization signal 13 ... Second synchronization separation circuit 14 ... Image data 15 ... A / D converter 16 ... Write address data 17 ... Write address generation counter 18 ... Image Memory 19 ... Comparison signal 19 20 ... Write / read address comparison circuit 21 ... Inversion detection signal 22 ... Address size inversion detection circuit 23 ... Interpolation image data 24 ... Information interpolation circuit 25 ... D / A converter 26 ... Synthetic RGB signal 27 ... Signal Synthesis circuit 28 ... Monitor 30 ... Comparator 30 31 ... First register 32 ... Second register 33 ... Exclusive OR signal 3 ... exclusive OR circuit (EOR) 35 ... third register 40 ... selection control signal 41 ... line counter 42 ... line delay circuit 43 ... averaging circuit 44 ... selector

Claims (1)

[Claims] 1. An image signal having a first scanning frequency is output as a second image signal.
In an image signal conversion device for outputting as a display image signal for displaying at a scanning frequency, write address data generating means for separating a first synchronization signal from the image signal and generating and outputting write address data, First conversion means for performing analog / digital conversion of an image signal to output image data; and storing the image data based on the write address data, based on read address data corresponding to the second scanning frequency. Storage means for outputting; comparison means for outputting a comparison signal by comparing the write address data and the read address data; and a magnitude comparison between the write address data and the read address data based on the comparison signal. When the relationship is reversed, the image data for at least one line immediately before the magnitude relationship is reversed and Interpolated image data is generated and output based on the image data of at least one line immediately after the small relationship is reversed, and is output from the storage means based on the read address data when the large relationship is not reversed. An interpolating unit that outputs the image data as it is; and a second converting unit that performs digital / analog conversion of the interpolated image data or the image data output from the interpolating unit and outputs the image signal for display. An image signal conversion device characterized by the above.