JPH02186833A - Line memory - Google Patents

Abstract

PURPOSE:To enable readout to be started from an arbitrary address by setting a start address on a readout address generation circuit from the outside by a start address setting means. CONSTITUTION:The initial values A1-Am (m is positive integer) of readout addresses are supplied from the outside to the readout address generation circuit 5 consisting of a counter to which the initial value can be inputted, and also, the initial values A1-Am are supplied by supplying a load signal, the inverse of LD, and is set on the counter. Also, the readout address generated at the readout address generation circuit 5 is returned to '0' when an address progresses to the final address of a memory cell array 1, and hereafter, it is incremented again. Thus, since the start address can be set on the readout address generation circuit 5 from the outside by the start address setting means, the readout can be started from the arbitrary address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line memory suitable for use in scrambling video signals in pay broadcasting, for example.

[Prior Art] In recent years, with the development of digital signal processing technology, various types of memories have been developed for different purposes, such as dual-port memory 18 frame memories for image processing.

Line memory is one such memory, and this line memory is a memory for storing data for one horizontal scan of a video signal.

FIG. 3 shows the configuration of a conventional line memory. In the figure, l is a memory cell array that can store data for one horizontal scanning interval of a video signal, and 2 is a memory cell array l that stores data Di of n pitch I (n is a positive integer Fi).
A manual buffer for writing 1 to D 1, 3 a write address generation circuit configured as a counter and for generating a write address, 4 a memory cell array 1 to n
The output buffer 7.5 for reading out the hit data Dol-Don is a read address generation circuit composed of a counter and for generating a read address.

In the above configuration, writing to the memory cell array 1 is performed as follows.

That is, the write reset signal n (shown in FIG. 4B) is supplied to the write address generation circuit 3, and the counter therein is reset to "o", and at the same time, the write clock ', V CI ((
4A) is supplied, and the write address is sequentially incremented (as shown in FIG. 4C).

In addition, the large power buffer 2 also has a write enable signal v
rF- is supplied, and the write clock ~VCK
are supplied, and n-bit data Dil to D11 are sequentially supplied to the memory cell array 1 via the input huff 72.

As a result, 11 bits of data Dil-Din are sequentially written into the memory cell array 1 from address "O".

On the other hand, reading from the memory cell array 1 is performed once as follows.

That is, the read reset signal rTT<<shown in FIG.
(shown in Figure 5A) is supplied and the read address is 1.
It is incremented by the 111th order (as shown in FIG. 5C).

The output buffer 74 also has a read enable signal ■
At the same time, the read clock RCK is supplied, and n-bit data Do from the memory cell array 1 is supplied.
t to Don are sequentially outputted via the output buffer 74.

As a result, address "0" is output from memory cell array l.
Then, n pieces of data Dot to Don are sequentially read out.

Note that writing and reading are performed in a non-same manner.

Such a line memory is used, for example, as a line delay memory in a television receiver or video tape recorder system, a time base conversion memory, or a memory for aligning multiple input signals.

[Problems to be Solved by the Invention] By the way, in the line memory shown in the example in FIG. 3, reading cannot be started from an address in the middle of a memo.
It was not possible to cut out any part of the data for one horizontal scanning interval of the video signal and swap the left and right sides.

Therefore, it is an object of the present invention to provide a line memory that can start reading from any address.

[Means for Solving the Problems] The present invention includes a write address generation circuit, a read address generation circuit, and a memory cell array capable of storing data for one horizontal scanning period of Is No. 13. It is a line memory, and in the read address generation circuit,
A start address setting means is provided which can set a start address from outside.

[Function] In the above configuration, the read address generation circuit 5 has the following functions:
Since the start address can be set externally by the start address setting means, reading can be started from any address.

[Example] See Figure 1 below. An embodiment of the present invention will be described with reference to the drawings. In FIG. 1, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In this example, the read address generation circuit 5
It is constructed with a counter that can be manually operated. Initial values A1 to Am (m is a positive integer) of the read address are supplied to this read address generation port ¥85 from the outside, and this initial value Al-Am is low 1''.
When No. 18 FF is supplied, it is manually set on the counter.

The read address generated at the read address generation port Y85 returns to "0" when it reaches the final address of the memory cell array l, and is incremented again thereafter.

The rest is constructed in the same way as in Figure 3 (chestnut).

In the following configuration, writing to the memory cell array 1 is performed in one step as follows, similar to the example in FIG.

That is, one write reset signal FyTI (shown in FIG. 4B) is supplied to the write address generation circuit 3, and the counter therein is reset to "0", and the write clock WCI (shown in FIG. 4B) is supplied to the write address generation circuit 3. (
4A) is supplied, and the write address is sequentially incremented (as shown in FIG. 4C).

In addition, a write enable signal 7 is sent to the human buffer 72.
1 is supplied, a write clock WCK is also supplied, and n-bit data Dil-D11 is sequentially supplied to the memory cell array 1 through the manual buffer 2.

As a result, data Dil-Din of n bits are sequentially written into the memory cell array l from address "0".

On the other hand, reading from the memory cell array 1 is performed as follows: by supplying the load 1 word "1" (shown in FIG. 2B) to the read address generation circuit 5, the initial value A1 ~Am (shown in Figure 2C) is manually set in the counter.As a result, the reading start address is set to "x" (0≦X≦) specified by the initial values A1 to Am.
2'''-1).Then, the read 0 clock RCK (shown in FIG. 2A) is supplied to the read address generation circuit 5, and the read address is sequentially incremented (shown in FIG. 2). When the write address reaches the final address 2-1 of the memory cell array I, it returns to "0" and is incremented again.

The output buffer 4 also receives a read enable signal W.
(2) is supplied, the read clock RCK is supplied, and the n-bit data Do from the memory cell array 1 is supplied.
t to Don are sequentially outputted via the output buffer 4.

As a result, from the memory cell array 1, the address r
n bits of data Dol~Don from J is 111
Sixth reading is performed.

As described above, according to this example, n-bit data Dil to Din are sequentially written from the address "0" to the memory cell array 1, and n-bit data Dol=DO from the address rXJ is written from the memory cell array 1.
Since n are read out sequentially, by changing the initial value Al-Am that specifies the address "x", one of the video signals can be read out sequentially.
74 data can be obtained by cutting the data between horizontal scans at an arbitrary part and swapping the left and right sides.

It is clear that if X=O is set, the same operation as the example in FIG. 3 will be performed.

[Effects of the Invention] As explained above, according to the present invention, since the start address can be externally set in the read address generation circuit by the start address setting means, reading can be started from any 7 traces. . Therefore, by changing the start address, data for one horizontal scanning period of the video RIrs can be cut at any part and left and right swapped to obtain data, which is used, for example, to scramble video signals in paid broadcasting. This makes it suitable.

Figure 2 is a diagram for explanation, Figure 3 is a configuration diagram of a conventional example,
FIG. 4 and FIG. 5 are diagrams for explaining the same.

・Memory cell array ◆Manpower buffer ・Write address generation circuit One output huff 7 ・Read address generation circuit

Claims (1)

[Claims] (1) In a line memory comprising a write address generation circuit, a read address generation circuit, and a memory cell array capable of storing data for one horizontal scanning period of a video signal, an external signal is input to the read address generation circuit. A line memory characterized in that a start address setting means for setting an address is provided.