JPS63136394A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain an image memory of optional size without providing external mount components by serially inputting/outputting storage data of a memory cell coupled with a selected word line and data line according to a clock signal supplied externally. CONSTITUTION:The initial value of a row address counter RAC and a pointer PNT are designated via external terminals Ao-Ai at the time of start. The pointer PNT shifts the selection signal written in the bit corresponding to the head column address stored in a column address register CAR according to the serial clock signal SC fed externally. When the word line of the final address is selected by the row address counter RAC, the final row address detection signal raf is formed and the row address counter RAC is initialized again. Thus, the word and data lines starting selection are designated as the head row and column address in the dynamic RAM and the image memory of optional size is constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and relates to a dynamic RAM used as an image memory, for example. It is something.

[Conventional technology]

Regarding dynamic RAM, which has the function of serially inputting and outputting stored data and is used as an image memory, for example, February 11, 1985.

r Nikkei Electronics 12 published by Nikkei McGraw-Hill
It is described on pages 19 to 229.

In the dynamic RAM described above, each bit is provided corresponding to the data line of the memory array, and by shifting a selection signal of logic "1" according to a serial clock signal supplied from the outside, data can be stored. A shift register is provided for sequentially specifying lines. Further, a row address generation amplifier down counter circuit is provided which sequentially specifies word lines of the memory array by stepping in accordance with an increment signal or a decrement signal supplied from the outside. Using these shift registers and up/down counter circuits for generating row addresses, the dynamic RAM serially inputs and outputs stored data to the memory area within the range to which the serial clock signal and increment signal (or decrement signal) are supplied. It has the function of

[Problem that the invention seeks to solve]

However, in order to configure a field memory of any size using the dynamic RAM described above,
It is necessary to input the serial clock signal and increment signal (or decrement signal) by the number of pulses according to their size. It is necessary to provide a counter circuit with a large number of bits, an address decoder, etc. outside the dynamic RAM. For this reason, external attachment increases the number of parts, leading to an increase in cost (and the circuit configuration becoming more complex, increasing the design burden).

An object of the present invention is to provide a semiconductor memory device having new functions.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows. That is,
An address register for holding a first address signal and/or last address signal supplied from the outside in a semiconductor memory device, and an address generator for sequentially specifying word lines and/or data within a specified address range. A circuit is provided.

〔effect〕

According to the above-mentioned means, storage data can be serially input/output to a memory area within a pre-specified address range by simply supplying a serial clock signal from the outside, so there is no need to install any external parts. Image memory of any size can be realized.

〔Example〕

Figure 1 shows a dynamic RA to which this invention is applied.
A block diagram of one embodiment of M is shown. Each circuit block in the figure is formed on a single semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

The dynamic RAM of this embodiment is a memory array M
-ARY includes a row address counter RAC for sequentially selecting and specifying word lines, and a pointer PNT for sequentially selecting and specifying a plurality of memory cells coupled to the selected word line.

The initial values of the row address counter RAC and the pointer PNT, that is, the start addresses of the word line and data line to be selected, are input to the external terminal AO- when the dynamic RAM is activated.
It can be specified via Ai. These first addresses are held in a row address register RAR and a column address register CAR, respectively. pointer PN
T is a logic value written to the bit corresponding to the first column address held in the column address register CAR.
1" selection signal is shifted in accordance with the serial clock signal SC supplied from the outside. When this selection signal reaches the final bit of the pointer PNT, the final column address detection signal caf is generated and the pointer PNT is reinitialized. In addition, this final column address detection signal ca
The row address counter RAC is incremented by f, and the next word line is automatically selected. When the word line at the final address is selected by the row address counter RAC, the final row address detection signal raf is generated, and at the time when the above-mentioned final column address detection signal car is generated on the word line at the final address, the row address is Counter RAC is reinitialized. As a result, the dynamic RAM of this embodiment can specify the word line and data line at which selection starts as the first row address and the first column address, and can configure an image memory of any size.

In FIG. 1, the memory array M-ARY has m+1 word lines W Ow W arranged in the vertical direction of the figure.
m, n+1 sets of complementary data lines DO, DO to Dn-Dn arranged in the horizontal direction of the figure, and (m+1) x (n+1) arranged at the intersections of these word lines and complementary data lines.
) memory cells.

Word lines WO to Wm are row address decoders RDCR
One word line is selected and specified by the row address counter RAC. That is,
The row address decoder RDCR receives a complementary internal address signal axQ- supplied from the row address counter RAC.
waxi (here, for example, the non-inverted internal address signal ax
Q and the inverted internal address signal aXO are collectively expressed as a complementary internal address signal aXO (the same applies hereinafter), and one word line is selected and set to a high-level selected state. The word line selection operation by row address decoder RDCR is performed according to word line selection timing signal φX supplied from timing control circuit TC.

The row address counter RAC is a timing control circuit T.
The timing control circuit T
It is stepped in accordance with a timing signal φrc supplied from C. The timing signal φrc is set to a high level when the pointer PNT selects the data line of the final column address and the final column address detection signal caf becomes high level. In addition, the timing signal φcs is set to a high level when the dynamic RAM is activated, or when the row address counter RAC specifies the word line of the final row address, the output signal of the final row address detection circuit RAD, that is, the final row address detection signal rar. When the final column address detection signal caf becomes high level at the same time, it becomes high level.

The output signal of the row address counter RAC is supplied to the row address decoder RDCR and the final row address detection circuit RAD as the complementary internal address signal xO-xi. First row address signals AXO to AXi supplied
capture and retain. Although not particularly limited, in the dynamic RAM of this embodiment, the first row address signals AXO to AXi and the first column address signal AY specify the address of the word line and data line to start selection.
A so-called address multiplex method is adopted in which O to AYi are time-divided and supplied via the same external terminals AO to At when the dynamic RAM is activated. That is, the first row address signal AXO=AXi is activated in synchronization with the fall of the row address strobe signal RAS supplied as a control signal from the outside, and the first column address signal AYO~ is activated in synchronization with the fall of the column address strobe signal CAS. AYi is supplied to external terminals AO to At, respectively.

Therefore, the row address register RAR receives the row address strobe signal R in the timing control circuit TC.
According to the timing signal φar generated by detecting the falling edge of AS, the first row address signals AXO to AX
Take in i.

The final row address detection circuit RAD receives a complementary internal address signal axQ output from the row address counter RAC.
~Sat xi is monitored to form the final row address detection signal raf. That is, the final row address detection circuit RAD
sets the final row address detection signal raf to high level when the word line Wm of the final address is specified by the row address counter RAC. This final row address detection signal rat is supplied to the timing control circuit TC.

On the other hand, complementary data lines DO and D of memory array M-ARY
On the other hand, O~Dn-Dn is the sense amplifier S
They are respectively coupled to input/output nodes of corresponding unit circuits of A. Although not particularly limited, each unit circuit of the sense amplifier SA has a basic configuration of a latch consisting of two cross-connected CMOS inverter circuits. These sense amplifier SA unit circuits are put into an operating state by the timing signal φpa supplied from the timing control circuit TC, amplify the minute read signal of the memory cell output to the corresponding complementary data line, and read the signal of the complementary data line. Expand the level to a binary level of high level/low level.

Complementary data lines DO/DO~D of memory array M-ARY
On the other hand, n-Dn is coupled to the input/output node of the corresponding unit circuit of the data register DR. The unit circuits of these data registers DR include flip-flops consisting of two cross-connected CMOS inverter circuits, and non-inverted signal lines and inverted signal lines of complementary data lines corresponding to the input/output nodes of these flip-flops. A pair of MO5FET switches for data transfer are provided between the lines. Switch M for these data transfers
The O3FET pair is simultaneously turned on by the high level of the data transfer timing signal φdt supplied from the timing control circuit TC.

The input/output nodes of each unit circuit of the data register DR are further connected to the corresponding switch MOS of the data selector DSL.
FET pairs. data selector DS
L selectively connects each bit of the data register DR to the complementary common data line CD-CD. Data selector D
The gates of the switch MOS FETs of each pair of SL are connected in common, and a data register selection signal is supplied from the pointer PNT.

The pointer PNT is composed of an n+1 bit shift register, and performs a shift operation of the selection signal according to the shift clock timing signal φC supplied from the timing control circuit TC. Each bit of the pointer PNT corresponds to a column address decoder CDCH. output terminal.

The column address decoder CDCR receives a data line selection timing signal φy supplied from the timing control circuit TC.
The column address register CA
Complementary internal address signal supplied from R
i is decoded and the first column address signal AYO-AY
A selection signal of logic "1" is written in the bit of pointer PNT corresponding to i. This selection signal is shifted within pointer PNT according to timing signal φC supplied from timing control circuit TC.

By shifting the selection signal at the pointer PNT, a high-level data register selection signal is sequentially supplied to the data selector DSL, and the data register DR
Each bit is connected to complementary common data line CD-8 one after another. As a result, in the serial write operation mode of the dynamic RAM, the complementary common data line CD-
The write data input serially via the CD is
Starting from the bit designated by the first column address signals AYO to AYt, the bits are sequentially input to the data register DR. The write data held in the data register DR is generated by a timing signal φdt generated for each word line.
Accordingly, the signal is input in parallel to a plurality of memory cells coupled to the selected word line. In addition, in the serial read operation mode of the dynamic RAM, read data read from a plurality of memory cells coupled to a selected word line is inputted in parallel to the data register DR according to the timing signal φdt, and the read data is inputted in parallel to the data register DR according to the timing signal φC. Serially complementary common data line CD
- Output to CD.

The input/output terminals of the data input/output circuit I10 are coupled to complementary common data lines CD-CD to which the unit circuits of the data register DR are sequentially and selectively connected. The data input/output circuit I10 includes a main amplifier (not shown), a data output buffer that receives an output signal from the main amplifier, and a data buffer sofa. The read signal transmitted via data line CD-CD is further amplified. In the serial read operation mode of this dynamic RAM, the data output buffer
It is brought into operation by the high level of the timing signal φr supplied from the timing control circuit TC, and the read data obtained as the output signal of the main amplifier is serially outputted from the output terminal Dout to an external device. Dynamic type R in which the timing signal φr is set to low level
In the AM non-selection state and write operation mode, the output of the data output buffer is in a high impedance state. On the other hand, the data input/output circuit I10's data input/output circuit I10 is put into an operating state by the high level of the timing signal φW supplied from the timing control circuit TC in the serial write operation mode of the dynamic RAM, and is externally connected via the input terminal Din. The write data serially supplied from the device is used as a complementary write signal,
It is transmitted to complementary common data lines CD-CD. In the non-selected state of the dynamic RAM and in the read operation mode in which the timing signal φW is at a low level, the output of the data cover sofa is in a high impedance state.

The timing control circuit TC receives a row address strobe signal RAs, a column address strobe signal τ]T, a write enable signal W1, a serial clock signal SC, and a pointer P, which are supplied as control signals from an external device.
The various timing signals described above are formed using the final column address detection signal caf sent from the NT and the final row address detection signal raf sent from the final row address detection circuit RAD, and are supplied to each circuit.

FIG. 2 shows a timing diagram of an embodiment of the serial read operation mode of the dynamic RAM of this embodiment. An overview of the serial read operation mode of the dynamic RAM of this embodiment will be explained with reference to the same figure.

In FIG. 2, the dynamic RAM is activated by changing the row address strobe signal RAS from high level to low level.

Prior to the fall of the row address strobe signal RAS, the write enable signal layer 1 is set to a high level. In addition, external terminals AO to At are provided with a first row address signal AX for specifying the word line to be selected first.
O=AXi is supplied. In this embodiment, the first row address is "xlo".

In the dynamic RAM, the timing signal φcs as well as the timing signal φar are kept at a high level for a predetermined period. Due to the high level of the timing signal φar, the first row address signals AXO to AXI are taken into the row address register RAR and held. Further, due to the high level of the timing signal φcs, the first row address signal taken into the row address register RAR is further taken into the row address counter RAC. As a result, the row address counter RAC is initialized to the first row address "xl".

A little later than the timing signal φar, the word line selection timing signal φX is set to high level, and the word line selection operation by the row address decoder RDCH is started.

At the time when the word line selection operation is completed, the timing signal φpa is set to high level, and the sense amplifier SA is activated. As a result, the minute read signal output from the n+1 memory cells coupled to the selected word line to the corresponding complementary data line is amplified, and the high level/
It is said to be a low level 200 million read signal. At the point in time when a binary read signal is established on the complementary data line, the timing signal φdt is set to a high level. As a result, the read signals of each complementary data line are input to the corresponding bits of the data register DR all at once and held.

Next, column address strobe signal CAS is changed from high level to low level. Prior to the fall of column address strobe signal CAS, external terminals AO to Ai are supplied with first column address signal A for specifying the complementary data line to be selected first by pointer PNT.
YO to AYi are supplied. In this embodiment, the first column address is 1y11.

In a dynamic RAM, the timing signal φa is triggered by the fall of the column address strobe signal CAS.
c is set to high level, and the first column address signal AYO
~AYi is taken into column address register CAH. Also, a little later than the timing signal φac, the data line selection timing signal φy is set to high level, and the column address decoder CDCH outputs a logic “1” selection signal to the bit corresponding to the first column address signal AYO to AYi of the pointer PNT. As a result, first, the bit corresponding to the first column address "yl" of the data register DR is connected to the complementary common data 1JlcD-C.

When the selection operation of the word line and complementary data line (unit circuit of the data register DR) is completed and the first read data is output from the main amplifier of the input/output circuit I10, the timing signal φr is set to high level. This results in
The data output terminal Dout has an address “xl・y1′”
The read data of the memory cell corresponding to " is output.

When the above read operation in the dynamic RAM is completed, the serial clock signal SC is supplied, and the row address strobe signal RAS and column address strobe signal CAS are set to high level. Thereby, the dynamic RAM can perform a refreshing operation by a refresh circuit (not shown) in parallel with the serial output operation of stored data in synchronization with the serial clock signal SC.

The selection signal of logic "1" written in the bit corresponding to the first column address "y1" of the pointer PNT is shifted in synchronization with the falling edge of the timing signal φC generated according to the serial clock signal SC, and is shifted to the data register DR. unit circuits are sequentially selected. Further, the read data held in the unit circuits of these data registers DR is sequentially sent to the data input/output circuit I10 via the complementary common data line CD-CD, and further data is output in synchronization with the rising edge of the timing signal φC. It is sent to the outside from the terminal Dout.

When the pointer PNT selects and specifies the bit corresponding to the final column address "x1·yn" of the first row address of the data register DR, the final column address detection signal caf is set to high level. As a result, the data line selection timing signal φy is set to high level, and the pointer P
A selection signal of logic "1" is written again to the bit corresponding to the first column address "yl" of NT, and the pointer P
The NT is initialized, and the timing signal φr
c is set to high level, and row address counter RAC is incremented. Further, the word line selection timing signal φX is set to high level a little later than the timing signal φrc,
Next, the timing signal φpa and the timing signal φd
t is set to high level.

For these reasons, the word line corresponding to the row address "X+1" next to the first row address is set to the selected state, and the stored data of the n+1 (lI) memory cell coupled to this word line is stored in the same way as above. , are input in parallel to corresponding bits of data register DR and held.

Thereafter, similar serial output operations are repeated for each word line in synchronization with the serial clock signal SC, and each time the bit corresponding to the final column address of the data register DR is selected, the final column address detection signal caf goes high. level, and the row address counter RAC is incremented. When the row address counter RAC specifies the word line of the final row address>(m, the output signal of the final row address output circuit RAD, that is, the final row address detection signal raf becomes high level. This final row address detection signal raf During the period considered to be at a high level,
When the final column address detection signal Caf becomes high level, that is, the final address of the memory array M-ARY"
When the storage data of the memory cell corresponding to "x m -y ri" is output, the timing signal φcs is set to high level together with the word line selection timing signal φX, the data line selection timing signal φy, etc. As a result, the pointer PNT At the same time, the first row address "xl" held in the row address register RAR is taken into the row address counter RAC again by the high level of the timing signal ψCS, and the row address counter RAC is initialized. Thereafter, as the serial clock signal SC continues to be supplied, the data stored in the memory cells within the range corresponding to row addresses "xl" to "xm" and column addresses 1y1" to 1yn" are repeatedly output serially. Terminal Dou
Output from L.

As described above, the dynamic RAM of this embodiment includes a row address counter RAC for sequentially selecting a word line, and a complementary common data line C- A pointer PNT is provided for connecting to the D-CD. Furthermore, the addresses of the word lines and data lines that are first selected by the row address counter RAC and the pointer PNT can be specified via the external terminals AO to Al when the dynamic RAM is activated. These first row addresses and first column addresses are stored in the row address register R.
It is held in AR and column address register CAR, and initialization of pointer PNT or row address counter RAC is repeated every time the final address is detected. Therefore, the dynamic RAM of this embodiment can serially input and output data stored in memory cells at addresses within a specified range as long as the serial clock signal SC is supplied.

FIG. 3 shows a conceptual diagram for explaining the serial input/output operation of the dynamic RAM of this embodiment.

In FIG. 3, the rows of the memory array of the dynamic RAM, that is, the word lines WO to
Wm corresponds to the Y-axis addresses yQ -, -y n, and the columns of the memory array, that is, the complementary data lines Do-Do to Dn.
-Dn is supported. By specifying the first row address "x1" and the first column address "yl" for the serial input/output operation of the dynamic RAM, it is possible to serially input/output only the data stored in a partial memory area. .That is, dynamic type R
The pointer PNT of AM is the first column address “ylo
The data lines from to the final column address "yn" are repeatedly selected, and the row address counter RAC repeatedly selects the word lines from the first row address "x1" to the final row address "xm". Therefore, storage data can be serially input/output to and from memory cells in the shaded range in FIG. 3 among all memory areas of the dynamic RAM. Needless to say, by matching the specified range of this memory area with the number of scanning lines and pixels of a CRT for image display, it is possible to realize an image memory of any size that is compatible with the image system.

As shown in the above embodiment, when the present invention is applied to a semiconductor memory device such as a dynamic RAM used as an image memory, the following effects can be obtained. That is, (1) an address register to hold the start address and/or the end address at which the serial input/output operation should be started, and a word line and/or data line sequentially within the range specified by the start address and end address. By providing an address selection circuit for designation, it is possible to serially input and output data stored in any memory area.

(2) The +11 term above provides the effect that an image memory whose size corresponds to the number of scanning lines and the number of pixels of an image display CRT can be constructed without any external parts.

(3) According to the above (11) and (2), it is possible to realize a low-cost image memory that is easy to control.

The invention made by the present inventor has been specifically explained above based on examples, but it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without getting across the gist of the invention. Nor. For example, in the embodiment shown in FIG. 1, the final address is fixed in accordance with the final word line Wm and the final complementary data line Dn-Dn of the memory array M-ARY of the dynamic RAM, but the final row address and the final By providing an address register for holding column addresses and an address comparison circuit, it may be possible to arbitrarily set the start address and the end address.

Further, contrary to this embodiment, the start address may be fixed according to the start word line WO and the start complementary data line DO, and only the end address can be arbitrarily set. In the embodiment, the column address system selection circuit is configured with a pointer PNT consisting of a shift register with n+1 pins, but it may also be configured with an address counter with n+1 pins as in the row address system. The column address detection signal car and the final row address detection signal raf may be output as synchronization signals to an external CRT.Furthermore,
In parallel with the serial input/output operation of stored data described in this embodiment, various combinations of block configurations and control signals can be used, such as providing a function to randomly input/output stored data in units of one bit or several bits. This is an embodiment of the present invention.

In the above explanation, we have mainly explained the case where the invention made by the present inventor is applied to a dynamic RAM for image memory, which is the field of application that formed the background of the invention.
The present invention is not limited to this, and can also be applied to semiconductor storage devices for various purposes, such as similar image memories configured with static RAM, buffer memories for image communications, and image storage memories for VTRs. The present invention can be widely applied to semiconductor memory devices used for serially inputting and outputting image data of different sizes, and semiconductor devices incorporating such semiconductor memory devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, an address register for holding the start address and/or the end address at which the serial input/output operation should be started, and a register for sequentially specifying the word line and/or data line within the range specified by the start address and the end address. By providing this address selection circuit, it is possible to realize a low-cost image memory that can be of any size depending on the number of scanning lines and the number of pixels of an m-image display CRT.

[Brief explanation of the drawing]

Figure 1 shows a dynamic RAM to which this invention is applied.
FIG. 2 is a timing diagram showing an example of serial read operation of the dynamic RAM shown in FIG. 1; FIG. 3 is a block diagram showing an example of serial read operation of the dynamic RAM shown in FIG. FIG. 3 is a conceptual diagram for explaining the operation. M-ARY 1...Memory array, SA...Sense amplifier, RDCR...Row address decoder, RAC
...Row address counter, RAD...Final row address detection circuit, RAR...Row address register,
DR...data register, DSL...data selector, PNT...pointer, CDCR...column address decoder, CAR...column address register,
110...Data input/output circuit, ]゛C...Timing control circuit. Figure 1 Figure 2

Claims (1)

[Claims] 1. A memory array consisting of a plurality of word lines, a plurality of data lines, and a plurality of memory cells arranged in a grid at the intersections of these word lines and data lines; a selection circuit that sequentially selects word lines and/or data lines within a predetermined range from a specified address and/or to an externally specified address, and is coupled to the selected word line and data line. 1. A semiconductor memory device characterized in that data stored in a memory cell is serially input/output according to a clock signal supplied from the outside. 2. The selection circuit includes an address register that holds a start address signal supplied from the outside, a final address detection circuit that identifies that the word line or data line at the final address of the memory array has been selected, and a final address detection circuit that detects the selected address. 2. The semiconductor memory according to claim 1, further comprising an address generation circuit that sequentially specifies word lines or data lines in a predetermined range of the memory array according to the output signal of the register and the final address detection circuit. Device.