JP4088649B2 - Display system - Google Patents

Description

  The present invention relates to a liquid crystal display control device, a computer system, and a display device that achieve a reduction in the capacity of a storage element required when a video signal from a personal computer or the like is enlarged and displayed on a liquid crystal display device.

  Conventionally, as a liquid crystal display control device for enlarging and displaying video information from a personal computer or the like, a video signal from a personal computer or the like is temporarily stored in a frame memory as disclosed in, for example, Japanese Patent Laid-Open No. 4-12393. A technique for performing readout at a timing suitable for liquid crystal display is known. Details of this technique will be described below with reference to FIGS.

  FIG. 12 is a block diagram of a control circuit inside the liquid crystal display device disclosed in Japanese Patent Laid-Open No. 4-12393. In FIG. 12, the reference numeral “1101” is a video signal from a personal computer or the like. The reference numeral “1102” is a synchronization signal. Similarly, reference numeral “1103” is a horizontal / vertical timing and basic clock generation circuit, reference numeral “1104” is an input signal automatic discrimination circuit, reference numeral “1105” is a frame memory data and write control signal generation circuit, and reference numeral “1106” is a field. A frame memory circuit composed of a memory and a line buffer, symbol “1107” is a frame memory read control and display data generation circuit, symbol “1108” is an enlarged display control circuit, symbol “1109” is a liquid crystal display circuit, and symbol “1110” "" Refers to the liquid crystal display unit.

  FIG. 13 is a block diagram showing details of the frame memory circuit 1106 of FIG. In FIG. 13, reference numeral “1201” denotes a field memory. Similarly, reference numeral “1202” indicates a line buffer, and reference numeral “1203” indicates a read data selection circuit.

  12 and 13, a horizontal / vertical timing and basic clock generation circuit 1103 generates frame memory data and a frame memory based on horizontal and vertical synchronization signals 1102 for driving a CRT display device input from a personal computer or the like. A horizontal timing signal, a vertical timing signal, and a basic clock signal CK1 for controlling the operation of the writing circuit 1105 are created.

  The frame memory data creation and frame memory write circuit 1105 generates a control signal WRCT (write clock signal SWCK, write enable signal WE, reset write signal RSTW) based on the basic clock signal CK1, and outputs this to the field memory 1201. Output (see FIG. 13). Further, memory data Din corresponding to one screen created from a video signal 1101 input from a personal computer or the like is sequentially written in the field memory 1201 and temporarily stored.

  On the other hand, the frame memory read and display data creation circuit 1107 generates the control signal RDCT based on the liquid crystal display driving clock signal CK2 generated by the liquid crystal display circuit 1109 and the control signal generated by the enlarged display control circuit 1108. The control signal RDCT is output to the frame memory circuit 1106. The liquid crystal display driving clock signal CK2 has a longer period than the basic clock signal CK1.

  The control signal RDCT includes a read clock signal SRCK, a read reset signal RSTR, a write clock signal WCK, a reset write signal RSTWN, a read clock signal RCK, a reset read signal RSTRN, and a data selection signal SELDT. Among these, the read clock signal SRCK and the read reset signal RSTR are supplied to the field memory 1201. The write clock signal WCK, the reset write signal RSTWN, the read clock signal RCK, and the reset read signal RSTRN are supplied to the line buffer 1202 of the frame memory circuit 1106. The data data selection signal SELDT is supplied to the read data selection circuit 1203 of the frame memory 1106.

  The read data select circuit 1203 selects either the output data D1 from the field memory 1201 or the output data D2 from the line buffer 1202 and outputs it as frame memory read data Dout.

  The frame memory reading and display data creation circuit 1107 described above creates serial liquid crystal display data suitable for the liquid crystal display unit 1110 based on the data Dout.

  The liquid crystal display circuit 1109 generates a signal suitable for the format of the liquid crystal display unit 1110 of the liquid crystal display drive signal, the data shift clock signal, and the alternating signal based on the clock signal CK2 for driving the liquid crystal display.

  The liquid crystal display unit 1110 displays a predetermined image based on the liquid crystal display data output from the frame memory reading and display data creation circuit 1107 and the signal output from the liquid crystal display circuit 1109.

  Incidentally, the enlarged display control circuit 1108 determines whether or not an instruction to enlarge a part of the screen has been given by the operator. If it is determined that an instruction for enlargement display has been given, the frame memory data creation / frame memory write circuit 1105 and the frame memory read / display data creation circuit 1107 are controlled in accordance with the instructed enlargement magnification and information about the area.

  Also, the input signal automatic determination circuit 1104 determines an input video signal that differs depending on, for example, the type of personal computer based on the synchronization signal 1102. The horizontal / vertical timing and basic clock generation circuit 1103 is controlled according to the determination result.

JP-A-4-12393

  In the prior art, enlargement processing is possible. However, since the input / output of the video signal is controlled completely asynchronously using the field memory, the field memory needs to have a memory capacity sufficient to store video information for one screen. The memory capacity capable of storing video information for one screen is not small for the current technical level of memory.

  Further, in the conventional technology, all video signals are temporarily stored in the frame memory circuit 1106 so that the read timing to the liquid crystal display unit is always constant. Therefore, when a high-resolution video signal is input, a field memory that can be accessed at high speed regardless of whether or not enlargement processing is performed is required. Memory that can be accessed at high speed is expensive, and the use of such memory has been a factor that hinders cost reduction of display devices.

  An object of the present invention is to provide a liquid crystal display control device capable of enlarging processing while suppressing an increase in memory capacity.

  Another object of the present invention is to provide a liquid crystal display control apparatus that can handle a high-resolution video signal while using a memory having a low access speed (that is, an inexpensive memory).

  Still another object of the present invention is to provide a liquid crystal display control device capable of arbitrarily selecting image quality and cost according to a user's request.

  The present invention has been made to achieve the above object. As a first aspect of the present invention, a liquid crystal display is provided by inputting a video signal and outputting display data corresponding to the video signal to a liquid crystal display panel. In a liquid crystal display control device for displaying an image on a panel, a storage element capable of storing the input video signal, and storing the video signal in the storage element at the input timing to the liquid crystal display panel There is provided a liquid crystal display control device comprising memory control means for reading out the video signal from the storage element at a timing of outputting the display data.

  The operation of the first aspect will be described.

  The memory control means stores the input video signal such as a personal computer in the storage element at the input timing. On the other hand, the video signal is read from the storage element at the timing of outputting the display data to the liquid crystal display panel. Accordingly, it is sufficient that the storage element has a storage capacity for two lines.

  As a second aspect of the present invention, in a liquid crystal display control apparatus that receives a video signal and displays a video corresponding to the video signal on a liquid crystal display panel, a frame memory that stores the input video signal; A line memory for storing a video signal read from the frame memory, a memory control means for controlling writing and reading of a video signal of data to and from the frame memory and the line memory, and a video read from the frame memory An arithmetic processing circuit that performs a predetermined process on the signal and the video signal read from the line memory and then outputs the processed signal to the liquid crystal display panel, and the memory control means is configured to output the video from the frame memory. A predetermined interval is set between reading the signal and writing the video signal to the frame memory. The liquid crystal display control apparatus characterized by synchronizing the bets is provided.

  In this case, the storage capacity of the frame memory is preferably two lines of the input video signal.

  The operation of the second aspect will be described.

  The memory control means causes the video signal input from the personal computer or the like to be read from the frame memory. In this case, the memory control means synchronizes this reading with the writing of the video signal to the frame memory at a predetermined interval (it is not always necessary to synchronize). Therefore, the storage capacity of the frame memory is sufficient for two lines of video signals.

  The arithmetic processing circuit performs predetermined processing (for example, enlargement processing) on the video signal read from the frame memory and the video signal read from the line memory, and then outputs the processed signal to the liquid crystal display panel. In the case where the predetermined process is an enlargement / reduction process, the certain interval defined above is determined according to the enlargement / reduction ratio.

  If the frame memory and the line memory are composed of a single type of storage element, it is advantageous from the viewpoint of simplifying the device. In the present invention, it is necessary to control input / output asynchronously and to perform input / output operations simultaneously. Therefore, a FIFO type line buffer is most preferable as the memory element to be used (the same applies to other aspects of the present invention). If the video signal is processed in two parallel, the frame memory can be configured using a FIFO type line memory having a capacity of one line in the expansion direction. In this way, the amount of data that can be processed within a unit time is doubled, so that the processing speed is improved.

  As a third aspect of the present invention, in a liquid crystal display control device that receives a video signal and displays a video corresponding to the video signal on a liquid crystal display panel, a frame memory that stores the input video signal; A memory mounting unit capable of mounting a separately prepared line memory for storing a video signal read from the frame memory; input / output of a video signal to / from the frame memory; and a line memory mounted to the memory mounting unit The video signal read from the memory control means configured to be able to control input / output of the video signal to and from the frame memory or the line memory mounted on the frame memory and the memory mounting unit A liquid crystal display comprising: an arithmetic processing circuit that outputs the liquid crystal display panel after the processing Your device is provided.

  In this case, it is preferable that the arithmetic processing circuit changes the processing contents depending on the presence or absence of the line memory.

  Furthermore, it is preferable that the memory mounting portion is configured so that a memory card can be mounted.

  The processing performed by the arithmetic processing circuit may include video enlargement / reduction processing corresponding to the video signal.

  The operation of the third aspect will be described.

  The memory control means inputs / outputs a video signal to / from a frame memory and a line memory mounted on the memory mounting unit (which may be a memory card). The arithmetic processing circuit performs predetermined processing (for example, video enlargement / reduction processing corresponding to the video signal) on the video signal read from the frame memory and the line memory mounted on the memory mounting unit, and then the liquid crystal Output to the display panel. The arithmetic processing circuit changes the processing contents according to the presence or absence of the line memory. Therefore, it is possible to configure a system according to the image quality desired by each user and the allowable cost depending on whether or not the line memory is simply attached.

  According to a fourth aspect of the present invention, in a liquid crystal display control apparatus that receives a video signal and displays a video corresponding to the video signal on a liquid crystal display panel, the resolution determination that determines the resolution of the input video signal. Means, a first processing means for outputting the video signal as a bypass video signal as it is, a second processing means for performing a predetermined process on the input video signal and then outputting it as a processing signal, and the first processing. Or a timing adjustment unit that adjusts an output timing of the signal output from the second processing unit to the liquid crystal display panel, wherein the first processing unit obtains the video obtained by the determination of the resolution determination unit. When the resolution of the signal matches the resolution of the liquid crystal display panel, the bypass video signal is output and, conversely, obtained by the determination of the resolution determination means. The output of the bypass video signal is stopped when the resolution of the received video signal does not match the resolution of the liquid crystal display panel, and the second processing means is obtained by the determination of the resolution determination means. When the resolution of the video signal matches the resolution of the liquid crystal display panel, output of the processing signal is stopped, and conversely, the resolution of the video signal obtained by the determination of the resolution determination means is the liquid crystal display panel. A liquid crystal display control device is provided that outputs the processing signal when the resolution does not match the resolution.

  In this case, the second processing means may perform an enlargement process on the video signal.

  The operation in the fourth aspect will be described.

  The resolution determination unit determines the resolution of the input video signal. The first processing means and the second processing means change the processing operation according to the determination result. That is, when the resolution of the video signal obtained by the determination by the resolution determination unit matches the resolution of the liquid crystal display panel, the first processing unit outputs a bypass video signal. On the other hand, the second processing means stops outputting the processing signal. Conversely, if the resolution of the video signal does not match the resolution of the liquid crystal display panel, the second processing means performs a predetermined process (for example, video enlargement process) on the input video signal and then outputs it as a processed signal To do. On the other hand, the first processing means stops outputting the bypass video signal. The timing adjusting unit adjusts the timing of the signal output from the first processing unit or the second processing unit, and then outputs the signal to the liquid crystal display panel.

  By switching the video signal processing means (or processing path) in accordance with the resolution in this way, it is not necessary to employ elements that can handle video signals of any resolution as the elements constituting each processing means. For example, when the second processing means performs an enlargement process performed using a frame memory or the like, the second processing means is not required to be capable of processing a high-resolution video signal that matches the resolution of the liquid crystal panel. . Therefore, the frame memory of the second processing means can be configured using an inexpensive memory having a low access speed.

  As described above, according to the present invention, an enlarged display of a video signal on a liquid crystal display panel can be realized by a low-speed and low-capacity memory (for example, a FIFO type line buffer).

  Further, the enlargement processing method can be selected depending on whether or not the line memory is installed. Therefore, the user can select an optimum apparatus configuration according to the application, cost, and required image quality.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 1, the liquid crystal display control device of this embodiment includes an A / D conversion circuit 104, a resolution determination circuit 107, a gate circuit 109, a frame memory 110, a line memory 111, a frame / line memory control circuit 112, and a display timing. A generation circuit 120 is provided. Needless to say, this liquid crystal display control device is used by being connected to the personal computer 101 and the liquid crystal display panel 124. Here, it is mainly assumed that the liquid crystal display panel 124 is connected to a high resolution (for example, 1024 × 768 dots).

  The A / D conversion circuit 104 digitizes the analog video signal 102 output from the personal computer 101 and outputs the digital video signal 105 to the frame memory 110 and the gate circuit 109. Similarly, the synchronization signal 103 output from the personal computer 101 is also converted to a digital signal and output to the frame / line memory control circuit 112 as a dot clock 106. This dot clock 106 indicates the conversion speed of the A / D conversion circuit 104.

  The resolution determination circuit 107 determines the resolution of the video signal 102 based on the synchronization signal 103. The resolution determination circuit 107 outputs the determination result as the resolution determination result 108 to the gate circuit 109, the frame / line memory control circuit 112, and the display timing generation circuit 120.

  The gate circuit 109 is for performing bypass processing of the digital video signal 105. The gate circuit 109 of the present embodiment opens the gate when the digital video signal 105 whose resolution matches the resolution of the liquid crystal display panel 124 is input, and the display timing generation circuit 120 uses the digital video signal 105 as bypass data 117. It is configured to output to. When a digital video signal 105 having a resolution other than this is input, the gate is closed and the video signal 105 is not passed. The gate circuit 109 acquires the resolution of the video signal 105 input at that time based on the resolution determination result 108 input from the resolution determination circuit 107.

  The frame memory 110 is for temporarily storing the digital video signal 105. In the present embodiment, a FIFO type line buffer memory having a storage capacity for two lines of the video signal 105 is employed as the frame memory 110. Data once stored in the frame memory 110 is output as frame memory read data 115 to the enlargement processing control circuit 118 and the line memory 111. The line memory 111 reads and stores the data stored in the frame memory 110 one line at a time in order to be used for video enlargement processing. The line memory 111 also has a storage capacity for two lines of the video signal 105. The data stored in the line memory 111 is output to the enlargement processing control circuit 118 as line memory read data 116. In the present embodiment, input / output to and from the frame memory 110 and the line memory 111 is performed in synchronization. Therefore, even if the frame memory 110 has only two lines, there is no failure. Since this point is one of the features of the present invention, it will be described in detail later. The operations of these memories 110 and 111 are controlled by a frame memory control signal 113 and a line memory control signal 114 input from the frame / line memory control circuit 112.

  The frame / line memory control circuit 112 controls the operations of the frame memory 110 and the line memory 111. Therefore, the frame / line memory control circuit 112 generates a frame memory control signal 113 and a line memory control signal 114 based on the dot clock 106, the synchronization signal 103, the resolution determination result 108, and the memory access arbitration signal 123, and outputs them to the frame. The data is output to the memory 110 and the line memory 111. In addition, a memory configuration decode signal 206 described later is output to the display timing generation circuit 120.

  The enlargement processing control circuit 118 performs enlargement processing using the frame memory read data 115 and the line memory read data 116. The result of the enlargement process is output to the display timing generation circuit 120 as a video signal 119. Note that the video enlargement processing itself by the enlargement processing control circuit 118 and the line memory 111 is basically the same as the above-described conventional technology.

  The display timing generation circuit 120 is for adjusting the video signal 117 and the video signal 119 to the display timing of the liquid crystal display panel 124. The display timing generation circuit 120 adjusts the timing of these signals, and then outputs them as a video signal 121 to the liquid crystal display panel 124. However, as described above, only one of the video signal 117 and the video signal 119 is input according to the video signal 105 input at that time, and both are not input simultaneously. The timing adjustment operation performed by the display timing generation circuit 120 also differs depending on the resolution determination result 108 (that is, the resolution of the video signal 105 input at that time). In addition, the display timing generation circuit 120 generates a display timing signal 122 and a memory access arbitration signal 123 based on the synchronization signal 103 and the resolution determination result 108. The display timing signal 122 is output to the liquid crystal display panel 124, while the memory access arbitration signal 123 is output to the frame / line memory control circuit 112. This memory access arbitration signal 123 is a signal synchronized with the display timing of the liquid crystal display panel 124. Reading of data from the frame memory 110 described above is performed in synchronization with the memory access arbitration signal 123. The display timing signal 122 and the memory access arbitration signal 123 also differ depending on the resolution determination result 108.

  This embodiment is characterized in that the timing of the digital video signal 105 and the frame memory read data 115 is synchronized. Further, when the resolution of the analog video signal 102 (digital video signal 105) matches the resolution of the liquid crystal display panel 124, the display data is output as bypass data 117 through the gate circuit 109. . With such a feature, in this embodiment, a low-speed, low-capacity FIFO type line buffer similar to the line memory 111 can be used as the frame memory 110.

  Next, an outline of the operation of the liquid crystal display control device of this embodiment will be described with reference to FIG.

  The A / D conversion circuit 104 converts the analog video signal 102 into a digital video signal 105. In parallel with this, the resolution determination circuit 107 performs resolution determination based on the horizontal / vertical synchronization signal 103. Then, the determination result 108 is output to the gate circuit 109, the frame / line memory control circuit 112, and the display timing generation circuit 120.

The gate circuit 109, the frame / line memory control circuit 112, and the display timing generation circuit 120 change the operation contents according to the resolution determination result 108.
(1) When the resolution of the video signal 105 matches the resolution of the liquid crystal display panel 124
The gate circuit 109 opens the gate. Then, the digital video signal 105 input at this time is output to the display timing generation circuit 120 as bypass data 117. The display timing generation circuit 120 adjusts the timing of the bypass data 117 and outputs the display data 121 to the liquid crystal display panel 124. At the same time, the synchronization signal 103 is output to the liquid crystal display panel 124 as the display timing signal 122. On the other hand, the frame / line memory control circuit 112 stops the memory access in this case (when the resolution of the video signal 105 matches the resolution of the liquid crystal display panel 124).
(2) When the resolution of the digital video data 105 is lower than the resolution of the liquid crystal panel 124 The gate circuit 109 closes the gate. Therefore, the bypass data 117 is not output. On the other hand, the frame / line memory control circuit 112 performs write / read control to be described later on the frame memory 110 and the line memory 111. When the write / read control is performed, the digitized video signal 105 is output to the display timing generation circuit 120 after being subjected to enlargement processing or the like. Hereinafter, the write / read control will be described.

  When the write / read control by the frame / line memory control circuit 112 is started, the digitized video signal 105 is first written to the frame memory 110. The display data written to the frame memory 110 is read according to the memory access arbitration signal 123 (that is, the display timing of the liquid crystal display panel 124), and is sent to the enlargement processing control circuit 118 and the line memory 111 as frame memory read data 115. Is output. In this case, reading from the frame memory 110 is performed in synchronization with writing to the frame memory 110 at predetermined intervals (which are determined according to the enlargement ratio). Therefore, no problem occurs even if the frame memory 110 has a capacity of only two lines.

  The display data written to the line memory 111 is read after being delayed for a certain period and output to the enlargement processing control circuit 118. The enlargement process control circuit 118 executes an enlargement process based on the frame memory read data 115 and the line memory read data 116. Then, the result of the enlargement process is output to the display timing generation circuit 120 as a video signal 119. The display timing generation circuit 120 adjusts the timing of the video signal 119. Then, the video signal after the timing adjustment is output as display data 121 to the liquid crystal display panel 124 together with the display timing signal 122. Further, the display timing signal 122 is generated by the synchronization signal 103 and the synchronization signal generated inside the display timing generation circuit 120 and is output to the liquid crystal panel 124.

  This is the end of the summary description of the present embodiment.

  Next, details of the memory access arbitration signal generation unit 213 in the frame / line control circuit 112 and the display timing generation circuit 120 in FIG. 1 will be described with reference to FIG.

  The frame / line control circuit 112 includes an input video signal validation circuit 204, a memory configuration decoding circuit 205, an enlargement operation decoding circuit 207, a synchronization circuit 209, an internal horizontal synchronization signal generation circuit 211, a memory access arbitration circuit 213, and a frame memory write control. A circuit 214, a frame memory read control circuit 215, a line memory write control circuit 216, and a line memory read control circuit 217 are provided.

  The memory configuration decoding circuit 205 decodes the mode signal 201 input from the outside of the frame / line memory control circuit 112 and outputs the decoding result as a decoding signal 206. The decode signal 206 indicates the memory configuration of the frame memory 110 and the line memory 111. Table 1 shows the decoding correspondence list of the mode signal 201.

  There are three memory configuration modes: both frame / line memory, only frame memory, and no frame / line memory. In this embodiment, since both the frame memory 110 and the line memory 111 are provided (see FIG. 1), the mode signal 201 is “MODE (1: 0) = (0, 0)”.

  The enlargement operation decoding circuit 207 decodes the operation mode signal 203 indicating the enlargement operation mode, and outputs the decoding result as a decode signal 208. The operation mode signal 203 is input from outside the frame / line memory control circuit 112. Table 2 shows a decoding correspondence list of the operation mode signal 203.

  The mode signal 201 and the operation mode signal 203 are logically “H” or “L” fixed level signals.

  Here, there are six calculation modes: through mode (with / without memory), 2 → 3 enlargement (gradation integration method / simple enlargement method), and 4 → 5 enlargement (gradation integration method / simple enlargement method). And The through mode is a mode in which a video signal having a resolution that can be enlarged and displayed is displayed in the input size without being enlarged. The gradation integration method is a method of increasing the number of dots by assigning gradation weights to each dot and making the data obtained as a result of a predetermined calculation correspond to the dots of the liquid crystal display panel 124. (See FIG. 3). The simple enlargement method is a method in which a certain dot is displayed in correspondence with two dots on the liquid crystal display panel 124, and the remaining dots are displayed in correspondence with one dot on the liquid crystal display panel 124 (see FIG. 4).

  In the configuration of FIG. 1, the through mode “SCALE (2: 0) = (0, 0, 1)” with memory and 2 → 3 enlargement (gradation integration method) “SCALE (2: 0) = (0, 1, 0) ”and 4 → 5 enlargement (gradation integration method)“ SCALE (2: 0) = (1, 0, 0) ”. Here, the enlargement size is 2 → 3 (1.5 times) or 4 → 5 (1.25 times), which is merely an example, and an arbitrary magnification can be set.

  Table 3 shows a list of enlarged sizes in various input modes.

  Here, it is assumed that the resolution of the liquid crystal display panel 124 is a high resolution of 1024 × 768 (XGA mode). Only the medium resolution input mode of 800 × 600 (SVGA) is 4 → 5 (1.25 times) enlargement. In other low resolution input modes, the enlargement is 2 → 3 (1.5 times). In the same 1024 × 768 (XGA) input mode as the liquid crystal display panel 124, the through mode is set.

  The synchronization circuit 209 in FIG. 2 synchronizes the input horizontal synchronization signal 103 with the reference clock 202 serving as a reference for display timing, and then outputs it to the internal horizontal synchronization signal generation circuit 211 as the input horizontal synchronization signal 210. The reference clock 202 is input from a clock provided outside the frame / line memory control circuit 112.

  The internal horizontal synchronization signal generation circuit 211 synthesizes the input horizontal synchronization signal 210 with the internal horizontal synchronization signal that is generated internally, and then outputs it to the memory access arbitration circuit 213 as the output horizontal synchronization signal 212.

  The memory access arbitration circuit 213 is for adjusting the timing of access to the frame memory 110 and the line memory 111. The memory access arbitration signal 123 output from the memory access arbitration circuit 213 is used when each display of the through mode, the gradation integration mode, and the simple enlargement mode is performed according to the memory configuration by the mode signal 201 and the calculation mode signal 203. This signal determines the access method of the frame memory 110 and the line memory 111. Specifically, it is shown in the horizontal direction memory access timing chart of FIG. 5 to FIG. 7 (in the second embodiment described later, FIG. 9 and FIG. 10). This is for selecting an operation sequence to be shown. The memory access arbitration circuit 213 is actually included in the display timing generation circuit 120 in FIG.

  The frame memory write control circuit 214 and the frame memory read control circuit 215 are for controlling the frame memory 110.

  The line memory write control circuit 216 and the line memory read control circuit 217 are for controlling the line memory 111.

  Although not shown in FIG. 2, a resolution determination signal 108 is input to each unit shown in FIG. The frame / line memory control circuit 112, the display timing generation circuit 120, and the like perform FIG. 5 to FIG. 7 (the operations shown in FIG. 9 and FIG. 10 in the second embodiment described later) according to the value of the resolution determination signal 108. It is supposed to switch.

  Next, the enlargement processing operation by the frame / line memory control circuit 112 and the like will be described with reference to FIGS.

  FIG. 5 is a timing chart showing the operation of 2 → 3 enlargement (gradation integration method) by the frame / line memory control circuit 112. FIG. 6 is a timing chart showing the operation of 4 → 5 enlargement (gradation integration method). FIG. 7 is a timing chart showing the operation in the through mode when the memory is used.

  The input video signal validation circuit 204 enables the frame memory write control circuit 214 at a predetermined timing determined based on the synchronization signal (VSYNC-N / HSYNC-N) 103 and the dot clock 106.

  The frame memory write control unit 214 in the valid state generates a write signal (clock: FWCLK / write reset: FRSTW-N) of the frame memory 110 based on the decode signal 206 and the dot clock 106. This write signal constitutes a part of the frame memory control signal 113 in FIG. The write operation to the frame memory 110 performed in accordance with the write signal 113 is synchronized with the horizontal synchronization signal (HSYNC-N) 103 in all modes shown in FIGS.

  The control content by the frame memory read control circuit 215 is the same as the control content by the line memory write control circuit 216. This is because the data read from the frame memory 110 is immediately written to the line memory 111 in the case of enlargement processing by the gradation integration method (see FIGS. 5 and 6). For example, in the example of FIG. 5, the reading of data from the frame memory 110 (FRData 115) and the writing of data to the line memory 111 (LWData 115) are always performed at the same timing.

  Reading from the line memory 111 is performed before the write cycle (in the present embodiment, two dot clocks). This is because a write operation to the line memory 111 is enabled.

  In the vertical direction, input / output is synchronized at regular intervals. That is, the input horizontal synchronization signal synchronization circuit 209 synchronizes the input horizontal synchronization signal (HSYNC-N) 103 with the display timing reference clock 202 and then outputs it as the input horizontal synchronization signal 210. The internal horizontal synchronization signal generation circuit 211 synthesizes the internal horizontal synchronization signal generated within itself and the input horizontal synchronization signal 210. Then, the signal obtained by this synthesis is output to the memory access arbitration circuit 213 as the output horizontal synchronization signal 212. In the case of 2 → 3 enlargement (gradation integration method), the internal horizontal synchronization signal generation circuit 211 inputs the output horizontal synchronization signal 212 every time the input horizontal synchronization signal (HSYNC-N) 103 is output twice. Synchronize with the horizontal synchronizing signal 103. Then, after the synchronization and before the next synchronization, the output horizontal synchronization signal 212 is generated twice (see FIG. 5). On the other hand, in the case of 4 → 5 enlargement (gradation integration method), the internal horizontal synchronization signal generation circuit 211 synchronizes the output horizontal synchronization signal 212 every time the input horizontal synchronization signal (HSYNC-N) 103 is output four times. . Then, after the synchronization and before the next synchronization, the output horizontal synchronization signal 212 is generated four times (see FIG. 6). Switching of the processing contents according to such an enlargement ratio is performed based on the decode signal 208.

  The memory access arbitration circuit 213 generates a memory access arbitration signal 123 based on the output horizontal synchronization signal 212. Then, this is output to the frame memory read control circuit 215, the line memory write control circuit 216, and the line memory read control circuit 217.

  In addition to the memory access arbitration signal 123, the frame memory read control circuit 215, the line memory write control circuit 216, and the line memory read control circuit 217 receive the memory configuration decode signal 206, the enlarged operation decode signal 208, and the reference clock 202. Has been. The frame memory read control circuit 215 generates and outputs a frame memory read control signal (clock: FRCLK / read reset: FRSTR-N) in accordance with these signals 202, 206, 208, and 123. The frame memory read control signal constitutes a part of the frame memory control signal 113 in FIG. Similarly, the line memory write control circuit 216 generates a line memory write control signal (clock: LWCLK, write reset: LRSTW-N). The line memory read control circuit 217 generates a line memory read control signal (clock: LRCLK, read reset: LRSTR-N). The line memory write control signal and the line memory read control signal constitute the line memory control signal 114 in FIG.

  In the case of the through mode when using the memory (see FIG. 7), only the frame memory 110 is used because the enlargement process is not performed. The frame / line memory control circuit 112 generates the output horizontal synchronization signal 212 at the same timing as the input horizontal synchronization signal 103. The read cycle is read with a delay of one line (one horizontal period) with respect to the frame memory write cycle.

  As described above, according to the first embodiment (FIGS. 1 and 2), enlarged display by the gradation integration method and through display using a memory are possible. Further, since the read operation and the write operation of the frame memory 110 are performed in synchronization, a FIFO type line buffer having a capacity of two lines can be used as the frame memory 110.

  Further, when the analog video signal 102 having the same high resolution as that of the liquid crystal display panel 124 is input, the frame memory 110 and the line memory 111 are bypassed to perform through display. Therefore, the memories 110 and 111 only need to have a processing speed capable of processing a video signal having a medium resolution or less, and an inexpensive low-speed memory can be used. Frame memory 110 and line memory usable when the resolution of the liquid crystal display panel 124 is 1024 × 768 (XGA mode), the display processing speed is 30 MHz, the input operation speed of the medium resolution video signal is 50 MHz at maximum, and two parallel processing An example of 111 is shown in Table 4.

  Here, since it is assumed that the data is processed in two parallels, the dot clock is 25 MHz which is half of the input operation speed of 50 MHz. In this embodiment, the high-resolution video signal does not pass through the memories 110 and 111. Therefore, the memories 110 and 111 only need to be compatible with a dot clock of 25 MHz. On the other hand, when the present invention is not applied, a high-resolution video signal (XGA mode) must also be processed through the memories 110 and 111. In this case, the input processing speed is as high as 70 MHz, and the dot clock is also as high as 37.5 MHz. To follow this, an expensive high-speed memory is required.

  A second embodiment of the present invention will be described with reference to FIG.

  The second embodiment employs a simple enlargement method (see FIG. 4) as an enlargement processing method. Therefore, no line memory is installed. In FIG. 8, a part surrounded by a broken line is a part different from the first embodiment (see FIG. 1).

  Timing charts for 2 → 3 enlargement and 4 → 5 enlargement using the simple enlargement method (see FIG. 4) are shown in FIGS. The frame / line memory control circuit 112 performs input horizontal synchronization signal synchronization, internal horizontal synchronization signal generation, and the like in the same manner as in the first embodiment (see FIG. 2). Therefore, the circuit shown in FIG. 2 can be used as it is in the second embodiment.

  The control switching between the gradation integration method and the simple enlargement method is performed by a decode signal 208 obtained by decoding the operation mode signal 203 (see FIG. 2) by the enlargement operation decoding circuit 207.

  Both the 2 → 3 simple enlargement process and the 4 → 5 simple enlargement process in this embodiment are realized by reading the first line from the frame memory 110 twice. Even when the line memory 111 is installed, if the read / write control for the line memory 111 is disabled, simple enlargement processing can be realized.

  The liquid crystal display control device of the embodiment described above can change the contents (that is, the image quality) of the enlargement process depending on whether or not the frame memory is installed. In this case, it is not necessary to change the control circuit. Therefore, for example, if the line memory 111 is formed as a memory card and can be arbitrarily mounted, the end user can freely select an enlargement processing method (image quality) according to the application and cost.

  A configuration for detecting a memory configuration when the line memory 111 is formed into a memory card will be described with reference to Table 5 and FIG. In this description, it is assumed that the mode signal settings associated with the memory configuration are as shown in Table 5 below.

  In the through mode in which no memory is used, the resistors R2 and R3 are mounted, and the MODE (1: 0) signal is logically at the “L” level. When only the frame memory is mounted and the simple enlargement process is performed, the resistor R1 is mounted instead of the resistor R2, so that MODE (1: 0) = (L, H). When the line memory is mounted by the memory card, one end of the resistor R4 mounted on the memory card is connected to the MODE1 terminal, and this terminal is logically at the “H” level. That is, MODE (1: 0) = (H, H) level. As a result, it is recognized that both the frame memory and the line memory are mounted, and gradation integration processing is possible.

It is a block diagram which shows schematic structure of the liquid crystal display control apparatus which is one Embodiment of this invention. 3 is a block diagram showing an example of the internal configuration of a frame / line control circuit 112 and a memory access arbitration signal generation unit 213 in the display timing generation circuit 120. FIG. It is a figure which shows the outline | summary of the expansion process system by a gradation integration system. It is a figure which shows the outline | summary of the expansion processing system by a simple expansion system. It is a timing chart which shows the operation | movement at the time of 2-> 3 expansion by a gradation integration system. It is a timing chart which shows the operation | movement at the time of 4-5 expansion by a gradation integration system. It is a timing chart which shows operation | movement of through mode at the time of memory utilization. It is a block diagram which shows schematic structure of the liquid crystal display control apparatus which is the 2nd Embodiment of this invention. It is a timing chart which shows the operation | movement at the time of 2 → 3 expansion by a simple expansion system. It is a timing chart which shows the operation | movement at the time of 4-5 expansion by a simple expansion system. It is a figure which shows the structure for detecting a memory structure. It is a block diagram which shows an example of a structure of the conventional liquid crystal display control apparatus. 1 is a block diagram showing details of a conventional frame memory circuit 1106. FIG.

Explanation of symbols

101 ・ ・ ・ Personal computer
102 ... Analog video signal
103 Sync signal
104 A / D conversion circuit
105 ... Digital video signal
106 ... dot clock
107 ... Resolution judgment circuit
108 ・ ・ ・ Resolution judgment result
109 ・ ・ ・ Gate circuit
110 ・ ・ ・ Frame memory
111 ・ ・ ・ Line memory
112... Frame / line memory control circuit
113 ・ ・ ・ Frame memory control signal
114 ... Line memory control signal
115 ... Frame memory read data
116 ... Line memory read data
117 ... Bypass data
118 ・ ・ ・ Enlargement processing control circuit
119 ... Video signal after enlargement processing
120 ... Display timing generation circuit
121 ・ ・ ・ Video signal after timing adjustment
122 ... Timing signal for display
123 ・ ・ ・ Memory access arbitration signal
124 ... LCD panel
201 ... Mode signal
202 ... Reference clock
203 ・ ・ ・ Calculation mode signal
204 ・ ・ ・ Input video signal validation circuit
205 ... Memory configuration decoding circuit
206 ... Memory configuration decode signal
207 ... Enlarged operation decoding circuit
208 ... Enlarged operation decode signal
209 ... Synchronous circuit
210 ... Synchronized input horizontal sync signal
11 ... Internal horizontal sync signal generation circuit
212 ・ ・ ・ Output horizontal sync signal
213: Memory access arbitration circuit
214 ... Frame memory write control circuit
215: Frame memory read control circuit
216: Line memory write control circuit
17 ... Line memory read control circuit

Claims (22)

  In a display system that displays an enlarged video signal,
  A control circuit for inputting the video signal according to an input synchronization signal and outputting the video signal according to an output synchronization signal;
  A display panel for displaying the video signal;
  A processing circuit for enlarging the video signal to a non-integer multiple according to (resolution of the display panel) / (resolution of the video signal input to the control circuit),
  Each time the input synchronization signal occurs M times and the output synchronization signal occurs N times, the output synchronization signal is synchronized with the input synchronization signal,
  N ≠ M and N> M,
  N / M is a non-integer,
  N / M corresponds to (resolution of the display panel) / (resolution of the video signal input to the control circuit),
  The generation period of the output synchronization signal is constant,
  The control circuit outputs the video signal input with M input synchronization signals as N output synchronization signals,
  The processing circuit generates video data to be inserted into the video signal in order to expand the video signal, using the video signal output from the control circuit with N output synchronization signals. Display system.   The display system of claim 1,
  The control circuit includes a memory capable of storing the video signal,
  The display system, wherein the control circuit inputs the video signal to the memory in accordance with the input synchronization signal, and outputs the video signal from the memory in accordance with the output synchronization signal.   The display system of claim 2,
  The display system, wherein the memory can store the video signal for one frame.   The display system of claim 2,
  2. The display system according to claim 1, wherein the memory can store the video signal for two lines.   The display system according to any one of claims 1 to 4,
  The display system according to claim 1, wherein the processing circuit generates video data to be inserted into the video signal by a gradation integration method.   The display system according to any one of claims 1 to 5,
  A timing generation circuit for generating a display timing signal used by the display panel based on the input synchronization signal;
  The display system, wherein the timing generation circuit receives the enlarged video signal, and outputs the video signal together with the display timing signal to the display panel.   The display system of claim 6,
  The timing generation circuit generates the output synchronization signal by combining a circuit for synchronizing the input synchronization signal with a reference clock, and the input synchronization signal and an internal synchronization signal generated inside the timing generation circuit. A display system comprising: a generation circuit.   The display system according to any one of claims 1 to 7,
  A determination circuit for determining a resolution of a video signal input to the control circuit based on the input synchronization signal;
  The processing circuit uses the determination result of the determination circuit to expand the video signal to a non-integer multiple according to (resolution of the display panel) / (resolution of the video signal input to the control circuit). A display system characterized by   The display system of claim 8,
  A timing generation circuit for generating a display timing signal used by the display panel based on the input synchronization signal and the determination result of the determination circuit;
  The display system, wherein the timing generation circuit receives the enlarged video signal, and outputs the video signal together with the display timing signal to the display panel.   The display system of claim 9,
  A bypass for bypassing the processing circuit and outputting the video signal to the generation circuit when the resolution of the video signal input to the control circuit matches the resolution of the display panel according to the determination result of the determination circuit A display system comprising a circuit.   The display system of claim 2,
  The processing circuit is connected between the memory and the display panel,
  The display system, wherein the processing circuit expands the video signal output from the memory to a non-integer multiple.   In a display system that displays an enlarged video signal,
  A control circuit for inputting the video signal according to an input synchronization signal and outputting the video signal according to an output synchronization signal;
  A display panel for displaying the video signal;
  A processing circuit for enlarging the video signal to a non-integer multiple according to (resolution of the display panel) / (resolution of the video signal input to the control circuit),
  Each time the input synchronization signal occurs M times and the output synchronization signal occurs N times, the output synchronization signal is synchronized with the input synchronization signal,
  N ≠ M and N> M,
  N / M is a non-integer,
  N / M is synchronized with (resolution of the display panel) / (resolution of the video signal input to the control circuit),
  Each period of the output synchronization signal is M / N times the period of the input synchronization signal;
  The control circuit outputs the video signal input in accordance with M input synchronization signals in accordance with N output synchronization signals,
  The processing circuit generates video data to be inserted into the video signal in order to expand the video signal, using the video signal output from the control circuit with N output synchronization signals. Display system.   The display system of claim 12,
  The control circuit includes a memory capable of storing the video signal,
  The display system, wherein the control circuit inputs the video signal to the memory in accordance with the input synchronization signal, and outputs the video signal from the memory in accordance with the output synchronization signal.   The display system of claim 13,
  The display system, wherein the memory can store the video signal for one frame.   The display system of claim 13,
  2. The display system according to claim 1, wherein the memory can store the video signal for two lines.   The display system according to any one of claims 12 to 15,
  The display system according to claim 1, wherein the processing circuit generates video data to be inserted into the video signal by a gradation integration method.   The display system according to any one of claims 12 to 16,
  A timing generation circuit for generating a display timing signal used by the display panel based on the input synchronization signal;
  The display system, wherein the timing generation circuit receives the enlarged video signal, and outputs the video signal together with the display timing signal to the display panel.   The display system of claim 17,
  The timing generation circuit generates the output synchronization signal by combining a circuit for synchronizing the input synchronization signal with a reference clock, and the input synchronization signal and an internal synchronization signal generated inside the timing generation circuit. A display system comprising: a generation circuit.   The display system according to any one of claims 12 to 18,
  A determination circuit for determining a resolution of a video signal input to the control circuit based on the input synchronization signal;
  The processing circuit uses the determination result of the determination circuit to expand the video signal to a non-integer multiple according to (resolution of the display panel) / (resolution of the video signal input to the control circuit). A display system characterized by   The display system of claim 19,
  A timing generation circuit for generating a display timing signal used by the display panel based on the input synchronization signal and the determination result of the determination circuit;
  The display system, wherein the timing generation circuit receives the enlarged video signal, and outputs the video signal together with the display timing signal to the display panel.   The display system of claim 20,
  A bypass for bypassing the processing circuit and outputting the video signal to the generation circuit when the resolution of the video signal input to the control circuit matches the resolution of the display panel according to the determination result of the determination circuit A display system comprising a circuit.   The display system of claim 13,
  The processing circuit is connected between the memory and the display panel,
  The display system, wherein the processing circuit expands the video signal output from the memory to a non-integer multiple.

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