200847125 九、發明說明： 【發明所屬之技術領域】 本發明係關於影像處理，特別是關於一種用以放大或縮小一源影像 之解析度以產生一目標影像之影像縮放裝置及其方法。 【先前技術】 影像縮放裝置係用於接收並顯示包含在連續通道視頻訊號中的影 像圖框。衆所周知，影像圖框係以晝素資料單元來表示，而畫素資料 單元係根據影像訊號中之顯示資料部分進行編碼而得。第一圖繪示習 知影像縮放裝置，其包括-接收器1〇2、一影像縮放單元1〇4、一發射 器106、一時脈產生器11〇，以及一振盪器114。接收器1〇2接收輸入 之視頻訊號，並從中提取出輸人晝素資料、輸人垂直同步訊號及輸入 水平同步訊號，並將該些訊號輸出至影像縮放單元1〇4。時脈產生器11〇 根據該振m器1M之輸出產生-輸出時脈訊號。影像縮放單元舰將解 析度較小的源影像訊號（即輸人晝素資料、輸人垂直同步訊號及輸入 水平同步訊號）進行内插處理，而產生解析度較大之目標影像訊號（輸 出畫素資料、輸出垂直同步訊號及輪出水平同步訊號），以顯示於顯示 器螢幕。例如，源影像訊號以預定解析度顯* (例如由⑦初乂解碼 器所得的驗120大小的影像資料），而經由影像縮放單元1〇4放大後 即可顯示於-較大_示||螢幕上（如—的CRT顯示榮幕）。 發射器將該輸出畫素資料、該輪出垂直同步訊號及該輪出水平同 步訊號轉換為輸出視頻訊號，以供顯示單元（未圖示）顯示。 5 200847125 然而，在此種架構中，接收器102使用的是時脈產生器11〇產生的 輸入時脈(通常為一較低之時脈），而影像縮放單元和發射器使 用的是時脈產生器110產生的輸出時脈(通常為一較高之時脈）；換言 之，時脈產生器110須產生兩種時脈分別提供給接收器1〇2、影像縮放 單元104和發射器106。因此，在影像放大過程中，資料必須跨越兩個 時脈域（ClockDomain)，如此較易產生訊號不穩定的現象。 另請參見第二圖，美國專利第5,739,867號揭示了另一習知影像縮 放裝置100。影像縮放裝置1〇〇包括一時間基礎轉換器31〇、一資料路 徑控制區塊330、一 SCLK時脈產生器340、一 DCLK時脈產生器350, 以及一内插器320。時間基礎轉換器31〇包括一輸入資料同步器41〇、 一線緩衝器420、一先入先出器（FIF0 ) 43 〇以及一控制邏輯440。SCLK 時脈產生器340與DCLK時脈產生器350在資料路徑控制區塊330的 控制下分別產生SCLK時脈和DCLK時脈，以供該輸入資料同步器410 使用。輸入資料同步器410以輸入時脈SCLK接收源影像晝素資料， 並且以輸出時脈DCLK輸出此相同的資料。線緩衝器420使用DCLK 時脈訊號接收和輸出該源影像晝素資料。先入先出器43〇係用以解決 對線緩衝器420的讀取和寫入周期之間的衝突。控制邏輯440用以協 調和控制輸入資料同步器41〇、線緩衝器420以及先入先出器的操作。 内插器320包括一内插器線緩衝器510、一垂直内插器520及一水平内 插器530。垂直内插器52〇接收一當前線晝素資料和前一線晝素資料以 作爲輸入，並執行垂直内插運算。水平内插器530接收用於每一條掃 6 200847125 描線的畫素資料，並對其執行水平内插。細在上述繼，輸出時 脈舰係根據輸出晝面的解析度與輸入畫面解析度之間的比例關係 計异而得’而DCLK的計算方式以保持輸人與輸出晝面的圖框鮮 例如為60Hz)相同為依據。換言之，由於内插器中對 畫素資料進行内_作，使得其輸㈣晝素倾量她讀入的源影 像晝素資料量有所增加，而爲了保持輸入和輸出晝面的圖框頻率相 同因而内插器32〇使用的時脈頻率應大於輸入資料同步器仙截取 晝面時所用的時脈頻率。因此，在前述習知影像縮放裝置中，影像資 «_ (aGekDGmain) ’ _易產生訊號不穩定的 現象。 故，有必要提供一種影像縮放器及其方法，以解決習知技術中所存 在的問題。 【發明内容】 本發明之-目的在於提供—種影像縮放裝置，其制單一時脈域200847125 IX. DESCRIPTION OF THE INVENTION: FIELD OF THE INVENTION The present invention relates to image processing, and more particularly to an image scaling apparatus and method for amplifying or reducing the resolution of a source image to produce a target image. [Prior Art] The image scaling device is for receiving and displaying an image frame contained in a continuous channel video signal. As is well known, the image frame is represented by a pixel data unit, and the pixel data unit is encoded according to the portion of the displayed data in the image signal. The first figure shows a conventional image scaling device comprising a receiver 1, 2, an image scaling unit 1, 4, a transmitter 106, a clock generator 11A, and an oscillator 114. The receiver 1〇2 receives the input video signal, and extracts the input and output data, the input vertical synchronization signal and the input horizontal synchronization signal, and outputs the signals to the image scaling unit 1〇4. The clock generator 11 产生 generates and outputs a clock signal according to the output of the oscillator 1M. The image scaling unit ship interpolates the source image signal (ie, the input pixel data, the input vertical sync signal, and the input horizontal sync signal) with a small resolution, and generates a target image signal with a large resolution (output drawing) Prime data, output vertical sync signal and round horizontal sync signal) for display on the monitor screen. For example, the source image signal is displayed at a predetermined resolution (for example, image data of a size of 120 obtained by the 7th initial decoder), and is enlarged by the image scaling unit 1〇4 to be displayed on the larger_show|| On the screen (such as - CRT shows the honor screen). The transmitter converts the output pixel data, the round vertical sync signal and the round horizontal sync signal into an output video signal for display by a display unit (not shown). 5 200847125 However, in this architecture, the receiver 102 uses the input clock generated by the clock generator 11 (usually a lower clock), while the image scaling unit and transmitter use the clock. The output clock generated by the generator 110 (typically a higher clock); in other words, the clock generator 110 must generate two clocks for the receiver 1, the image scaling unit 104, and the transmitter 106, respectively. Therefore, in the process of image enlargement, the data must span two clock domains (ClockDomain), which is more likely to cause signal instability. Another conventional image retracting device 100 is disclosed in U.S. Patent No. 5,739,867. The image scaling device 1A includes a time base converter 31, a data path control block 330, an SCLK clock generator 340, a DCLK clock generator 350, and an interpolator 320. The time base converter 31 includes an input data synchronizer 41, a line buffer 420, a first in first out (FIF0) 43 and a control logic 440. The SCLK clock generator 340 and the DCLK clock generator 350 generate the SCLK clock and the DCLK clock, respectively, under the control of the data path control block 330 for use by the input data synchronizer 410. The input data synchronizer 410 receives the source image pixel data at the input clock SCLK, and outputs the same data at the output clock DCLK. Line buffer 420 receives and outputs the source image data using the DCLK clock signal. The first-in first-out ejector 43 is used to resolve the conflict between the read and write cycles of the line buffer 420. Control logic 440 is used to coordinate and control the operation of input data synchronizer 41, line buffer 420, and first-in first-out. Interpolator 320 includes an interpolator line buffer 510, a vertical interpolator 520, and a horizontal interpolator 530. The vertical interpolator 52 receives an input of the current line and the previous line of the data as an input and performs a vertical interpolation operation. The horizontal interpolator 530 receives the pixel data for each of the scan lines 200848125 and performs horizontal interpolation on it. In the above, the output clock system is calculated based on the proportional relationship between the resolution of the output pupil and the resolution of the input screen, and the DCLK is calculated to keep the input and output frames fresh, for example. The same is based on 60Hz). In other words, due to the internal data of the pixel data in the interpolator, the amount of data of the source image read by the input (4) is increasing, and the frame frequency of the input and output is maintained. The same clock frequency used by the interpolator 32 should be greater than the clock frequency used when the input data synchronizer intercepts the face. Therefore, in the conventional image zooming apparatus described above, the image resource «_(aGekDGmain)'_ is susceptible to signal instability. Therefore, it is necessary to provide an image scaler and method thereof to solve the problems in the prior art. SUMMARY OF THE INVENTION The present invention is directed to providing an image zooming device that produces a single clock domain
Domain) ’崎免輸人資簡輸η制跨越兩個不同時脈域 的問題’使内部訊號能夠更簡單的控制。 之目❸在_供—縣舰定顯频像之顯示器。 •本發a月之再一目的在於提供_種影像縮放方法，以解決輸入資料與 輸出資料間跨越兩個不W脈域的問題，使内部訊號能夠更簡單的控 制。 —種影像縮放裝置，用以放大或縮小— 7 200847125 源办像之解析度w產生—目標影像。此種影像驗裝置包括：一時脈 生器用以產i a夺脈，一影像擷取單元，用以根據時脈產生器產 生之該時脈來接收該源影像資料並從中存取數條源垂直掃描線及源水 平掃描《料，該數條源掃觀f料各包括多觸畫素倾；一影像 縮放單元，用以根據時脈產生器產生之該時脈來接㈣彡像擷取單元輸 出之畫素資料’並對其進行解析度·大或縮小；以及—圖框頻率轉 換器，用以根據時脈產生器產生之該時脈來接收影像縮放單元之輸出 訊號，並將輸出訊號的圖框頻率作轉換或是維持相同頻率，以產生目 標影像。 根據另-技術《，本侧提供—娜像方法，其包含下列步 驟：產生-時脈；根_時脈來接收賴影像資料並從中取得數條源 垂直掃描線及源水平掃描線資料，該數條源掃描線資料各包括源晝素 資料；以及根據該時脈對該源畫素資料進行織操作’以產生目標畫 素資料。 本發明影像縮放裝置從獲取影像訊號直到輸出之全過程均使用相 同的時脈進行工作，保證了影像訊號從輸入到輸出之穩定。 【實施方式】 一般而言，LCD顯示器之基本架構係如第三圖所示。如圖所示， LCD顯示器至少包含-介面電路模組丨以及_顯示模組2。介面電路 模組1係接收由影像輸出裝置（如個人電腦、光碟播放機等；未圖示）所 輸出的原始影像之訊號，並藉由所設置之影像縮放裝置（如本發明之影 8 200847125 像縮放裝置10)進行縮放處理，以配合顯示模組2中之LCD面板（未 圖示）的畫素位置以及解析度而將原始影像之訊號加以轉換，從而經由 LCD面板顯示影像。 請參見第四圖所示，本發明影像縮放裝置1〇包括一影像擷取單元 Π，用以接收不同訊號源所產生的源影像資料，該源影像資料可以是數 位或類比訊號，並從中存取數條線資料，包括晝素資料、垂直同步訊 號及水平同步訊號；一影像縮放(scaling)單元12，用以接收影像擷取單 元U輸出之影像，並對影像進行放大或縮小；一圖框頻率轉換器 (Frame Rate Converter ; FRC) 13，係用以將影像縮放單元12之輸出訊 號的圖框頻率作轉換或是轉相同鮮，以滿足獨麵顯示器的顯 示需求;-時脈產生器M’用以產生一時脈RCLK，並將該時脈祖 分別供給影像單元u、影像職單元12職隨鮮轉換器i3 作爲工麵脈。該RCLK時脈訊號之時轉細需錄高速率的單元 (例如影像繼單元）所要求的日械率騎。由於影賴取單元u原本 所需的時脈輪低，因此可顧例衫統端所提供讀低時脈率當作 控制信號來娜綱取料η以適當方她該時脈腹為基礎 >動。舉例而言，如果原本以低時脈率操作，影像触單元η係以 2個脈波鱗位，現細高_ rclk為鱗，_㈣個脈波 二位。應注意在此-或二個脈波等僅為舉例說明，並無限制本發明 之忍。 包括一線緩衝器020、一先 請參見第五圖所示，影像縮放單元12 9 200847125 入先出器（FIFO) 630、一控制邏輯640、一内插器線緩衝器710、一 垂直内插器720及一水平内插器730。線緩衝器62〇根據時脈產生器 14產生之RCLK時脈接收和緩衝輸出來自影像擷取單元η的垂直線和 水平線畫素資料。舉例而言，線緩衝器620可以是靜態隨機存取記憶 體（SRAM)，亦可為雙埠ram。先入先出器630向垂直内插器720 提供垂直晝素資料，並且用以解決對線緩衝器62〇的讀取和寫入周期 之間的衝突，即當線緩衝器620只有一單一埠以供讀取和寫入共用時， 其能夠確保對線緩衝器620的讀寫操作均可被執行。控制邏輯64〇使 用RCLK時脈訊號協調和控制線緩衝器620與先入先出器630的操作。 内插器線緩衝器710、垂直内插器720及水平内插器73〇係用以對垂直 線及水平線的晝素資料執行内插操作，從而在各垂直及水平目的線上 產生目標晝素資料。以雙線内插為例，内插器線緩衝器710首先提供 前一條掃描線至垂直内插器720。垂直内插器72〇分別從先入先出器 630及内插器線緩衝器710中接收一當前線晝素資料和前一線晝素資料 以作爲輸入，並執行垂直内插運算，以產生額外的水平線。垂直内插 器720輸出的在垂直方向放大後的織具有與目標影像相同的垂直線 數；但是，每條線還需要在水平方向做進-步内插，以產生最後的目 標影像。水平内插器73〇接收用於每一條掃插線的晝素資料（包括因 垂直方向的尺寸放大而產生的額外線），並對其執行水平内插，進而產 生目標畫素資料。 參見第六A及六B圖所示，影像縮放裝置1〇，或1〇，，可另包括一 200847125 時序控 (TimingC麵㈣’用以接收_率轉換㈣的輸 出訊號。輪· 2G綱—物脈_卿咖η之輸 出影像訊號傳給顯示屏面板上的驅動電路，驅動電路根據此時脈來決 定相關元件工作的順序與時機，從而達到正確顯示目標影像的目的。 在第六A騎故—實補中，郷像縮魏置⑴，，雜擷取單元 11、影像織單元12、圖_補邮13、時脈產u 14以及時序控 制器20物嫩含在同—織裝置麵電路（Seaie⑽内，而時 脈產生器14產生該積體電路之功頻率。在第六b圖所示之另一實施 例中，於影像微裝置料，擷取單元u、影像織單元12、 圖柩頻顿及雜產B 14，鱗崎銳含糊一縮放裝 置積體電路内，時脈產生器14產生該積體電路之工作頻率，而時序控 制器20則叹置於該縮放裝置積體電路之外，例如另外的積體電路内。 以上所述者僅爲本發明之較佳實施方式，舉凡熟習本案技術之人士 k依本發批精神所作之等效修飾或變化，皆涵蓋於制之中請專利 範圍内。 【圖式簡單說明】 第一圖係一習知影像系統之結構方塊圖； 第二圖係另一習知影像系統之結構方塊圖； 第二圖係LCD顯示器之示意圖； 第四圖係本發明影像縮放裝置之結構方塊圖； 第五圖係本發明影像縮放裝置之影像縮放單元之結構方塊圖； 11 200847125 第六A圖係本發明影像縮放裝置之各組成單元設置於同一積體電 路中之示意圖；以及 第六B圖係本發明影像縮放裝置之各組成單元設置於不同積體電 路中之示意圖。 【元件符號說明】 影像縮放裝置 10、10,、10”， 影像縮放裝置 100 接收器 102 影像縮放單元 104、12 發射器 106 影像擷取單元 11 時脈產生器 110、14 振盪器 114 圖框頻率轉換器 13 時序控制器 20 時間基礎轉換器 310 内插器 320 資料路徑控制區塊 330 SCLK時脈產生器 340 DCLK時脈產生器 350 輸入資料同步器 410 線緩衝器 420 、 620 先入先出器 430、630 控制邏輯 440 、 640 内插器線緩衝器 510 、 710 垂直内插器 520 、 720 水平内插器 530、730 12Domain) 'The problem of shunning the simplification of the system to cross two different clock domains' makes internal signals easier to control. The witness is in the display of the _ supply-county ship fixed-frequency image. • Another goal of this month is to provide an image scaling method to solve the problem of spanning two non-W domains between input data and output data, so that internal signals can be more easily controlled. - Image zooming device for zooming in or out - 7 200847125 The resolution of the source image is generated - the target image. The image detecting device comprises: a time generator for generating an ia, and an image capturing unit for receiving the source image according to the clock generated by the clock generator and accessing the plurality of sources for vertical scanning. The line and the source horizontally scan the material, and the plurality of source scanning materials each include a multi-touch pixel tilt; an image scaling unit is configured to connect according to the clock generated by the clock generator (4) the image capturing unit output The pixel data 'and its resolution, large or small; and - the frame frequency converter, for receiving the output signal of the image scaling unit according to the clock generated by the clock generator, and outputting the signal The frame frequency is converted or maintained at the same frequency to produce a target image. According to another technique, the side provides a method of anamorphism, which includes the following steps: generating a clock; a root_clock to receive image data and obtain a plurality of source vertical scanning lines and source horizontal scanning line data, The plurality of source scan line data each include source pixel data; and the source pixel data is woven according to the clock to generate target pixel data. The image zooming device of the present invention works by using the same clock from the process of acquiring the image signal until the output, thereby ensuring the stability of the image signal from input to output. [Embodiment] In general, the basic structure of an LCD display is as shown in the third figure. As shown, the LCD display includes at least a -interface circuit module and a display module 2. The interface circuit module 1 receives the signal of the original image output by the image output device (such as a personal computer, a CD player, etc.; not shown), and uses the image zooming device (such as the shadow 8 of the present invention 200847125) The scaling device 10) performs a scaling process to convert the original image signal in accordance with the pixel position and resolution of the LCD panel (not shown) in the display module 2, thereby displaying the image via the LCD panel. As shown in the fourth figure, the image zooming apparatus 1 of the present invention includes an image capturing unit 接收 for receiving source image data generated by different signal sources, and the source image data may be digital or analog signals and stored therein. Taking a plurality of line data, including a pixel data, a vertical synchronization signal, and a horizontal synchronization signal; an image scaling unit 12 for receiving an image output by the image capturing unit U and enlarging or reducing the image; The frame rate converter (FRC) 13 is used to convert or rotate the frame frequency of the output signal of the image scaling unit 12 to meet the display requirement of the single-sided display; - clock generator M' is used to generate a clock RCLK, and the clock ancestor is separately supplied to the image unit u, and the image unit 12 is used as a work surface pulse. When the RCLK clock signal is turned, it is required to record the high-rate unit required for the high-speed unit (such as the image relay unit). Since the time chakra required by the unit u is low, the low clock rate provided by the system can be used as a control signal to take the η as the basis of the appropriate time. move. For example, if the original operation is performed at a low clock rate, the image touch unit η is scaly with 2 pulse waves, and the fine _ rclk is the scale, and the _ (four) pulse is the second. It should be noted that the - or two pulse waves and the like are merely illustrative and do not limit the tolerance of the present invention. Including a line buffer 020, as shown in the first figure, the image scaling unit 12 9 200847125 in-and-out (FIFO) 630, a control logic 640, an interpolator line buffer 710, a vertical interpolator 720 and a horizontal interpolator 730. The line buffer 62 receives and buffers the vertical line and horizontal line pixel data from the image capturing unit n according to the RCLK clock generated by the clock generator 14. For example, the line buffer 620 can be a static random access memory (SRAM) or a double ram. The first in first out 630 provides vertical pixel data to the vertical interpolator 720 and is used to resolve conflicts between the read and write cycles of the line buffer 62, i.e., when the line buffer 620 has only a single pass. When shared for reading and writing, it can ensure that read and write operations to the line buffer 620 can be performed. Control logic 64 uses the RCLK clock signal to coordinate and control the operation of line buffer 620 and first-in first-out 630. The interpolator line buffer 710, the vertical interpolator 720 and the horizontal interpolator 73 are used to perform interpolation operations on the vertical and horizontal line data, thereby generating target pixel data on each of the vertical and horizontal destination lines. . Taking two-line interpolation as an example, the interpolator line buffer 710 first provides the previous scan line to the vertical interpolator 720. The vertical interpolator 72 receives, as input, a current line pixel data and a previous line element data from the first in first out 630 and the interpolator line buffer 710, respectively, and performs a vertical interpolation operation to generate an additional Horizontal line. The vertically magnified output of the vertical interpolator 720 has the same number of vertical lines as the target image; however, each line also needs to be interpolated in the horizontal direction to produce the final target image. The horizontal interpolator 73 receives the pixel data for each of the sweep lines (including the extra lines due to the size enlargement in the vertical direction) and performs horizontal interpolation thereon to generate target pixel data. Referring to Figures 6A and 6B, the image zooming device 1〇, or 1〇, may further include a 200847125 timing control (TimingC surface (4)' for receiving the output signal of the _ rate conversion (4). Wheel 2G - The output image signal of the object _ _ _ _ η is transmitted to the driving circuit on the display panel, and the driving circuit determines the order and timing of the relevant components according to the pulse at this time, thereby achieving the purpose of correctly displaying the target image. Therefore, in the real compensation, the image is reduced to Wei (1), the hybrid unit 11, the image weaving unit 12, the map _ refill 13, the clock production u 14 and the timing controller 20 are tenderly contained in the same weaving device. In the circuit (Seaie (10), the clock generator 14 generates the work frequency of the integrated circuit. In another embodiment shown in FIG. b, the image micro device, the capture unit u, the image woven unit 12, In the integrated circuit of the scaling device, the clock generator 14 generates the operating frequency of the integrated circuit, and the timing controller 20 is placed on the scale device. Outside the circuit, for example, in another integrated circuit. For the preferred embodiment of the present invention, equivalent modifications or variations made by persons skilled in the art in the spirit of the present invention are included in the scope of the patent application. [Simplified Schematic] The block diagram of a conventional image system; the second diagram is a block diagram of another conventional image system; the second diagram is a schematic diagram of an LCD display; the fourth diagram is a block diagram of the image zooming apparatus of the present invention; Figure is a block diagram of an image scaling unit of the image scaling device of the present invention; 11 200847125 Figure 6A is a schematic diagram showing the components of the image scaling device of the present invention disposed in the same integrated circuit; and the sixth B is the present invention A schematic diagram of each component of the image scaling device disposed in different integrated circuits. [Description of component symbols] Image scaling device 10, 10, 10", image scaling device 100 Receiver 102 Image scaling unit 104, 12 Transmitter 106 image Capture unit 11 clock generator 110, 14 oscillator 114 frame frequency converter 13 timing controller 20 time base converter 31 0 Interpolator 320 Data Path Control Block 330 SCLK Clock Generator 340 DCLK Clock Generator 350 Input Data Synchronizer 410 Line Buffer 420, 620 First In First Out 430, 630 Control Logic 440, 640 Interpolator Line Buffers 510, 710 vertical interpolators 520, 720 horizontal interpolators 530, 730 12