JPH0627932A - Frame memory controller - Google Patents

Abstract

PURPOSE:To give a margin to the processing contents on a device side where image data are written in a frame without any hindrance to the transfer of the image data from the frame memory to a display device side by providing an interleaving control means and a timing control means. CONSTITUTION:Parallel writing to and serial reading from the frame memory 3 are performed in synchronism with a horizontal synchronizing signal (HSYNC#). Then interleaving control which switches memory banks at intervals of one horizontal line is performed to transfer the line image data from the memory 3 to a display side during a period consisting of both the horizontal scan blanking period of the display device 5 and the following line display section. The transferred image data are displayed on a display while delayed by one horizontal scanning period at each time. Consequently, the restrictions on the timing at the time of the transfer of the image data from the memory 3 to the display side are relaxed to surely transfer the line image data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame memory control device for transferring image data written in a frame memory in a bit map system to a CRT display device of a raster scan system for display.

[0002]

2. Description of the Related Art In a conventional device of this type, as shown in FIG. 5, (a) the frame memory 3 is divided into a plurality of logically independent memory banks A, B and C, and (b) ) The display screen 51 of the CRT display device is virtually divided into display sections # 0, # 1 and # 2 by the number of horizontal scanning lines, and (c) image data displayed in the display section # 0 is displayed in the bank A. The image data displayed in the display section # 1 is written in the bank B, and the image data displayed in the display section # 2 is written in the bank C.

The frame memory 3 is constructed by using a dual port DRAM (memory that can be written at any time) having two types of ports, parallel and serial. In this frame memory 3, image data written in parallel from the parallel port side by one bit in a bit map method
One line is read out serially from the serial port every horizontal scanning line period and transferred to the display device side (for example, JP-A-63-240).
620).

[0004]

However, according to such a configuration, there is a problem that processing contents on the device side for writing data into the frame memory are greatly restricted.

The above problem occurs for the following reasons. That is, in the case where a processing device that writes image data in the frame memory 3 handles a large amount of image data that covers the entire display screen 51, or when arbitrarily performing enlargement, reduction, rotation, movement, composition, etc., The writing of image data to the frame memory needs to proceed simultaneously to all memory banks.

Therefore, in the prior art, as shown in FIG. 4, parallel writing and serial reading with respect to the frame memory are separated in synchronization with the horizontal synchronizing signal (HSYNC #), and the horizontal scanning retrace line section (BLAN) of the display device is separated.
K #), the image data for one line is serially transferred to the display device side, and while the image data for one line transferred serially is displayed on the display device, it is transferred to an arbitrary bank of the frame memory. I was trying to write.

However, in this case, on the writing side, the time during which continuous access to the frame memory is possible is restricted by the horizontal synchronization period, and on the reading side, the timing is restricted only to the horizontal scanning blanking interval, and eventually both of them are It is forced to operate under extremely strict timing conditions.

In other words, since the writing side device can only perform a process in which one access is always completed within one horizontal scanning period, the contents of the process are restricted, and a large amount of data, for example, covering the entire screen is generated. It becomes difficult to smoothly perform the processing that handles the image data of. Further, since the reading side is given only a limited timing of only the horizontal scanning blanking interval, if the writing side access may be prolonged, the transfer of image data to the display device side may occur. Cannot be performed, and display noise appears on the display screen.

The present invention has been made in view of the above-mentioned problems, and the processing contents on the device side for writing to the frame memory can be improved without hindering the transfer of image data from the frame memory to the display device side. An object of the present invention is to provide a frame memory control device capable of providing a margin.

[0010]

In order to solve the above-mentioned problems, the present invention provides a frame memory so that the image data is transferred from the frame memory to the display side by switching the memory bank for each horizontal line. While logically dividing into a plurality of memory banks, transfer of line image data from the frame memory is performed in a period spanning both the horizontal scanning retrace line section and the subsequent line display section,
It is equipped with the configuration.

[0011]

According to the present invention, with the above-mentioned configuration, the timing constraint when transferring the image data from the frame memory to the display side is greatly relaxed, and the transfer of the line image data from the frame memory to the display side is ensured. In addition to the above, since the device side that writes to the frame memory can also greatly relax the time constraint when accessing the frame memory,
It is possible to cause the device on the writing side to perform high-level processing without causing any trouble in the display on the display device on the reading side of the frame memory.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts. FIG. 1 shows a schematic configuration of a frame memory control apparatus according to an embodiment of the present invention, in which 1 is an image memory for accumulating an unprocessed input image, and 2 is an image memory.
Is a display controller for processing image data, 3
Is a frame memory that stores image data in a bitmap format, and 4 is 1 from the serial port side of the frame memory 3.
A video signal conversion / transfer unit 5 for converting the image data transferred serially line by line into a video signal and outputting the video signal. Reference numeral 5 is a bit map type CRT display for displaying the video signal transferred from the video signal conversion transfer unit 4. Device, 6
Is a frame memory control device for controlling the operation of the frame memory 3 and its surroundings.

The frame memory 3 is constructed by using a dual port DRAM (memory that can be written at any time) having two types of ports, parallel and serial.

The frame memory controller 6 logically divides the frame memory 3 into a plurality of memory banks so that the image data is transferred from the frame memory 3 to the display side by switching the memory banks for each horizontal line. And the timing control means for transferring the line image data from the frame memory 3 within a period extending over both the horizontal scanning blanking interval and the subsequent line display interval.

FIG. 2 shows the correspondence between the frame memory and the display screen. The correspondence shown in the figure is logically constructed by the control of the frame memory control device 6.

In the figure, (a) the frame memory 3
Is logically divided into three memory banks A, B and C, and each memory bank A, B and C is logically divided into two blocks L and H, respectively.

(B) The display screen 51 of the CRT display device 5 is virtually divided into three display sections # 0, # 1 and # 2 according to the number of horizontal scanning lines.

(C) The image data displayed in the display section # 0 of the display screen 51 is alternately stored and stored in the banks AL and BH of the frame memory 3 line by line. Similarly, the display image data of the section # 1 is stored in the banks CL and AH, and the display image data of the section # 2 is stored in the banks BL and CH.
, And are alternately allocated to each line and stored.

FIG. 3 shows the above correspondence for each horizontal scanning line of the display device. As shown in the figure, the transfer of image data from the frame memory 3 to the display side is performed by switching the memory bank for each horizontal line by interleave control.

The operation of the frame memory control device configured as described above will be described below.

In the above-mentioned device, as shown in FIG. 4, first, parallel writing and serial reading to the frame memory 3 are performed in synchronization with the horizontal synchronizing signal (HSYNC #). Under this synchronization, the interleave control that switches the memory bank of the transfer source for each horizontal line is performed to transfer the line image data (n, n + 1, ...) From the frame memory 3 to the display side. Device 5
The horizontal scanning retrace line section and the line display section after that are performed during the period. Each of the transferred line image data is displayed on the display with a delay of one horizontal scanning period (n-1, n, n + 1, ...
・).

As a result, the timing constraint when transferring the image data from the frame memory 3 to the display side is greatly alleviated, and the transfer of the line image data from the frame memory 3 to the display side can be ensured. Will be able to. At the same time, on the side of the display control device 2 that writes data to the frame memory 3, the time constraint when accessing the frame memory 3 is greatly relaxed. For example, in the horizontal scanning blanking interval. It is also possible to perform image processing in which the frame memory 3 is accessed with a shift. As a result, it is possible to cause the display control device 2 on the writing side to perform high-level processing without hindering the display on the display device 5 on the reading side of the frame memory 3.

[0024]

As is apparent from the above description, according to the present invention, a plurality of frame memories are provided so that the image data is transferred from the frame memory to the display side by switching the memory bank for each horizontal line. It is logically divided into memory banks and the transfer of line image data from the frame memory is performed within a period that spans both the horizontal scanning retrace line section and the subsequent line display section, so The restriction on the timing when transferring the image data to the frame memory is greatly relaxed, the transfer of the line image data from the frame memory to the display side can be surely performed, and the device side that writes to the frame memory is However, the time constraint for accessing the frame memory is greatly relaxed, so Without disturbing the display on the display device is a read side of Mumemori, it becomes possible to perform sophisticated processing apparatus to be the writing side, and has the effect that.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a system using a frame memory control device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a correspondence relationship between a frame memory and a display screen.

FIG. 3 is a diagram showing, for each line, a correspondence relationship between a frame memory and a display screen.

FIG. 4 is a diagram showing write / read timing conditions of the frame memory according to the present invention.

FIG. 5 is a diagram showing a conventional correspondence relationship between a frame memory and a display screen.

FIG. 6 is a diagram showing timing conditions for writing / reading of a conventional frame memory.

[Explanation of reference numerals] 1 input image memory 2 display control device (writing side) 3 frame memory 4 video signal conversion transfer unit 5 CRT display device 6 frame memory control device

Claims (1)

[Claims] 1. An interleave control means for logically dividing the frame memory into a plurality of memory banks so that image data is transferred from the frame memory to the display side by switching the memory bank for each horizontal line. A frame memory control device having timing control means for causing the transfer of the line image data from the device during the horizontal scanning blanking interval and the subsequent line display interval.