JPH06161883A - Image memory device - Google Patents

Abstract

PURPOSE:To provide the image memory device which can execute local processing or raster scan at high speed by removing the demerit of making the configuration of the image memory device huge corresponding to color image signals. CONSTITUTION:This device is provided with a first memory 109 for storing digital image data composed of one luminance signal and two color difference signals, second memory 110 for storing image data by using a control signal independent of the first memory 109 and a data bus, and memory control part 103 for controlling the first and second memories 109 and 110 so that data for two arbitrarily continuous lines can be stored in the first memory 109 or the second memory 110, data for two continuous lines adjacent to the two lines can be stored in the other memory concerning the luminance signal, and data for one arbitrary line can be stored in the memory other than the first or second memory for storing the luminance signal corresponding to an image position concerning the color difference signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory device in a color image processing device.

[0002]

2. Description of the Related Art Generally, since an image memory used in an image processing apparatus is required to have a large capacity and a low cost, a DRAM (dynamic random access memory) which is a low speed device is used. Therefore, it is necessary to devise the configuration of the memory device to increase the speed in order to compensate for the drawback that the memory device is slow.

One method for achieving this speedup is disclosed, for example, in Japanese Patent Laid-Open No. 01-263776. According to this document, two data buses are provided to store image data in which one pixel is represented by n-bit data.
By preparing a memory having n lines and storing data of two adjacent pixels at one time, the apparent speed of the memory is doubled to achieve high speed. Therefore, for example, for a monochrome image in which one pixel is represented by 8 bits, a memory having a data bus with a data width of 16 bits is prepared, and one pixel is R (red), G (green), B ( A memory having a data bus having a data width of 48 bits may be prepared for a color image represented by 8 bits of (blue).

[0004]

However, it is difficult to realize an effective image memory device depending on the format of the image signal to be handled in the device having the above-mentioned configuration. For example, "4: 2: 2 digital component television signal" generally known in the field of image coding is a digital image signal defined in CCIR Recommendation 601, and the sampling frequency of the signal and per line The number of effective pixels is luminance signal Y: 13.5 MHz and 720 pixels / line, color difference signals Cb and Cr: 6.75 MHz and 360 pixels / line, and the number of quantization bits is 8 bits / pixel for both Y, Cb, and Cr. is there. Therefore, according to the 4: 2: 2 format signal, the luminance signal 2 pixels correspond to the color difference signals Cb and Cr 1 pixel.

Similarly, CCITT Recommendation H.264, which is also known as an image coding system for communication, is used. The image format handled by the H.261 is called 4: 2: 0 format signal (or 4: 1: 1 format signal), and the color difference signal C
4 pixels of luminance signal correspond to 1 pixel of b and Cr. That is, in a color image signal in the 4: 2: 2 format or the 4: 2: 0 format, the number of pixels forming the image is Y,
Since the signals of Cb and Cr are different for each signal, the conventional device having the above configuration must be provided for each signal, resulting in a problem that the amount of hardware of the image memory device becomes huge.

The present invention eliminates the disadvantage that the configuration of the image memory device becomes huge for color image signals in the 4: 2: 2 format and the 4: 2: 0 format described above, and further performs local processing and rasterization. An object of the present invention is to provide an image memory device capable of executing scanning at high speed.

[0007]

In order to solve the above-mentioned problems, the present invention stores the image data in an image memory device for storing digital image data consisting of one luminance signal and two color difference signals. A first memory,
A second memory that stores the image data using a control signal and a data bus that are independent of the first memory, and two consecutive lines of data for the luminance signal are stored in the first memory or the first memory. Stored in either one of the second memories,
Data of continuous two lines adjacent to the two lines is stored in the other memory, and data of any one line for the color difference signal is stored in the first or second luminance signal corresponding to the image position. And a memory control unit for controlling the first and second memories so as to be stored in the other memory.

[0008]

In the image memory device having the above structure,
For a color image signal in a 2: 2 format or a 4: 2: 0 format, a memory for storing luminance signals for every two consecutive lines is selected, and for a color difference signal, the other of the memories storing the corresponding luminance signals is selected. Since the image memory is configured to store data in the memory, it is possible to read and write arbitrary line data and neighboring line data at the same time regardless of whether it is a luminance signal or color difference signal, and local processing and raster scanning can be executed at high speed. Is. Further, unlike the conventional device, the luminance signal and the color difference signal are not stored in separate memory devices, so that the number of memory devices and the number of bus lines can be significantly reduced, and the device configuration can be kept small. The above problems can be solved.

[0009]

1 is a block diagram showing an embodiment of an image memory device according to the present invention, in which 101 is an instruction signal input to the image memory device and 102 is an image signal read / written by the image memory device. , 103 are instruction signals 101
Based on the memory address 104 and the two memory control signals 106 and 108, and further outputs two image signals 105 and 107 based on the input image signal 102, or two input image signals. 105 and 1
A memory control unit for outputting the image signal 102 based on 07, 109 is a memory address 104 and a memory control signal 1
The first memory 110 which reads / writes the image signal 105 based on 06 and further outputs the raster scanning signal 111, reads / writes the image signal 107 based on the memory address 104 and the memory control signal 108, and further reads the raster scanning signal. The second memory outputs 111.

In this embodiment, the first memory 1
09 and the second memory 110 are both DPRAM (dual port random access memory)
Section and SAM section. The RAM part has a ROW address (row address) represented by B bits (B is a positive integer)
Is a memory having an address space composed of a COLUMN address (column address) represented by B bits, and operates similarly to a DRAM. SAM part is 2 ^B
A memory for storing individual data, the data being RA
Input and output are performed one by one, independently and asynchronously with the access to the M section. The 2 ^B pieces of data corresponding to an arbitrary row address of the RAM portion can be simultaneously transferred to the SAM section, also be simultaneously transferring 2 ^B pieces of data of the SAM unit to any of the row address of the RAM portion it can. In this embodiment, B = 9.

Further, in this embodiment, a 4: 2: 0 format signal is used as an example of the target image data, and the size thereof is a luminance image (Y image) 352 pixels × 28.
8 pixels, color difference signal (Cb image) 176 × 144 pixels, and color difference signal (Cr image) 176 pixels × 144 pixels.

FIG. 2 is a diagram showing the correspondence between the actual image and the first memory 109 and the second memory 110 in this embodiment. Hereinafter, the operation of the image memory device according to the present embodiment will be described in detail with reference to FIGS.

[Image Data Writing Operation] When writing image data, first, the position (x, y) on the image and the identification data of the Y image / Cb / Cr image and the data writing command are used as the instruction signal 101. It is given from the outside and input to the memory control unit 103.

The memory control unit 103 uses the instruction signal 101.
The memory address 104 is calculated based on the correspondence between the real image and the memory shown in FIG. That is, according to FIG. 2, the memory for storing every two consecutive lines of the Y image 204 is divided into the first memory 201 and the second memory 202, and C
For the b image 205 and the Cr image 206, the memory for storing each line is the first memory 201 and the second memory 2.
Divide into 02. At this time, the Y image and the Cb and Cr images are separated from each other in the memory storing the corresponding image data. For example, the line Y _{3 of the} Y image and the lines Cb ₁ and C of the Cb image
The line Cr _{1 of the} r image corresponds to the same image position, but Y ₃ is stored in the second memory 202, and Cb ₁ and Cr ₁ are stored in the first image.
In the memory 201 of each. Also, the Cb image 20
5 line data Cb _n (n = 0, 1, 2, ... 14
3) and the line data Cr _n of the Cr image 206 is 20 in the figure.
In the form of an array of pixel data alternately as shown in 3 (figure C _n and expressions) stored in the first memory 201 or second memory 202.

The memory control unit 103 calculates a row address and a column address commonly used by the first memory 109 and the second memory 110 based on the rules described above, and outputs them as the memory address 104. Further, the memory control unit 103 creates memory control signals 106 and 108 including a RAS (row address strobe) signal, a CAS (column address strobe) signal, a WE (write enable) signal, and the like, and respectively generates the first memory control signals 106 and 108.
To the memory 109 and the second memory 110. Further, the memory control unit 103 divides the input image signal 102 into image signals 105 and 107, and supplies each signal to the first memory 109 and the second memory 110.

Next, the first memory 109 outputs the image signal 1 based on the memory address 104 and the memory control signal 106.
05, and the second memory 110 stores the memory address 1
04, the image signal 107 based on the memory control signal 108
Memorize At this time, since the memory addresses 104 given to the two memories are common, the two pixel data separated by two pixels in the vertical direction in the Y image and the vertical direction in the Cb / Cr image by the correspondence shown in FIG. Two adjacent pixel data are stored respectively. Therefore, the data of two neighboring pixels can be stored at the same time, and as a result, the image data of the local area can be written into the memory at high speed. At this time, if the data is written in the image memory while incrementing (or decrementing) the x-coordinate value on the image, a high-speed access mode (eg, high-speed page mode or static column mode) generally used in DPRAM or DRAM. ) Can be used to store image data at a higher speed.

[Image Data Read Operation] In executing the image data read operation, first, the position (x, y) on the Y image and the identification data of the Y image / Cb / Cr image and the data read command are instructed. The signal 101 is given from the outside and input to the memory control unit 103.

The memory control unit 103 uses the instruction signal 101.
Based on the above, in the same way as when writing image data,
Memory address 104, memory control signals 106 and 10
8 is output.

The first memory 109 has a memory address of 10
4. The image signal 105 is read out based on the memory control signal 106, and the second memory 110 stores the memory address 10
4. Read out the image signal 107 based on the memory control unit 108.

The memory control unit 103 uses the image signal 105.
And 107 are output to the outside in the form of the output image signal 102. At this time, since the memory addresses 104 given to the two memories are common, two pixel data separated by two pixels in the vertical direction are read out in the Y image according to the correspondence shown in FIG. 2, and in the Cb / Cr image. Two pixel data that are vertically adjacent to each other are read out. Therefore, the data of two neighboring pixels can be read at the same time, and as a result, the image data of the local area can be read from the memory at high speed. still.
As in the case of writing image data, DPRAM or D
The high-speed access mode of the RAM makes it possible to speed up the reading of data.

[Read Operation of Raster Scan Data] In executing the read of the raster scan data, when a data read command is externally input to the memory control unit 103 as an instruction signal 101, the memory control unit 103 causes (x, y) = (0,0) and the memory address 104 and the memory control signal 1 for the Y image along the correspondence of FIG.
06 and 108 are output. As a result, the first memory 1
The line data Y ₀ of the RAM section corresponding to the row address (= 0) of 09 is transferred to the SAM section. Next, the memory control unit 103 switches the target image from the Y image to the Cb / Cr image, and outputs the memory address 104 and the memory control signals 106 and 108 according to the correspondence of FIG. As a result, the line data C ₀ (= Cb ₀ and Cr) of the RAM section corresponding to the row address (= 144) of the second memory 110.
₀ ) is transferred to the SAM section.

Next, the memory control unit 103 operates the first memory 1
09 and the second memory 110, the read enable signal of the SAM unit is output. However, the read enable signal is the memory control signals 106 and 108.
It is a control line dedicated to the SAM unit included in. By inputting the read enable signal to the first memory 109 and the second memory 110, the S of the two memories is S.
The raster scan signal 111 corresponding to y = 0 by the AM unit
(Y ₀ , Cb ₀ , Cr ₀ ) is output.

Hereinafter, the values of (x, y) set by the memory control unit 103 are (0, 1), (0, 2), (0, 3).
The SAM of the two memories is repeated by repeating the above-mentioned processing while changing it to (0, 287).
From the section (Y ₁ , Cb ₀ , Cr ₀ ), (Y ₂ , Cb ₁ , C
r ₁ ), (Y ₃ , Cb ₂ , Cr ₂ ), ..., (Y ₂₈₇ , C
The raster scan signal 111 for one frame is output like b ₁₄₃ , Cr ₁₄₃ ). Therefore, since the data in the image memory can be output in accordance with the raster scanning, the data can be output to an image output device such as a CRT or the Y / Cb / Cr image can be output as an R image.
This is effective when converting to a / G / B image. Further, if the SAM units of the two memories are not used as the image data output unit as in the present embodiment, but the SAM units are used as the image data input unit, the data is input from the image input device such as a TV camera. It is effective when inputting.

In this embodiment, the case where the first memory and the second memory are composed of DPRAM has been described. However, DRAM or SRAM (Static Random Access Memory) is used according to the specifications required of the image processing apparatus. You may apply. For example, when it is not necessary to access the SAM part of DPRAM, DRA is used instead of DPRAM.
M may be used. Further, the SRAM may be applied when the size of the target image is small to some extent or when it is necessary to further increase the speed of the image memory device.

In the present embodiment, the explanation has been made for the 4: 2: 0 format signal, but the present invention can be applied to the 4: 2: 2 format signal. FIG. 3 shows an example of correspondence between the actual image and the first and second memories in this case. As shown in FIG. 3, a Y image 404 of 352 × 288 pixels and a Cb image 405 of 176 × 288 pixels.
For the image data in the 4: 2: 2 format including the Cr image 406 and the Cr image 406, for example, by configuring the memory control unit so as to associate the first and second memories with each other as indicated by 401 and 402 in the figure. The same effect as this embodiment can be obtained. In this example, the arrangement of the color difference signals on the same row address is shown in FIG.
As in 03, the Cb signal and the Cr signal are alternately arranged.

In this embodiment, the first and second memories have been described as storing one frame of image data, but the two memories are configured to store a plurality of frames of image data. May be. That is, if each of the first memory and the second memory is divided into a plurality of address spaces and the image data for one frame is stored in each address space by the same method as in this embodiment, It is possible to realize an image memory device having the same effect as that of the present embodiment and capable of storing image data of a plurality of frames. In this case, it is possible to provide an effective image memory for an image processing device that requires calculation between each frame, for example, a moving image encoding device.

FIG. 4 shows an example of correspondence between the actual image and the first and second memories when storing image data for two frames. As shown in FIG. 4, a Y image of 352 × 288 pixels and 1
Two image data A in a 4: 2: 0 format composed of a Cb image and a Cr image of 76 × 144 pixels (5 in the figure
04, 505, 506), image data B (507 in the figure,
508, 509), for example, by configuring the memory control unit so that the first and second memories are associated with each other as indicated by 501 and 502 in the figure, the same effect as this embodiment can be obtained. . In this example, as in the present embodiment, the arrangement of the color difference signals on the same row address is alternately arranged for the Cb signal and the Cr signal as indicated by 503 in the figure.

In the present embodiment, as the size of the target image, the operation was explained for the Y image of 352 × 288 pixels and the Cb image and Cr image of 176 × 144 pixels, but it corresponds to one pixel on the color difference image. If the size of the pixel on the luminance image is 2 or 4 pixels, the image memory device according to the present invention can be applied to obtain the same effect as that of the present embodiment even if the size of the image is arbitrarily set. You can

[0029]

As described in detail above, according to the present invention, a luminance signal is stored every two consecutive lines for a color image signal in a 4: 2: 2 format or a 4: 2: 0 format. The image memory is configured to store the data in the other memory of the memory that stores the corresponding luminance signal for the color difference signal, so it is possible to select any line data for both the luminance signal and the color difference signal. Since it is possible to simultaneously read and write the line data and its neighboring line data, it is possible to quickly read and write the image data necessary for various local processes used in the image processing apparatus such as image conversion, filter processing, and motion detection. Further, since the luminance signal and the color difference signal corresponding to the luminance signal are stored in different memories, the luminance signal and the color difference signal can be read and written at the same time. Therefore, it is possible to realize an image memory device having high compatibility with a raster scanning signal output from an image input device such as a TV camera or a raster scanning signal input to an image output device such as a CRT. Further, since the luminance signal and the color difference signal are not stored in separate memory devices as in the conventional device, the number of memory devices and the number of bus lines can be significantly reduced, and the device configuration can be kept small.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an image memory device of the present invention.

FIG. 2 is a correspondence diagram between an actual image and first and second memories in the embodiment.

FIG. 3 is a correspondence diagram between a real image and a first and second memory for a 4: 2: 2 format signal.

FIG. 4 is a diagram showing an actual image and a first image for two frames of image data.
FIG. 7 is a correspondence diagram with a second memory.

[Explanation of symbols]

 101 instruction signal 102 image signal 103 memory control unit 109 first memory 110 second memory 111 raster scan signal

Claims (1)

[Claims] 1. An image memory device for storing digital image data composed of one luminance signal and two color difference signals, wherein a first memory for storing the image data and a control independent of the first memory A second memory for storing the image data by using a signal and a data bus; and for the luminance signal, data for two consecutive arbitrary lines is stored in either the first memory or the second memory. Then, the data of two consecutive lines adjacent to the two lines is stored in the other memory, and the data of any one line for the color difference signal is stored in the first or the first luminance data corresponding to the image position. An image memory device, comprising: a memory control unit that controls the first and second memories so as to be stored in the other memory of the two memories.