JP3123225B2 - Data sorting device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to sharing a circuit for NTSC and PAL signals in a data rearranging apparatus used for recording or transmitting image information with high efficiency coding. .

[0002]

2. Description of the Related Art Since image data has a very large data amount, when transmitting or recording, high-efficiency coding is often used to reduce the data amount. High-efficiency coding is a means for removing redundant components of image information and compressing the data amount. As the high-efficiency coding, there is a method in which an input sample value is first divided into blocks each including a plurality of adjacent pixels, and each block is orthogonally transformed, and is encoded for each orthogonal transformation. When encoding is performed in such a block unit, it is necessary to first rearrange input image data in the order of blocks suitable for encoding. In particular, it is also important to rearrange the data in units of blocks in order to improve the efficiency of high-efficiency coding and to disperse the effects of errors.

Here, an example will be described in which two fields of TV signals are collected to form one page, and one block is formed in units of two fields.

A signal of one screen is composed of a normal luminance signal Y and color difference signals Cr and Cb. The luminance signal is 858 horizontal pixels and 525 vertical pixels in the NTSC system, and 864 horizontal pixels and 625 vertical pixels in the PAL system. . Normally, when compressing a video signal, first, the signal rate of the color difference signal is reduced by half.
Then, the data is rearranged, DCT or the like is transformed, and compression is performed. When thinning this signal rate by half,
In the NTSC system, the data is thinned out horizontally and in the PAL system, the data is thinned out vertically.
FIG. 4 shows the thinned signal rates. The number of effective pixels and the number of effective lines in one field are as shown in (Table 1).

[0005]

[Table 1]

Next, a description will be given of an example of a data rearranging apparatus for performing signal blocking at the above two types of signal rates. FIG. 9 is a diagram showing an example of a conventional data rearranging apparatus. In FIG. 9, 1 is a horizontal thinning filter for Cr, 2 is a horizontal thinning filter for Cb, and 3 is a vertical thinning filter for Cr. 4 is a vertical thinning filter for Cb, 5 is a thinning filter output switching SW, 6 is a FIFO for luminance signal Y, and 7 is a color difference signal C.
8 is a color difference signal Cb FIFO, 9 is a color difference signal FIFO, 10 is a data switch SW, 11 is an image memory, 12 is an NTSC horizontal write address generation circuit, Reference numeral 13 denotes a PAL horizontal write address generation circuit, 14 denotes an NTSC horizontal read address generation circuit, 15 denotes a PAL horizontal read address circuit, 16 denotes a horizontal write address switch SW, and 17 denotes a horizontal read address switch SW. It is.

A luminance signal Y and a color difference signal C are input signals.
r and Cb are input, and in the case of the NTSC system, the color difference signal is band-limited in the horizontal direction through a horizontal thinning filter, and
Decrease to / 2. In the case of the PAL system, the color difference signal is vertically band-limited through a vertical thinning filter, and is thinned to 1/2. Therefore, in the case of the PAL system, each line has a Cr
Only the signal or the Cb signal is output, and the output data is switched by the switch SW5. The transfer rates of the four kinds of data of the luminance signal Y, the color difference signals Cr and Cb of the NTSC system, and the color difference signal of the PAL system are converted by the FIFOs 6, 7, 8, and 9, respectively.
Each FI according to the mode and the writing procedure of the image memory 11
The parallel data of the luminance signal and the color difference signal is switched by the FO output switch SW10 and converted into serial data.
The converted data is switched between the address output from the NTSC horizontal write address generator 12 and the address output from the PAL horizontal write address generator 13 by the horizontal write address switch SW16 according to the mode, and is stored in the image memory 11 according to the output address. Is stored. The stored data is switched by a horizontal read address switch SW17 according to the mode between the address output from the horizontal read address generator 14 for NTSC and the address output from the horizontal read address generator 15 for PAL after a predetermined time.
The data is read from the image memory 11 according to the output address and output.

[0008]

However, in the above-mentioned conventional configuration, there are two types of address generation circuits for writing two types of signals, NTSC and PAL, into the image memory, and an address generation circuit for reading out the two types of signals. A separate control circuit is required for each of the two types and four types of FIFOs for converting the data transfer rate, so that the number of control circuits increases.

The present invention relates to such a conventional NTSC, PA
An object is to solve the problem that the number of control circuits corresponding to the two types of the L system increases.

[0010]

According to the present invention, in order to solve the above-mentioned problems, when one field or a plurality of fields is one page, input moving image data is recorded in an image memory for each page. A horizontal thinning filter that limits the horizontal band of the color difference signal and further thins out data in the horizontal direction when the input signal is an NTSC signal, When the signal is a signal of the PAL system, the vertical band of the color difference signal is limited, and a vertical thinning circuit for thinning out data in the vertical direction, a SW for switching thinned data, and input Y, Cr, and Cb signals are respectively provided. FIFO for luminance signal Y, NT for converting input data rate to data rate to be input to image memory to transfer signals serially
FIFO2 for Cr and Cb of color difference signal shared by SC and PAL
A switch for switching the type and output data of each FIFO is provided.
Address generating circuit for writing NTSC data to image memory for one page and image memory for one page, address generating circuit for writing PAL data, and generating address for horizontal reading for both NTSC and PAL systems And a circuit for rearranging the data.

[0011]

According to the present invention, the FIFO for the color difference signal can be partially shared between the NTSC system and the PAL system, and the FIFO for converting the transfer rate for two types of signals can be used.
By specifying the reading of O and the address to be written in the image memory in each system and storing them, the reading address can be shared by the NTSC system and the PAL system, especially in the horizontal direction, and can be basically used in the vertical direction. The common processing can be shared and the number of handles can be different, and the circuit scale can be reduced.

[0012]

An embodiment of the present invention will be described below. FIG. 1 is a block diagram showing a first embodiment of the present invention. In FIG. 1, 1 is a horizontal thinning filter for Cr, and 2 is Cb
3 is a vertical thinning filter for Cr, 4 is a vertical thinning filter for Cb, 16 is a thinning filter output switch SW, and 6 is a luminance signal Y.
7 is a color difference signal Cr FIFO, 8 is a color difference signal Cb FIFO, 17 is a data switching SW, 11 is an image memory, and 12 is NTSC.
Reference numeral 13 denotes a horizontal write address generation circuit for PAL, reference numeral 18 denotes a horizontal read address generation circuit, and reference numeral 19 denotes an address switching SW.

Next, the operation of the block diagram of FIG. 1 will be specifically described. As input signals, a luminance signal Y and color difference signals Cr, C
b, and in the case of the NTSC system, the color difference signal passes through each of the horizontal thinning filters 1 and 2 to limit the band in the horizontal direction.
It is thinned out by half. In the case of the PAL method, the color difference signal passes through each of the vertical thinning filters 3 and 4 to perform band limitation in the vertical direction, and is thinned to 1/2. Therefore, in the case of the PAL system, only the Cr signal or the Cb signal is output for each line. FIG. 4 shows the signal rate of one field. Switching output data from each of the decimation filters 1, 2, 3, and 4 S
Switching is performed at W16, and a luminance signal Y and color difference signals Cr and Cb are output. The output data of the three types of data, the luminance signal Y and the color difference signals Cr and Cb, are converted by the FIFOs 6, 7, and 8, and are switched according to the mode and the write procedure.
The parallel data of the luminance signal Y and the color difference signals Cr and Cb are switched to each other at 7 and converted into serial data. FIG. 5 shows the signal rate input to the image memory 11. The signal rate of the output signal from the memory for blocking is as shown in FIG. 6. Since the signal rate is in units of 8 pixels, data input to the image memory 11 is handled in units of 8 pixels. The converted data is switched by the horizontal write address switch SW19 according to the mode between the address output from the NTSC horizontal write address generation circuit 12 and the address output from the PAL horizontal write address generation circuit 13, and the image memory is operated according to the output address. 11 is stored. The stored data is read out from the image memory 11 according to the address output from the horizontal read address generation circuit 18 after a predetermined time. FIGS. 7 and 8 show a memory map of each system.

FIG. 2 is a block diagram showing a second embodiment of the present invention. In FIG. 2, 21 is a horizontal interpolation filter for Cr, 22 is a horizontal interpolation filter for Cb,
23 is a vertical interpolation filter for Cr, 24 is a vertical interpolation filter for Cb, 20 is a switch for switching the output of the interpolation filter, 6 is a FIFO for luminance signal Y, and 7 is a FIFO for color difference signal Cr. , 8 are F for the color difference signal Cb
IFO, 11 is an image memory, 25 is NTS
26 is a horizontal read address generation circuit for C, and 26 is PAL.
A horizontal read address generating circuit; 18, a horizontal write address generating circuit; and 27, a horizontal read address switch SW.

Next, the operation of the block diagram of FIG. 2 will be specifically described. As input signals, a luminance signal Y and color difference signals Cr, C
When the serial data b is input to the image memory 11, the address output from the horizontal write address generation circuit 18 is switched by the SW 27 and the image is written to the image memory 11 in accordance with the address. The read from the image memory 11 is performed by the NTSC system. In the case of the PAL system, the reading is performed in accordance with the address from the horizontal read address generating circuit 25 for NTSC, and in the case of the PAL system, the processing is performed in accordance with the address from the horizontal reading address generating circuit 26 for PAL. , 7, and 8 are separately input to the luminance signal Y and the color difference signals Cr and Cb, and the transfer rates are converted. The color difference signals Cr and Cb signals are NTS
In the case of the C system, data interpolation is performed by the horizontal interpolation filters 21 and 22. In the PAL method, horizontal interpolation filters 23 and 24 are used.
Perform interpolation with. The luminance signal Y is directly input to the switch SW20. Output data from each of the interpolation filters 21, 22, 23, and 24 is input to the switch SW20, and is switched according to the mode and output.

FIG. 3 is a block diagram showing a third embodiment of the present invention. In FIG. 3, 1 is a horizontal thinning filter for Cr, 2 is a horizontal thinning filter for Cb, 3 is a vertical thinning filter for Cr, 4 is a vertical thinning filter for Cb, and 21 is a vertical thinning filter for Cb. This is a horizontal interpolation filter for Cr.
Reference numeral 22 denotes a horizontal interpolation filter for Cb, reference numeral 23 denotes a vertical interpolation filter for Cr, reference numeral 24 denotes a vertical interpolation filter for Cb, reference numeral 6 denotes a FIFO for a luminance signal Y, reference numeral 7 denotes a FIFO for a color difference signal Cr, 8 is a FIFO for the color difference signal Cb
Reference numeral 11 denotes an image memory, reference numeral 30 denotes a switch for switching between input data and output data, and reference numeral 31 denotes three types of FIFOs 6, 7, 8 and each of the thinning filters 1, 2, 3, and 3.
4 and the data flow of each interpolation filter 21, 22, 23, 24 is switched.
, And 32 is a SW for switching the FIFOs 6,
SWs for switching the flow of data between the memory 7 and 8 and the image memory 11 and for switching the data of each FIFO, 33 are switches for switching the input and output of the image memory 11, and 34 are NTSC in the recording mode ( When image data is input and blocked and output from the image memory), a horizontal write address for NTSC is generated, and in the reproduction mode (blocked image data is input to the image memory and one page of data is output). 35) a circuit for generating a horizontal read address for NTSC, a circuit 35 for generating a horizontal write address for PAL in the PAL in the recording mode, and a horizontal read address for PAL in the reproduction mode. A circuit 18 generates a horizontal read address in the recording mode, and generates a horizontal write address in the reproduction mode.

Next, the operation of the block diagram of FIG. 3 will be specifically described. In the recording mode, the SW 30 is in the input mode, and receives the luminance signal Y and the chrominance signals Cr and Cb as input signals. In the case of the NTSC system, the chrominance signals Cr and Cb pass through the horizontal thinning filters 1 and 2 in the horizontal direction. , And limit the bandwidth to 1/2. In the case of the PAL system, the color difference signal passes through the vertical thinning filters 3 and 4 to limit the band in the vertical direction, and thins out to 1/2. Therefore, in the case of the PAL system, only the Cr signal or the Cb signal is output for each line. The output data from each of the thinning filters 1, 2, 3, and 4 is switched by the switch SW31, and the luminance signal Y and the color difference signals Cr, Cb
Is output. Output luminance signal Y, color difference signals Cr, C
The transfer rates of the three types of data b are converted by the FIFOs 6, 7, and 8, and are switched according to the mode and the write procedure.
The luminance signal Y and the color difference signals Cr and Cb are switched by W32.
Is converted into serial data, and SW3
3 becomes an output mode, and image data is output. NTS
The address output from the horizontal write address generator 34 for C and the address output from the horizontal write address generator 35 for PAL are switched according to the mode.
The data is switched at 9 and stored in the image memory 11 according to the switched address. The stored data is read out from the image memory 11 according to the address output from the horizontal read address generation circuit 18 after a predetermined time.

In the reproducing mode, the SW 33 is in the input mode, and the luminance signal Y and the color difference signals Cr and Cb are input signals.
When the serial data is input to the image memory 11, the address output from the horizontal write address generation circuit 18 is switched by the address switch SW18 and written in the order read from the image memory 11 in accordance with the address.
Reading from the image memory 11 is N in the case of the NTSC system.
This is performed in accordance with the address from the TSC horizontal read address generation circuit 34. In the case of the PAL system, it is performed in accordance with the address from the PAL horizontal read address generation circuit 35, and three types of data output from the image memory 11 pass through the SW 32. The luminance signals Y and the color difference signals Cr and Cb are separately input to the FIFOs 6, 7, and 8, respectively, and the transfer rates are converted. The data output from each of the FIFOs 6, 7, and 8 passes through the SW 31, and the color difference signals Cr and Cb among them are interpolated by the horizontal interpolation filters 21 and 22 in the case of the NTSC system. In the PAL system, the vertical interpolation filter 2
Interpolation is performed at 3, 24. The luminance signal Y is output through the switches SW31 and SW30. Each interpolation filter 21, 22, 23,
The output data from the switch 24 is input to the switching SW 30 and is switched and output according to the mode.

[0019]

As described above, according to the data rearranging apparatus of the present invention, the FIF for converting the data transfer rate is used.
O can be shared by the NTSC system and the PAL system, the read address generation circuit of the image memory, especially the horizontal address generation circuit can be shared, and the circuit scale can be reduced by sharing the recording mode and the reproduction mode.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data rearranging apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a data rearranging apparatus according to a second embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of a data rearranging apparatus according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a signal rate of one field.

FIG. 5 is a diagram showing a signal rate of an input signal of an image memory.

FIG. 6 is a diagram showing a signal rate of an output signal of an image memory.

FIG. 7 is a diagram showing a memory map (one frame) for NTSC.

FIG. 8 is a diagram showing a memory map (one frame) for PAL.

FIG. 9 is a block diagram showing a conventional data sorting apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Horizontal thinning filter for Cr 2 Horizontal thinning filter for Cb 3 Vertical thinning filter for Cr 4 Vertical thinning filter for Cb 6 FIFO 7 FIFO 8 FIFO 11 Image memory

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 9/00 H04N 9/64 H04N 11/12

Claims (3)

(57) [Claims] 1. A data rearranging apparatus for recording input moving image data in an image memory for each page and rearranging the input moving image data in units of blocks when one field or a plurality of fields is defined as one page. When the input signal is an NTSC signal, a horizontal decimation filter that limits the horizontal band of the color difference signal and further thins out data in the horizontal direction, and when the input signal is a PAL signal, the color difference signal A vertical thinning circuit for limiting the vertical band of the data and further thinning the data in the vertical direction, a SW for switching the thinned data, and an input data rate for serially transferring the input Y, Cr, and Cb signals. Signal for converting luminance into a data rate to be input to an image memory, a color difference signal C common to FIFO, NTSC, and PAL for Y signal.
two types of FIFOs for r and Cb, a switch for switching each FIFO output data, an image memory for one page, a horizontal address generation circuit for writing NTSC data to the image memory for one page, and a PAL. 1. A data rearranging apparatus comprising: a horizontal address generating circuit for writing data of a system; and an address generating circuit for horizontal reading for both an NTSC system and a PAL system. 2. An apparatus for recording input block unit data in an image memory and rearranging the data in page units when one field or a plurality of fields are defined as one page. In the case of a signal of the system, a horizontal interpolation filter for interpolating data in the horizontal direction of the color difference signals Cr and Cb, and when the output signal is a signal of the PAL system, a vertical interpolation for interpolating data in the vertical direction of the color difference signal A filter and a luminance signal Y FIFO for converting the data rate of the serial data from the image memory into a parallel data output data rate of the luminance signal Y and the color difference signals Cr and Cb, NTSC, and the color difference signal Cr shared by the PAL.
Two types of Cb FIFOs and a switch for switching the output data of each interpolation filter are provided. The image memory for one page and the NTSC system for the image memory for one page, PA
Horizontal address generator for data writing shared by L system, P
AL type data horizontal read address generation circuit, NTS
A data rearranging apparatus, comprising: a C-system horizontal data read address generating circuit. 3. The data sorting device according to claim 1 and the data sorting device according to claim 2 are combined to form an NTS
C, PAL shared horizontal read address generation circuit, NT
3. The data rearranging apparatus according to claim 1, wherein a horizontal write address generating circuit shared by SC and PAL is shared, and a FIFO for converting a transfer rate is shared.