JP2572420B2 - Video signal processing circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit for reducing and displaying a screen.

[Conventional technology]

As an example of a device for displaying a reduced screen by applying a digital memory, a technical report of the Society of Television Engineers, TEBS114
−4, ED1009 “Multi-function VTR with digital signal processing” (1
(December 986). The nine-screen multi-screen function described in this paper is a function that simultaneously displays nine small screens reduced to one third. The screen is reduced by thinning out the video signal in the horizontal and vertical directions using a field memory, and this thinning out of the data causes an interruption in which the high frequency component of the video signal is turned back to the low frequency component. . Therefore, in the conventional example, a low-pass filter is provided to perform band control on the video signal before the reduction processing, thereby preventing horizontal aliasing interference.

[Problems to be solved by the invention]

By the way, the reduction of the screen in the vertical direction is performed by thinning out the scanning lines. This decimation, in other words,
Since the screen is sampled in the vertical direction, considering the frequency components in the vertical direction, especially when the frequency components are high, the high frequency components are turned back to the low frequency side as in the case of the horizontal direction. Vertical aliasing occurs, and a phenomenon occurs in which horizontal stripes that should appear bright on the screen appear dark. The above prior art does not consider this point.

In order to prevent this vertical aliasing, it is necessary to perform a vertical filtering process. Generally, however, to construct a vertical filter for this purpose, storage of one operation line period of a video signal is required. There is a problem in that one or more line memories having a large capacity are required, and further memory is required in addition to the field memory.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a video signal processing circuit capable of solving such a problem and enabling vertical filtering without increasing the memory.

[Means for solving the problem]

In order to achieve the above object, the present invention reduces the number of scanning lines of an input video signal to 1 / n (where n is an integer of 2 or more) so that a vertical screen can be reduced. ,
(Ni + 1) th (i = 0, 1, 2,...) Of the input video signal
..) And writes it to the row address i of the field memory, and (ni + 1 + j) -th (j = 1, 2,..., N−1) of the input video signal. Means for reading out the data written at the row address i of the field memory by the scanning line;
Means for performing an arithmetic operation on the data of the (+ 1 + j) th scanning line and the data read from the row address i of the field memory, and means for writing the data obtained as a result of the arithmetic processing to the row address i of the field memory. Is provided.

[Operation] The data of the (ni + 1) th scanning line of the input video signal is
Predetermined arithmetic processing is performed and the result is written to the row address i of the field memory. In the next (ni + 2) -th scanning line, the data of this row address i in the field memory is read out, and the data of the (ni + 2) -th scanning line of the input video signal is arithmetically processed, and the same row address i in the field memory is read. Is written to. The arithmetic processing of the scanning line data of the input video signal and the data read from the row address i of the field memory and the writing of the calculation result to the same row address i are performed from the (ni + 2) -th input video signal. ni + 1 + n-1) at least one of the scan lines
It is done about one.

As a result, one scanning line is formed by the arithmetic processing of two or more and n or less scanning lines, and the band is limited for frequency components in the vertical direction.

〔Example〕

Hereinafter, the embodiment of the present invention will be described by taking as an example a case where the screen is reduced to 1/3.

FIG. 3 shows the principle of operation of the present invention, in which 31 is an original screen, and 32 is a screen reduced to 1/3 (reduced screen). Here, each scanning line of the original screen 31 is represented by..., L _3i-3 ,
l _3i-2 ,..., l _3i , l _{3i + 1} ,..., l _{3i + 4} , l _{3i + 5} ,... In the case of the interlace method, these are the same field scanning lines. Each of the scanning lines of the reduced screen 32 is represented by..., L ′ _i−1 ,
l ′ _i ′ l ′ _{i + 1} ,..., each of the scanning lines of the reduced screen 32 is formed from three scanning lines of the original screen 31. For example, the scanning line l ′ _i−1 of the reduced screen 32 is
1 are formed from three scanning lines l _3i-3 , l _3i-2 , l _3i-1 , and similarly, the scanning line l ′ _i is the scanning lines l _3i , l _{3i + 1} ,
From l _{3i + 2} , scanning line l ′ _{i + 1} becomes scanning lines l _{3i + 3} , l _{3i + 4} , l _{3i + 5}
Respectively.

Strictly speaking, the video signals of the scanning lines of the reduced screen 32 are formed from the video signals of the three scanning lines of the original screen 31, but the expression becomes cumbersome. Is expressed as “formed from scanning lines”.

To create a scan line of the reduced screen 32, select 3
The scanning lines are added at a predetermined ratio. Now, assuming that α: β: α (where α + β + β = 1) in this case, taking the scanning line l ′ _i of the reduced screen 32 as an example, l ′ _i = α · l _3i + β · l _{3i + 1} + α・ It becomes l _{3i + 2} . An example of this ratio α: β: α is 1/4: 1/2:
There is 1/4.

FIG. 1 is a block diagram showing an embodiment of a video signal processing circuit according to the present invention based on such a principle, wherein 1 is an input terminal of a video signal of an original screen, 2 is an output terminal of a video signal of a reduced screen, and 3 Is an analog-to-digital converter (A / D)
4 is a sync separation circuit, 5 and 6 are multipliers, and 7,
8, 9 are switching switches, 10 is an adder, 11 is a frequency divider, 12 is a write control circuit, 13 is a column address generator, 14
Is a row address generation circuit, 15 is a field memory, 16 is a line buffer, 17 is a read system control circuit, 18 is a digital / analog converter (hereinafter referred to as a D / A converter), 1
9 is a latch circuit.

3, a video signal (hereinafter, referred to as an input video signal) 1a input to an input terminal 1 is a video signal corresponding to the original screen 31 in FIG. After being converted to the digital signal 1b, the multipliers 5 and 6 respectively output α
Times and β times. Normally, the sampling frequency for digitizing a video signal is set to four times the color subcarrier frequency in consideration of image quality and the like. / 3 is set, whereby the data in the horizontal direction is thinned out. The output digital signal of the multiplier 5 is switched by the switch 7
, And an E contact of the switching switch, and an output digital signal of the multiplier 6 is supplied to a B contact of the switching switch 7. The switching switches 7 and 9 and the switching switch 8 are controlled by a write control circuit 12.

Here, three scanning lines l of the original screen 31 in FIG.
_The case where the scanning line l' _i of the reduced screen 32 is created from _3i , _{l3i + 1} , _{l3i + 2} will be described.

Now, assuming that the input video signal 1a is of the scanning line _l3i ,
Period of the scanning line l _3i, switching switch 9 is closed to contact E side, through the switching switch 9 the output digital signal of the multiplier 5 is supplied to the field memory 15 as write data 1p.

On the other hand, the input video signal 1a is supplied to the sync separation circuit 4,
The vertical synchronizing signal 1c and the horizontal synchronizing signal 1d are separated, and a clock 1e synchronized with the horizontal synchronizing signal 1d is generated. The horizontal synchronizing signal 1d is frequency-divided by the frequency dividing circuit 11 into three pulses.
Write control circuit 12 together with clock 1e as 1h
Supplied to As a result, the write control circuit 12
Are the control signals of the switching switches 7, 8, 9 and the control signals of the column address generation circuit 13, the row address circuit 14, and the field memory.
15 write / read switching signals 1r are generated.

The column address generating circuit 13 is initialized by a horizontal synchronizing signal 1d, and generates a column address 1f which is updated for each sample data output from the A / D converter 3 by a clock 1e. The row address generating circuit 14 is initialized by the vertical synchronizing signal 1c and generates a row address 1g which is updated every output pulse 1h of the frequency dividing circuit 11. Since the frequency divider 11 divides the horizontal synchronization signal 1d by three, the input video signal from the input terminal 1 is
The row address 1g is held at the same value for three scanning line periods of 1a,
The row address 1g is updated every three scanning lines. Here, the row address 1g has the same value for the scanning lines l _3i , l _{3i + 1} , l _{3i + 2} .

The field memory 15 has a column address 1f and a row address 1g.
When the write / read switching signal 1r is "L" (low level), the mode is set to "H" (high level).
In the case of, the reading mode is set respectively. Column address
The position specified by 1f and the row address 1g is an area having a capacity capable of storing one piece of m-bit sample data. write/
When the read switch signal 1r is "L", write data (sample data) from the switch 9 is written at a position specified by the column address 1f and the row address 1g, and the write / read switch signal 1r Is "H", the sample data written at this position is read.

FIG. 2 schematically shows the field memory 15, and assuming that the number of bits by the A / D converter 3 (FIG. 1) is m, m partial memories 15 ₁ , 15 ₂ ,. They are 15 _m long and are divided vertically and horizontally in an atorics form. These minute areas to be divided are specified by a column address 1f specifying the horizontal position and a row address 1g specifying the vertical position. partial memory 15 _1, 15 _2, ..., minute regions, one for 15 _m is designated simultaneously. Then, m bits of sample data are written or read one by one into the simultaneously designated partial memories 15 ₁ , 15 ₂ ,..., 15 _m . These m designated micro-areas are the designated positions of the field memory 15 at the designated positions.

Now, assuming that the input video signal 1a in FIG. 1 is that of the scanning line _{l3i in} FIG. 3, writing / writing is performed during this scanning line _l3i.
The read switching signal 1r is "L", and the field memory 15 is set to the write mode. Here, as shown in FIG. 4A, the j-th sample data on the scanning line _l3i is represented by L (3
i, j), the switching memory 9 to the field memory 1
The write data supplied to 5 is α, L (3i, j). At this time, assuming that the column address 1f is CA _j and the row address 1g is RA _i , the position (CA _j , RA _i ) (the second
) Is written with the write data α · L (3i, j). For the next (j + 1) -th sample data L (3i, j + 1), the write data 1p becomes α · L (3i, j + 1) and CA
position specified by the row address 1g of the column address 1f and RA _i of _{j + 1} is written to the _{(CA j + 1, RA i} ).

Thus, each sample data of the scanning line l _3i is
Row address 1g is same as the column address 1f are sequentially written sequentially positions different from RA _i. When the writing of the scanning line l _3i is a final connexion next scanline l _{3i + 1,} the switching switch 7 contacts B
The switch 9 switches to the contact F side. For this purpose, the digital signal output from the A / D converter 3 is converted by the multiplier 6 into β
It is supplied to the adder 10 through the switching switch 7. On the other hand, the write / read switching signal 1r becomes “H” in the first half of each sample data period output from the A / D converter 3 and “L” in the latter half. Accordingly, the field memory 15 enters the read mode in the first half period of each sample data, and enters the write mode in the second half period. The switching switch 8 closes to the contact D when the field memory 15 is in the read mode, and closes to the contact C when the field memory 15 is in the write mode.

The row address generator 14, as in the case of the scanning line l _3i, but outputs the row address 1g of RA _i, column address generation circuit 13, horizontal with the start of the scanning line l _{3i + 1} synchronization signal 1d And the same C as in the case of the scanning line _l3i.
A ₀ , CA ₁ ,..., CA _j , CA _{j + 1} ,.

Therefore, as shown in FIG. 4B, the A / D converter 3 outputs the j-th sample data L (3i) of the scanning line _{l3i + 1.}
Assuming that (+1, j) is output, the sample data β · L (3i + 1, j) obtained by multiplying β by 3 is supplied to the adder 10 via the switching switch 7.

On the other hand, during the period of the sample data L (3i + 1, j), the field memory 15 stores the j-th data α of the scanning line _l3i.
The position (CA _j , RA _i ) where L (3i, j) is stored is specified, and the field memory 15 is in the read mode in the first half of this period, so this position (CA _j , RA _i ) , The sample data α · L (3i, j) is read out. This passes through the switching switches 9 and 8 as read data Ip, and the latch circuit 1
It is latched to 9. The output data α of this latch circuit 19
L (3i, j) is supplied to the adder 10 and added to the sample data β · L (3i + 1, j) of the multiplier 6.

In the latter half of the period of the sample data β · L (3i + 1, j), the field memory 15 enters the write mode, and the switching switch 8 switches to the contact C side. For this, adders
The output data {α · L (3i, j) + β + L (3i + 1, j)} is supplied to the field memory 15 as write data 1p through the switching switches 8 and 9. In the field memory 15, the write data 1p represented by the above equation is written at the position (CA _j , RA _i ) where the sample data L (3i, j) has been written so far.

Similarly, the scanning line _{l 3i + 1 (j + 1} ) th respect to the sample data L (3i + 1, j + 1), so far the scanning line l _3i field memories 15 (j + 1) th sample data L (3i , j + 1) was written (CA
_{j + 1} , RA _i ), the output data {α · L (3i, j + 1) + β · L (3i + 1, j + I)} of the adder 10 is written.

In this way, the field memory 15 is stored at the scanning line _{l3i + 1.}
At which the scanning line l _3i was concentrated at (CA ₀ , RA _i ),
_{(CA 2, RA i),} ......, (CA j, RA i), (CA j + 1, RA i), ...
Is rewritten.

When the writing of the scanning line _{l3i + 1} is completed and the next scanning line _{l3i + 2} is reached, the switching switch 7 switches to the contact A side. The switching switch 9 is held at the contact F side, and the switching operation of the switching switch 8 and the mode switching of the field memory 15 are performed by the scanning line _{l3i + 1.}
It is the same as when The row address generator 14 has the same RA _i
And outputs the row address 1g of the
The column address 1f is output in the order of CA ₀ , CA ₁ ,...

Therefore, similarly to the case of the scanning line l _{3i + 1,} as shown in FIG. 4 (c), the scanning line l _{3i + 2} j-th sample data L
Data {α · L (3i, j) + β · L (3i + 1, j)} is read from the position (CA _j , RA _i ) of the field memory 15 in the first half of the period (3i + 2, j), and is read in the second half. And sample data α · L (3i
+ 2, j) and the added write data 1p, that is, {αL (3i, j) + βL (3i + 1, j)} + αL (3i + 2, j)} are the same as those in the field memory 15. Written to the location (CA _j , RA _i ).

The next (j + 1) th sample data L (3i + 2, j +
Also in 1), data {α · L (3i, j + 1) + β + L (3i + 1, j + 1) + α · L (3i + 2, j + 1)} is similarly stored at the position (CA _{j + 1} , RA _i ) of the field memory 15. Then, similarly, writing to the field memory 15 at the scanning line _{l3i + 2} is performed.

In this way, the sample data of the scanning lines l _3i , l _{3i + 1} , l _{3i + 2} is added to each position of the i-th row address RA _i of the field memory 15 in the ratio α: β: α. Will be memorized.

In the next three scanning lines l _{3i + 3} , l _{3i + 4} and l _{3i + 5} in FIG.
The output pulse 1h of the frequency dividing circuit 11 is supplied to the row address generating circuit 14, and the row address 1g becomes RA _{i + 1.} Similarly, each of the scanning lines l _{3i + 3} , l _{3i + 4} , l _{3i + 5} Sample data is α: β:
The row addresses of the field memory 15 are added at the rate of α, and are stored at sequential positions where the row address is RA _{i + 1} .

In this way, the input video signal 1a is stored in the field memory 15
Although written to, data written in each position of the row address RA _i of the field memories 15, the sample data of the scanning line l _'i reduced screens 32 in FIG. 3. These scanning lines l ′ _i are three scanning lines l _3i , l _{3i + 1} , l of the original screen 31.
_{Since 3i + 2} is averaged by performing predetermined weighting, it means that filtering has been performed in the vertical direction.

The field memory 15 has a storage capacity for one field when the input video signal 1a is digitized at a normal sampling frequency. However, when the screen is reduced, the output video signal of the A / D converter 3 Since the input video signal 1a is digitized at 1/3 of the normal sampling frequency, the input video signal 1a is stored only in a 1/9 area of the entire field memory 15. This storage area can be designated by the write system control circuit 12 by appropriately setting a preset value when the column address generation circuit 13 and the row address generation circuit 14 are initialized.

Here, the horizontal direction of the field memory 15 corresponds to one scanning line displayed on the monitor, and the scanning lines are arranged in the vertical direction of the field memory 15.

The read system control circuit 17 reads one scanning line from the field memory 15 during the horizontal blanking period of the video signal 1a input to the input terminal 1, and transfers it to the lambuffer 16. Next, the readout control circuit 17 transfers and outputs the data of the line buffer 16 during the horizontal scanning period of the input video signal 1a. This allows the line buffer
A digital signal of one operation line is obtained from 16, converted into an analog video signal by the D / A converter 18, and output from the output terminal 2. The reading operation of the field memory 15 is sequentially performed.

Therefore, the input video signal 1a is processed and stored in the 1/9 area of the field memory 15 as described above, so that the screen reduced to 1/2 is displayed on the monitor. Further, by sequentially performing the write operation and the read operation, a moving image can be displayed on the monitor.

In the case of 9-screen multi-screen, field memory 15
In the example, the entire area is divided into nine areas, and one screen is assigned to each area. Specify the area to be written
Column address generation circuit 1 by write control circuit 12
3. It is performed under the control of the row address generation circuit 14.
That is, for each screen to be written into the field memory 15, the preset values for initializing the column address generation circuit 13 and the row address generation circuit 14 are stored in the field memory 15
What is necessary is just to change so that the area | region used may be designated.
The reading operation from the field memory 15 is the same as described above.

Also, by storing one reduced screen in the field memory 15, reading out the video signal of this reduced screen in synchronization with another video signal, and fitting this in the other video signal, it is possible to display two screens. Become. In the case of this two-screen display, the storage capacity of the field memory 15 may be one field of the reduced screen.

As described above, in this embodiment, vertical filtering can be performed using a field memory for screen reduction without providing a dedicated line memory for vertical filtering separately. Without increasing the memory, it is possible to prevent a vertical fold obstruction and to obtain a high-quality reduced screen.

In FIG. 1, the latch circuit 19 is provided between the contact D of the switching switch 8 and the adder 10, but the latch circuit 19 is provided between the adder 10 and the contact C of the switching switch 8, and the A / D converter The output data of the adder 10 may be latched in the first half of the period of each sample data output from the third.

FIG. 5 is a block diagram showing another embodiment of the video signal processing circuit according to the present invention, wherein 51 is an input terminal, 52 is a YC (luminance / color) separation circuit, 53 is a chroma decoder, and 54 is a switching switch. , 55 is an S / P (serial-parallel) conversion circuit, 56 and 57 are switching switches, 58 is a color encoder, 59 is a mixing circuit, 60 is a switching switch, 61 is a synchronization separation circuit, 62 is an input terminal, and 63 is an output Portions corresponding to FIG. 1 are denoted by the same reference numerals. In addition, the portions corresponding to FIG. 1 which are used for the luminance signal are denoted by Y, Y ₁ and Y ₂ codes, and the portions used for the color difference signals are denoted by the M code. ing.

This embodiment relates to a two-screen color display in which a child screen reduced to one third is fitted and displayed on a parent screen.

In the figure, a color video signal of a small screen (hereinafter referred to as a small screen input video signal) is input to an input terminal 51, and a YC
The signal is separated into a luminance signal (hereinafter, referred to as Y signal) 5b and a chroma signal 5a by a separation circuit 52. The chroma signal 5a is supplied to a chroma decoder 53 and is supplied to two color difference signals, that is, (RY).
The signal is decoded into a signal 5c and a (BY) signal 5d. Y signal
5b, (RY) signal 5c and (BY) signal 5d are switched by switch switch 54 so that their sampling rates are 4: 1:
It is sampled by switching so as to be 1, that is, in the order of Y, Y, RY, Y, Y, BY. At this time, Y
The signal, the (RY) signal, and the (BY) signal are thinned out in the horizontal direction. The output signal of the switching switch 54 is supplied to the A / D conversion circuit 3 and is converted into an m-bit digital signal. Therefore, the output signals of the A / D conversion circuit 3 are the Y signal, the (RY) signal, and the (B
-Y) A signal in which the sample data of the signal is arranged.

Such a signal is supplied to the S / P conversion circuit 55, and (RY)
A digital signal (hereinafter, referred to as a dot-sequential color difference signal) 5e in which signal sample data and (BY) signal sample data are alternately arranged, and every other sample data of the input Y signal sample data A digital signal (hereinafter, referred to as a first Y signal) 5f, and a digital signal (hereinafter, referred to as a second Y signal) composed of every other sample data.
5g). The dot-sequential color difference signal 5e, the first Y signal 5f, and the second Y signal 5g have the same sampling rate, and the S / P conversion circuit 55 so that the dimming of the sample data matches each other.
Output from

The dot-sequential color difference signal 5e is supplied to the multiplication circuits 5M and 6M and the switching switch 7
M, 8M, 9M, an adder circuit 10M, and a latch circuit 19M perform the same vertical filtering processing as in the embodiment shown in FIG. 1, and are written in a field memory 15M. Similarly, the first Y signal 5f and the second Y signal 5g also
The same vertical filtering as in the embodiment shown in the figure is performed, and the result is written in the field memories 15Y ₁ and 15Y ₂ .

Note that the dot-sequential color difference signal 5e, the first Y signal 5f, the second Y signal
For timing signal 5g each of the sample data match, the write system control circuit 12, the switching switch 7M, a 7Y _1, 7Y ₂ are simultaneously operated, the switching switch 8M, 8
Y _1, 8Y ₂ also are simultaneously operated, the switching switch 9M, 9Y _1, 9Y ₂ also can be operated simultaneously, a memory 15M, 15Y _1, 15Y ₂ are both column address from the column address generation circuit 13, the row address generator A row address is supplied from the circuit 14.

The field memories 15M, 15Y ₁ and 15Y ₂ have a storage capacity of 2 fields, and are divided into two areas F ₁ and F ₂ having a storage capacity of 1 field as shown in FIG. odd field to _1, even field is respectively written into the region F _2. Here, the storage capacity of one field may be the storage capacity of one field on a reduced screen or the storage capacity of a normal field.

On the other hand, the color video signal 5h of the main screen is input from the input terminal 62, and supplied to the contact H of the switching switch 60 and the synchronization separation circuit 61. In the synchronization separation circuit 61, the vertical synchronization signal 5p and the horizontal synchronization signal 5r are separated from the color video signal 5h of the main screen and supplied to the readout control circuit 17.

The readout control circuit 17 is composed of the field memories 15M and 15M.
Y, 15Y ₂ Read control and line buffer
16M, 16Y ₁ , 16Y ₂ are controlled, and point-sequentially at a predetermined timing with respect to the color video signal 5h of the main screen so that the child screen reduced to 1/3 is at a predetermined position with respect to the main screen. Point difference signal 5
s, the first Y signal 5t, and the second Y signal 5u are read. In this case, the write control circuit 12
In which of the areas F ₁ and F ₂ (FIG. 6) in 15M, 15Y ₁ and 15Y ₂ to write data is specified by controlling the column address generation circuit 13 and the row address generation circuit 14.
At the same time, write related control circuit 12 controls the read system control circuit 17, which in Yotsute field memory 15M, 15Y _1, 15Y ₂ in the area of which is not performed writing area F _1, F ₂ Reading is performed.

Here, field memory 15M, when 15Y _1, 15Y ₂ has a storage capacity of 2 fields worth of the reduced screen, for each field of the color video signal 5h of the main screen, the predetermined set of fields Reading is performed at a speed three times the writing speed within the period. Also, field memory 5
If M, 5Y ₁ and 5Y ₂ have a normal two-field storage capacity, a reduced screen with a reduction ratio of 1/3 has been written to a predetermined area of these memories, and reading is performed using the image of the main screen. An area corresponding to one field is read every one field of the signal 5h.

The dot-sequential color difference signal 5s is supplied to the switch 56, and (R
(Y) signal sampling and (BY) signal sample data. These color difference signals are supplied to a color encoder 58, and under the control of the readout system control circuit 17, a chroma signal is formed in such a manner that the phase matches the color subcarrier in the color video signal 5h of the main screen. This chroma signal is converted into an analog signal by the D / A conversion circuit 18M and supplied to the mixing circuit 59.

The second read from the first Y signal 5t and field memories 15Y ₂ read from the field memories 15Y ₁
Signal 5u is supplied to a switching switch 57, and these sample data are alternately selected and synthesized to form a digital Y signal 5u.
The signal 5w is obtained. Here, the sample data of the first Y signal 5t and the sample data of the second Y signal 5u are the sample data of the Y signal of the signal output from the A / D conversion circuit 3 as the sample data of the digital Y signal 5w. The timing is shifted so that the same arrangement as that of FIG. In order to do this, the transfer clocks of the line buffers 16Y ₁ and 16Y ₂ may be shifted in phase.

The digital Y signal 5w is converted into an analog signal by the D / A conversion circuit 18Y, and is mixed with the chroma signal 5v from the D / A conversion circuit 18M by the mixing circuit 59 to form the color video signal 5z of the child screen. The color video signal 5z of this small screen is switched by switch 60.
Is supplied to the contact point G. The switching switch 60 is controlled by the readout system control circuit 17, and normally closes to the contact H side to select the color video signal 5h of the main screen. And select the color video signal 5z. In this way, a color video signal obtained by synthesizing the color video signal 5z of the child screen with the color video signal 5h of the parent screen is obtained, and supplied from the output terminal 63 to a monitor (not shown). As a result, on the monitor,
A child screen reduced to 1/3 is displayed at a predetermined position on the main screen.

According to this embodiment, the child screen is reduced in size by filtering it in the vertical direction and is synthesized with the parent screen.
Screen display can be performed. Also, a dot-sequential color difference signal
Since the sampling rates of 5e, the first Y signal 5f, and the second Y signal 5g are equal, the field memories 15M, 15M
Y _1, column address generation circuit 15Y _2, to the row address generating circuit can be made common, a means for vertical filtering process can be controlled by a common control circuit, the circuit configuration is greatly simplified Is done.

Also, field memory 15M, the 15Y _1, 15Y _2, as shown in FIG. 6, because the writing area F _1, F ₂ having a storage capacity of each one field is performed a read in areas not done In addition, the reading does not overtake the writing, so that the occurrence of the joint of the small screen due to this can be avoided, and the scanning line in the vertical filtering process by three scanning lines is not read.

In this embodiment, the filtering in the vertical direction is also performed on the color difference signal. However, this processing is particularly performed only on the Y signal in which aliasing interference is conspicuous, and the mere scanning line thinning is performed on the dye signal. It may be.

Further, the field memories 15M, 15Y ₁ , and 15Y ₂ may have four areas each having a storage capacity of one field. In this case, two areas are used for storing odd fields, and the remaining two areas are used for storing even fields, so that when the parent screen is an odd field, an odd field area where writing is not performed is read. ,
When the parent screen is an even field, it is also possible to read an even field area where writing is not performed.

Further, in this embodiment, the Y signal, the (RY) signal,
(B-Y) The signals are switched by the switching switch 54 to mix these sample data, and these are digitized by the A / D conversion circuit 3. However, these signals may be separately A / D converted. .

Furthermore, the output signal of the A / D conversion circuit 3 may be directly subjected to filtering in the vertical direction to reduce the screen size.

FIG. 7 is a block diagram showing still another embodiment of the video signal processing circuit according to the present invention, wherein 1 is an input terminal of a color video signal, 64 is a synchronous addition circuit, and a portion corresponding to FIG. Are denoted by the same reference numerals, and redundant description is omitted.

This embodiment enables a nine-screen multi-screen in which nine screens reduced at a reduction ratio of 1/3 are divided and displayed.

In the figure, the color video signal from the input terminal 1 is
As in the embodiment shown in FIG. 5, a dot-sequential color difference signal,
First Y signal is filtering processing in the vertical direction for each second Y signal, it is reduced at a reduction rate of 1/3 by field memories 15M, although be written to 15Y _1, 15Y _2, each field memory 15M , 15Y ₁ and 15Y ₂ each have a normal one-field storage capacity as a whole, and are divided into nine areas as shown in FIG. 8, and each area is a reduced and different input color video signal. The screen will be stored. Writing of these areas is performed by controlling the column address generating circuit 13 and the row address generating circuit 14 at the time of initialization by the write control circuit 12, as in the embodiment shown in FIG. .

The field memories 15M, 15Y ₁ , and 15Y ₂ are read out in synchronization with each other by the read-out control circuit 17 in the same manner as in the embodiment shown in FIG. This reading is performed over the entire memory. Field memory 15
The dot-sequential color difference signals are read from M, and the first and second Y signals are read from the field memories 15Y ₁ and 15Y ₂ , respectively. The dot-sequential color difference signal is divided into a (RY) signal and a (BY) signal by a switching switch 56, and a color signal is formed by a color encoder 58. This chroma signal is converted into an analog signal by the D / A conversion circuit 18M and supplied to the mixing circuit 59. Further, the first and second Y signals from the field memories 15Y ₁ and 15Y ₂ are combined by a switching switch 57 to form a Y signal, and a synchronous addition circuit
After the vertical synchronizing signal, the horizontal synchronizing signal, the burst signal, etc. are added in 64, they are converted into analog signals in the D / A conversion circuit 18Y, and mixed with the chroma signal from the D / A conversion circuit 18 in the mixing circuit 59. A color video signal is obtained. The color video signal output from the mixing circuit 59 is supplied from an output terminal 63 to a monitor (not shown). As a result, a multi-screen of nine screens is displayed on the monitor.

Thus, according to this embodiment, each reduced screen is subjected to the filtering in the vertical direction, thereby realizing high-quality multi-screen display.

In this embodiment, the field memories 15M, 15M
The storage capacity of Y ₁ and 15Y ₂ may be increased, and two or more fields may be used for each reduced screen.

The embodiments of the present invention have been described above, but the present invention is not limited to only these embodiments.

That is, in the above embodiment, the reduction ratio of the screen is set to 1/3. However, in general, the reduction ratio can be set to 1 / n. In this case, the filtering in the vertical direction is performed for every n scanning lines at most. , Each scanning line may be multiplied by a desired coefficient and added.

In the above embodiment, the field memory is read in the first half of the period of each sample data, and in the second half, the read sample data and the supplied sample data are added and written to the field memory. However, if it takes a long time to perform this arithmetic processing, the read sample data is temporarily latched, arithmetic processing is performed, and the arithmetic processing result is written to the original position. , May be shifted to the latter half of the period of the next sample data or the subsequent sample data. In this case, it is necessary to make the column address different between the first half and the second half of each sample data period, and complicated control of the column address generation circuit 13 is required. On the other hand, the column address may be constant during each sample data period. In this case, the read position is shifted from the write position of the calculation result of the sample data read from this position, but the shift of the sample data of each scanning line after the vertical filtering is performed. There is no problem because they are equal. Of course, n
When performing vertical filtering using one scanning line, the writing result of the calculation result is one for each scanning line.
If the step is shifted (to the next position), the column address generating circuit 13 is initialized so that the column address is shifted by one step for each scanning line. Also, like this, 1
If the sampling write position shifts for each scanning line, and the read address overtakes the write address in the middle of the vertical filtering process, the other vertical filtering process ends for that scanning line. This means that the scanning line is shifted in the horizontal direction. In order to prevent this, a memory having a storage capacity of 2 fields or more may be used as a field memory, and a field area in which reading and writing are not performed may be performed.

Furthermore, in the above-described embodiment, the sample data for one scanning line read from the field memory is temporarily transferred to the line buffer and then output from the line buffer. However, the present invention is not limited to this. Not something.

Furthermore, the functions of the embodiments shown in FIGS. 5 and 7 share the same portions, and the portions specific to the two-screen display and the portions specific to the multi-screen display can be switched. The display can be selectively performed. In this case, the field memories 15A, 15Y ₁ and 15Y ₂ have a storage capacity that is an integral multiple of the normal field of the video signal.

Furthermore, in the embodiment shown in FIGS. 5 and 7, after the digital chroma signal output from the color encoder 58 and the digital Y signal output from the switching switch 57 and the synchronous addition circuit 64 are mixed, You may make it / A conversion.

〔The invention's effect〕

As described above, according to the present invention, the vertical filtering processing can be performed using the field memory for image reduction, and the line memory for the vertical filtering processing that has been conventionally required is provided. Thus, it is possible to reduce the circuit scale and realize display of a reduced screen with high image quality.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a video signal processing circuit according to the present invention, FIG. 2 is a memory map diagram of a field memory in FIG. 1, and FIG. 3 shows a vertical filtering process according to the present invention. FIG. 4 is a timing chart showing the operation of the embodiment shown in FIG. 1, FIG. 5 is a block diagram showing another embodiment of the video signal processing circuit according to the present invention, and FIG. 6 is FIG. 7 is a block diagram showing still another embodiment of the video signal processing circuit according to the present invention, and FIG. 8 is a memory map diagram of the field memory in FIG. Input terminal of the 1 ...... video signal, second output terminal of the ...... video signal, 3 ...... A / D converter _{circuit, 5,5M, 5Y 1, 5Y 2} , 6,6M, 6Y 1, 6Y 2 ...
... multiplication _{circuit, 7,7M, 7Y 1, 7Y 2} , 8,8M, 8Y 1, 8Y 2, 9,9M, 9Y 1, 9Y 2
...... Switching switch, 10,10M, 10Y ₁ , 10Y ₂ ...... Addition circuit, 1
5,15M, 15Y ₁ , 15Y ₂ …… Field memory.

Claims (2)

(57) [Claims] 1. A video signal in which the number of scanning lines of an input video signal is reduced to 1 / n (where n is an integer of 2 or more) using a field memory to perform a vertical reduction process of a screen. Means for processing the data of the (ni + 1) -th (where i = 0, 1, 2,...) Scanning line of the input video signal and writing the data to the row address i of the field memory; , (Ni + 1 + j) -th (where j =
Means for reading the data written at the row address i of the field memory with the scanning lines of (1, 2,..., N-1);
Means for performing an arithmetic operation on the data of the (ni + 1 + j) th scanning line of the input video signal and the data read from the row address i of the field memory, and converting the data obtained as a result of the arithmetic processing into the field memory Means for writing to the row address i, wherein at least one of the (ni + 1 + i) -th to (ni + 1 + n-1) -th scanning lines of the input video signal performs the above-mentioned arithmetic processing and the transfer to the row address i of the field memory. A video signal processing circuit for performing writing. 2. The method according to claim 1, wherein the arithmetic processing of the data of the (ni + 1) th scanning line of the input video signal is a processing of multiplying the data by a predetermined coefficient. The arithmetic processing on the scanning line is performed by multiplying the data on the scanning line by a predetermined coefficient and adding the data multiplied by the predetermined coefficient to the data read from the row address i of the field memory. And a video signal processing circuit.