JPS6386978A - Image storage device - Google Patents

Abstract

PURPOSE:To designate a read-out start position by one picture element unit, by constituting the titled device so that serial data input/output terminals of (n) pieces of dual port memories are all connected in parallel at the time of inputting a data, and only the corresponding input/output terminal of each memory is connected to an output by a serial clock of (n) phases at the time of outputting a data. CONSTITUTION:The titled device is provided with a means which has been constituted so as to input and output a serial data by a serial clock of (n) phases by connecting in parallel (n) pieces of dual port memories, and applies earlier the serial clock by a portion of a prescribed number of clocks, a frequency dividing means for starting a frequency division of the serial clock by a timing of a data for starting a display, and an output gate means for allowing only an output data to be displayed to pass through. According to such a constitution, in case when it is desired to read out a data in order from the first (i<=n) memory, the (n)-phase clock is applied in order from the first memory, the output is stopped until the (i-l)-th data, and from the i-th data, the output gate is opened and the output is started. The serial clock in this case is applied earlier by the (i-1) portion than the timing of the data to be displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image storage device capable of writing serially transmitted image data into a memory and serially reading out the data.

BACKGROUND OF THE INVENTION FIG. 6 is a block diagram of an example of a conventional image storage device. When an NTSC signal is input, it is separated into red, green, and blue components by an RGB separation circuit 1, each converted into a digital signal by an A/D conversion circuit 2, and sent to a memory 3.

On the other hand, a synchronization signal in the NTSC signal is separated by a synchronization separation circuit 4 and applied to a timing generation circuit 5, and a predetermined control signal created based on this synchronization signal is applied to a memory 3. The timing generation circuit 5 also generates a control signal for reading data from the memory 3, and in response to this control signal, data is sent from the memory 3 to the D/A conversion circuit 6 and converted into an analog signal. The output and the synchronizing signal from the synchronizing signal generating circuit 7 are combined by a combining circuit 8 and output to a monitor television 9. While writing and reading images in this manner, the host processor 1° exchanges data with the memory 3 by utilizing free time such as the blanking interval of the video signal. In this case, the memory 3 is usually a dual port memory having two types of input/output ports: a serial port that allows serial writing and reading, and a random access port that separately allows random writing and reading.

FIG. 7 is a block diagram showing an example of the internal configuration of a dual port memory. When performing random access, one cell in the memory cell array 11 is selected using a column address and a row address. That is, the row address is decoded by the row decoder 12, the column address is decoded by the column decoder 13, and one cell in the memory cell array 11 is selected. When writing data, the data input to the random input/output bannofer 14 is written to a selected cell in the memory cell array 11 through the sense amplifier 15.

Furthermore, when reading data, data of a selected cell in the memory cell array 11 is applied to the random input/output puff 714 through the sense amplifier 16 and output. The above explanation does not describe how to input row addresses and column addresses, how to specify data writing and reading, how to specify random access or serial access, etc. However, these differ depending on the type of memory, and this document Since it is not directly related to the invention, the explanation will be omitted.

Next, the case of serial access will be briefly explained. Serial access is performed via the data register 16 and serial input/output buffer 18 using a serial clock. Transfer is still performed between the memory cells in the row specified by the row address in the memory cell array 11 and the data register 16 according to the transfer command. Then, the grain pointer 1 is set to the column address specified at the time of this transfer.
7 is set. When the serial clock is input, serial access is started from the register indicated by the pointer 17 among the registers in the data register 16, and the pointer 1 is successively incremented by the serial clock. Therefore, in the case of writing, data is written to the data register 16 by the serial clock via the serial input/output cover sofa 18, and then the data register 1
6 to the memory cell array 11.

In addition, in the case of reading, first the address of the row to be read and the address of the pointer to start reading are specified as a row address and a column address, respectively, and then the data is transferred from the memory cell array 11 to the data register 16. By inputting the serial clock with the serial input/output buffer As mentioned above, when dual port memory is used, in addition to normal random access, it is possible to perform serial access using the serial clock.
This is very convenient for writing and reading serially transmitted image data such as Cj signals. In general, it is possible to operate faster when performing serial access than when performing random access, but there is a limit to that speed, and in reality, writing or There are cases where you want to read data. For example, this may be the case when it is desired to finely sample the video signal, or when it is desired to increase the readout clock speed to avoid using a high-resolution monitor television as the display. In such a case, a method is used in which multiphase serial clocks are input to several memories.

FIG. 8 shows an example of a configuration in which three-phase serial clocks are input using three memories. In FIG. 8, only the parts related to the serial clock and serial data are shown, and parts such as address designation are omitted. With this configuration, the frequency of the serial clock applied to one memory becomes IA of the original serial clock frequency, so the frequency of the original serial clock can be up to three times that of the case of one memory. It is possible to raise it.

In FIG. 8, reference numeral 19 denotes a frequency dividing circuit, which can reduce the image by dividing the frequency of the serial clock during writing, and can enlarge the image during reading. The changeover switches 20 to 22 are switched to the W side during writing and to the R side during reading. Also switch 23
-25 indicate that the outputs of delay circuits 26-28 are High.
It is set to turn on when the level is reached.

When writing, the input data is W of selector switches 2o to 22.
The signals are input to the serial ports of the memories 29 to 31 via the side. On the other hand, the serial clock is applied to a three-phase clock generation circuit 32 via a frequency dividing circuit 19, and the three-phase clocks are applied to serial clock inputs of memories 29-31, respectively. In this way, input data is stored in memories 29 to 31.
are sequentially written to the data registers. Then, when data for one row of each memory, that is, three rows in total, is written, data is transferred from the data register to the memory cell array.

Here, the positional relationship between the data written in the memories 29 to 31 and the input image will be briefly explained. For example, when writing an image corresponding to a horizontal scanning line into a memory as 640 pieces of image data, by configuring it as shown in FIG. 8 using three memories with 256 data registers,
A horizontal scan line's worth of data can be transferred from the data register to the memory cell array at one time. Therefore, the image data for each horizontal scanning line is sequentially written into the data registers of the memories 29 to 31 using the method described above.
When 640 pieces of data are written, the serial clock may be stopped and data may be transferred from the data register to the memory cell array.

Therefore, the input image data is AO-+BO→CO→MU1→
B1→C1→...→Person 212→B212→C212→
If input is made in the order of 213, there will be 0 people in the memory 29.
→Mu1→...→Person 213 are written in the order of memory 30.
In the order of BO-+B1→...→B212, memory 31
will be written in the order of Co-C1→...→C212.

At the time of reading, data for a predetermined horizontal scanning line is first transferred from the memory cell array to the data register, and then a serial clock is applied. The serial clock frequency divided by the frequency dividing circuit 19 is sent to the three-phase clock generating circuit 32.
The serial clocks are converted into serial clocks and applied to the serial clocks in memories 29-31, respectively. Taking the memory 29 as an example, when a three-phase clock is input, after a certain period of time (
Data is output from the serial port at a fixed time (determined by the delay of elements inside the memory, etc.) and applied to the changeover switch 20. The signal is then inputted to the switch 23 via the R side of the selector switch 20, and this switch 23 is turned on by the three-phase clock delayed by the delay circuit 26 as described above.

The delay time of the delay circuit 26 is set so as to delay the signal by the same amount as the delay in the memory 29 described above. Therefore,
The switch 23 is turned on only during the period of serial data output by the three-phase clock, and data is output. A similar operation is performed for the memories 30 and 31, and the serial data of the memories 29 to 31 are sequentially outputted as output data.

Figure 9 shows the waveforms of each part in Figure 8.
is the case where the frequency division ratio is 1, that is, no frequency division, and f-j is the case where the frequency division ratio is 2. In Figure 8, a is the serial clock, b
-d are the outputs of the three-phase clock generating circuit 32, and are added to the memories 29-31, respectively. Further, e indicates the output data at the time of reading, and the number 0. AI, . . . are data from the memory 29, BO, B1 . ...is memo 1J30
The data from Go, CI, . . . are data from the memory 31. Also, f indicates the output of the frequency dividing circuit 19 when the frequency division ratio is 2, g-1 indicates the output of the three-phase clock generation circuit 32, and j indicates the output data at the time of reading. . Although the figure shows an example in which the delay time inside the memory is negligibly small, if it cannot be ignored, the waveforms of e and j will be delayed by that time.

Problems to be Solved by the Invention However, in the above configuration, since three memories constitute one unit, data can only be handled in units of three pixels. For example, AO, BO.

Since one unit is CO, there is no problem if the readout start position is AO, but if you try to start readout from BO or CO, the following inconvenience will occur.

First, let's take as an example the case where you want to start reading from BO.
It is necessary to change the order of the three-phase clocks so that it becomes memory B → memory C → memory person.

In this case, the relationship between the three-phase clock and the output data is as shown in FIG. 10 a % d. That is, when data is first transferred from the memory cell to the data register by a transfer command, the data register of the memory person has MUO, AI, MU2, . ..., the data register of memo I73 has B.
o, B1. B2. Since data is stored in the order of cm, cl, c2°, etc. in the data register of memory C, the 3-phase clock is changed from memory B to memory C to memory C as shown in FIG. 10 IL-C. If you enter the memory in order,
The data are as shown in Figure d. B Q-+G O-) A
O-+ 81-) C1-bA1→... will be output in this order. Therefore, the order of the output image data is different from the original image, which is inconvenient.

Similarly, when it is desired to start reading from Go, if the order of the three-phase clocks is changed to memory C→memory B→memory person, the result will be as shown in FIG. 10e-h.

That is, the output data is in the order of Co→Mo-+Bo→C1→Mu1→B1→..., which is inconvenient because the order is different from the original image.

In view of the above, an object of the present invention is to provide an image storage device that can input and output data at high speed, and at the same time, does not cause any inconvenience even if the readout start position is specified in units of one pixel.

Means to Solve the Problem The present invention connects n memories in parallel that can input and output serial data by inputting a serial clock, and inputs and outputs serial data using an n-phase serial clock. It is configured as follows: a means for applying the serial clock earlier by a predetermined number of clocks; a dividing means for starting frequency division of the serial clock at the timing of the data to be displayed; and a frequency dividing means for applying only the output data to be displayed. 1. An image storage device characterized by comprising an output gate means for allowing the image to pass through.

Effect of the present invention With the above-described configuration, even when it is desired to read data sequentially from the i-th memory (i≦n), the n phase is applied sequentially from the first memory, and the output data is output. It is prevented from being output by gate means.

Then, output is stopped until the (i-1)th data, and the output gate is opened and output starts from the i-th data. In this case, the serial clock is applied (i-1) clocks earlier than the timing of the data to be displayed.

Furthermore, when enlarging an image by dividing the serial clock, the serial clock is not divided for the first (i-1) clock period, but starts from the i-th clock. .

As described above, reading can be started from any pixel, and the order of output data will not be out of order. Also n
Since two memories are connected in parallel, the frequency of the serial clock can be increased to n times that when using one memory, making it possible to input and output data at high speed.

Embodiment FIG. 1 shows a block diagram of main parts in an embodiment of the present invention. Figure 1 shows an example where three dual port memories are connected in parallel, and only the parts related to the serial clock and serial data are shown.
This corresponds to FIG. 8 described in the conventional column. Therefore, in FIG. 1, the same parts as in the conventional example are given the same numbers as those in FIG. What is different from the conventional example in FIG. 1 is an AND circuit 33, a timing generation circuit 34, a changeover switch 36, a delay circuit 36, and a switch 3.
Other parts may be the same as those in FIG.

First, the case of writing data will be explained.

When writing data, there is no need to specify the writing start position for each pixel because it can be specified at the time of reading. Therefore, writing can be performed using a method similar to the conventional method. That is, a high level signal is always applied from the typing generation circuit 34 to the changeover switch 36, the changeover switch 36 remains switched to the H side, and the changeover switches 20 to 22 are switched to the W side. Then, when the timing generation circuit 34 sets the b terminal of the AND circuit 33 to a high level at the timing when data to be written starts, writing is performed in the same manner as in the conventional method.

Next, the operation when reading data will be explained. The typing generation circuit 34 generates a signal that goes high at the timing of data to start displaying, and a signal that goes high from 0 to 2.
A clock earlier (as explained later, the number of clocks is determined depending on which memory data to start displaying)
The former is applied to the selector switch 36 and the delay circuit 36, and the latter is applied to the AND circuit 33. That is, the changeover switch 35 is switched to the L side before the timing of the data to start displaying, and it is switched to the H side when typing the data to start displaying.
can be switched to the side. Further, a continuous serial clock is applied to one input of the AND circuit 33, and a signal from the timing generation circuit 34 is applied to the other input as described above. Therefore, the AND circuit 33 outputs a serial clock that starts from typing 0 to 2 clocks earlier than the data to start displaying. The signal applied from the timing generation circuit 34 to the AND circuit 33 is a signal that becomes High level when the data to be displayed is typed when the display is to be started from the data of the memory person, and the display is started from the data of the memory B. If you want to,
A signal that goes high when you type 1 clock before the data that should start displaying.If you want to start displaying from the data in the memo IJQ, the signal goes high when you type 2 clocks before the data that you want to start displaying. This is the signal. By doing this, the three-phase serial clocks generated by the three-phase lock generation circuit 32 are always applied in the order of memory → memory B → memory C. Then, the read data passes through the R side of the changeover switches 20 to 22, passes through the switches 23 to 26, and is applied to the switch 37. On the other hand, the delay circuit 36 is connected to the other delay circuits 26 to 2.
8, and delays the same amount of time as the time from when the serial clock is input to the memory until the data is output. As described above, the signal applied from the timing generation circuit 34 to the delay circuit 36 goes high at the timing of the read clock of the data to start displaying.
Since this is a signal that becomes a high level, the output of the delay circuit 36 becomes a signal that becomes a high level at the timing when data to start displaying is output. In addition, the switch 37
is a switch that is turned ON when the signal from the delay circuit 36 becomes High level. Therefore, switch 3 is turned on at the timing when data to be displayed is output, and only data to be displayed is output.

The waveforms of each part during readout in Figure 1 are shown in Figure 2.
Fig. 6. Figure 2 shows Memo IJ.When reading out the data in order from Memo IJ with double magnification, Figure 3 shows Memo IJ.
When reading the data sequentially starting from data B and enlarging it twice, the fourth
The figure shows the case where the data is enlarged twice in order from the memo IJQ and read out, and Figure 5 shows the waveform of each part when the data is enlarged four times and read out from the memo IJC. It shows. In FIGS. 2 to 5, a is a continuous serial clock and is input to one side of the AND circuit 33.

b is a signal input from the timing generation circuit 34 to the AND circuit 33; in FIG. 2, it is the timing at which the data should be started to be displayed, and in FIG. Typing one clock faster, Figure 4.

In FIG. 5, the signal becomes Hi (h level) by typing two clocks earlier than the readout timing of the data to start displaying. C is the output signal of the AND circuit 33, and C is the output signal of the frequency divider circuit 19 and the changeover switch. 36 L
od applied to the side is a signal applied from the timing generation circuit 34 to the changeover switch 35 and the delay circuit 36, and goes high at the read timing of the hex data to start display.
H level belt. Therefore, the output of the changeover switch 35 is e
As shown, when the signal d is at a low level, it is a signal that is not frequency-divided, and when it is at a high level, it is a signal that is frequency-divided. This signal indicated by θ is applied to the three-phase lock generation circuit 32, and three-phase serial clocks indicated by f and h are applied to the memories 29 to 31, respectively. As a result, from the memories 29 to 31, the selector switch 2
via the R side of 0 to 22, then through the switches 23 to 25
The data is output in the order shown in the switch 37.
will be entered into. That is, in FIG. 2 1, from the timing of the data to start displaying, the timing changes from O-+BO to C0.
→Person 1→B1→C1→..., and in Figure 3 i, MU0 is output before the timing of the data to start displaying, and then BO is output from the timing of the data to start displaying. →CO→Person 1→B1→C1→... is output,
4 and 6, after M0 and BO are output before the timing of data to start displaying, CO→A1→B1→C from the timing of data to start displaying.
1→...Color output. However, in Figures 2 to 5, the delay time from when the serial clock is input to the memory until the data is output is ignored for the sake of clarity, but there are cases where the delay time cannot be ignored. , the operation is the same, only that the typing of i, j, is delayed by that amount. The signal shown with a square is the output of the delay circuit 36, which is a delayed version of the signal d, and becomes a signal that becomes High at the timing when the data to start displaying is output. As described above, the switch 37 is turned ON when the signal j is High, so the output of the switch 37 becomes a signal as shown by k. Therefore, in FIG. 2, data with the time axis doubled is output in the order of MU 0 → BO → CO →..., and the third
In the figure, data with the time axis doubled is output in the order of BO-+CQ → person 1 → B1 →..., and in FIG. In this order, data with the time axis expanded twice is output, and in Fig. 5, data with the time axis expanded four times is output in the order Go→Mu1→B1→C1→... It turns out.

Also, regarding the display end position, the timing generation circuit 3
By setting the signal applied to the delay circuit 36 from No. 4 to a low level at the timing of the data whose display should end, the display can be ended at an arbitrary position.

That is, when the timing generation circuit 34 sends a signal that becomes Low level when the data to be displayed is read and typed to the delay circuit 36, the output of the delay circuit 36 is output at the timing when the data to be terminated is output. Since the level becomes low and the switch 37 is turned off, subsequent data is no longer output. Therefore, the display end position can also be specified pixel by pixel.

As described above, according to this embodiment, three dual-port memories are connected in parallel to supply a three-phase serial clock, so the serial clock is faster than when only one memory is used. The frequency can be increased up to three times, serial data can be input/output at high speed, and the readout start position can be specified in units of one pixel. That is, when it is desired to start reading from the second memory, the serial clock is applied at a timing one clock earlier than the timing at which display should start, and the first data output from the memory is masked. By doing so, display can be started from the data in the second memory. Even when image data is enlarged and displayed, by starting the frequency division of the serial clock from the timing at which the display should start, regardless of the enlargement ratio, it is always one step ahead of the typing at which the display should start. It is only necessary to add the serial clock at a timing a few clocks earlier, and there is no need to change the timing depending on the magnification ratio. Also, if you want to start reading from the third memory, add a serial clock two clocks earlier than the timing when display should start, and mask the first two data output from the memory. , the reading can be started from the data in the third memory, and these timings do not need to be changed even when the magnification ratio is changed.

Therefore, the timing generation circuit can be realized with a simple configuration, and in this embodiment, there is no need to change the order in which the three-phase clocks are generated.

In this embodiment, three dual port memories are connected in parallel, but the number is not limited to three and any number may be used. Further, the type of memory used does not have to be a dual port memory, but any type of memory may be used as long as it can input and output serial data using a serial clock.

As described in detail, according to the present invention, it is possible to input and output image data to a memory at high speed, and there is no problem even if the readout start position is specified in units of one pixel. The practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of an image storage device according to an embodiment of the present invention, FIGS. 2 to 5 are operational waveform diagrams showing signals of each part of the embodiment, and FIG. A block diagram of an example of a storage device; FIG. 7 is a block diagram of an example of a memory capable of inputting and outputting serial data using a serial clock; FIG. 8 is a main part of a serial data input/output section in an example of a conventional image storage device Block diagram of FIG. 9. FIG. 1o is an operation waveform diagram showing signals of each part in FIG. 8. 3.29, 30.31...Memory that can input and output serial data using a serial clock, 5゜34
...Timing generation circuit, 16...Data register, 17...Pointer, 19...
...Frequency divider circuit, 20.21.22.35...
Changeover switch, 23°24.25.37...Switch, 26, 27. 28.36...Delay circuit, 32...3
Phase clock generation circuit, 33...AND circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person
Field 2 S se i ζ Q';E'S (-
Ku Tsune ξ ; Myo Ko b Sashiba Mi ・Ssa Fig. 7 f3 Fig. 10

Claims (1)

[Claims] n memories that can input and output serial data by inputting a serial clock are connected in parallel with all terminals other than the serial clock input terminal and the serial data input/output terminal, and the n-phase serial clock is connected to each of the memories. The serial data input/output terminals of each memory are all connected in parallel when serial data is input,
When outputting serial data, only the corresponding serial data input/output terminal of each memory is connected to the output by the n-phase serial clock.
≦n), there is a means for applying a serial clock (i-1) clocks earlier than the timing of the data to start displaying, and a means for applying the serial clock earlier than the timing of the data to start displaying at the output section. An image storage device comprising: an output gate means that prevents previous data from passing through; and a frequency division means that starts frequency division of a serial clock from the timing of data to start displaying.