RU1838891C - Device for image contrast control - Google Patents

Description

The invention relates to television technology and can be used in video information systems for image analysis and recognition.

The purpose of the invention is to expand the functionality of the device.

The invention is illustrated in the drawings, in which Fig. 1 shows a block diagram of a device according to the invention; in FIG. 2 - structural diagram of the detector; in FIG. 3 is a block diagram of an initial installation block; in FIG. 4 is a block diagram of a storage unit; in FIG. 5 is a block diagram of a selection block; in FIG. 6 is a structural diagram of a reference voltage driver; in FIG. 7 is a block diagram of a block for determining coordinates of information Regions; in FIG. 8 is a structural diagram of a mode selection block; Fig. 9 is a timing chart for explaining the operation of a mode block; in FIG. 10 is a block diagram of a control unit.

The image contrasting device comprises an analog-to-digital converter 1, a detector 2, an initial installation unit 3, a storage unit 4, a selection unit 5, a reference voltage generator 6, a clock generator 7, an information area coordinate determination unit 8, a buffer register 9, a mode selection unit 10 , a control unit 11, a digital-to-analog converter 12, a display unit 13, a recognition unit 14.

The device operates as follows.

An analog-to-digital converter 1 is, for example, an 8-bit analog-to-digital converter with a conversion time not exceeding the duration of one element of a television image. A digital signal at its output is generated synchronously with the clock pulses of the clock and in accordance with the reference voltages.

(L

WITH

oo

00

00

00

x

 Oj

the control inputs of block 1 that are output to the second and retium, respectively.

Detector 2 (Fig. 2) includes a first AND element 15, a first register 17, a first multiplexer 19, a first equalization circuit 21, which is a peak white level detector, as well as a second And element 16, a second register 18, and a second multiplexer 20, a second comparison circuit 22, which is a peak black level detector. When logic 1 is received at the fourth control input of detector 2 (this occurs at the beginning of any information area on each line), the multiplexer 19 enters a state in which the information present at its second input is transmitted to its output. Thus, the first comparison circuit 21 compares the reference digital1 code received at the second information input of block 2 with the digital code received at the first information input of block 2. As soon as the digital code received at the first information input of block 2 is larger than the reference digital code , the first comparison circuit 21 generates at its output A B a positive difference in logic levels, which goes to the third output of detector 2, as well as to one of the inputs of the first element And 15, to the other input of which clock cycles pulses arriving at the sixth synchronization input of block 2. According to the positive edge, which is formed in this case at the output of the first element And 15, a digital code is written to the first register 17 from the first information input of block 2. Synchronously with a positive difference in logic levels at the third output of block 2, logical O arrives at its fourth input, according to which the first multiplexer 19 switches to a state in which the information present at its first input is transmitted to its output. Thus, the comparison circuit 21 further compares between itself a digital code recorded in register 17 and a digital code from the first information input of block 2. As soon as the digital code at the first input of block 2 is larger than the digital code recorded in the first register 17, rewriting the code in the first register 17. Therefore, at the end of any information area for each line in the first register 17 will be written the maximum digital code from this area received at the first information input of block 2. The digital code recorded in he first register 17 is supplied to the first data output unit 2. The black level detector operates analogously detector white layer, but in the second register 18 will be recorded minimum digital code

from this information area, received at the first information input of block 2, since output A A is used in the second comparison circuit 22. The digital code recorded in the second register 18 is fed to the second information output of block 2.

The initial installation unit 3 (Fig. 3) includes a resistor unit 23, a first multiplexer 24 and a second multiplexer

5 25. If a logic zero is supplied to the control input of block 3, the first and second multiplexers 24 and 25 go into a state in which the information present at their first inputs is transmitted to their

0 exit. If a logical unit is supplied to the control input of block 3, then the first and second multiplexers 24 and 25 go into a state in which the information present on their output is transmitted to their output

5 second entrances. Therefore, if a logic zero is supplied to the control input of block 3, then the code 00 ... О is generated at the first output of block 3, and a code 11 ... 1 is generated at the second output, if a logical unit is fed to the control input of block 3 then information transmitted to its first and second inputs of block 3, respectively, is transmitted to its first and second outputs.

5 Storage unit 4 (Fig. 4) includes, for example, sixteen registers 26-41, combined in two groups: register UZBZZZ for storing a reference digital cDNA for a peak white level detector and registers 34-41 for storing a reference digital code for a pico detector black level. The number of registers in both groups corresponds to the number of information areas allocated by block 8. If the third

5 or the fourth control inputs of block 4 receives a logic zero, then, respectively, registers 26-33 or registers 34-41 will work in the recording mode of information, respectively, from the first or second

0 of the information input of block 4. If a logical unit is supplied to the third or fourth control inputs of block 4, then information 5 from the registers 26-33 and registers 34-41 will be read to the first and second information outputs of block 4. The control signals VK1 ... VK8 are used to select one of the registers 26-33 and one of the registers 34-41. in this case, those registers will be connected to the input and output of the unit to which the low acrgive level of one of the control signals VK1 ... VK8 is supplied. Moreover, for each information area in block 4, only two corresponding registers will be selected: one from the group of registers 26-33 and one from the group of registers 34-41.

The selection block 5 (Fig. 5) includes a block of resistors 42, a first multiplexer 43, and a second multiplexer 44. If a logic zero is supplied to the control input of block 5, then the multiplexers 43 and 44 go into a state when their output is transmitted information from their first entrances. If a logical unit arrives at the control input of block 5, the first and second multiplexers 43 and 44 go into a state when information from their second inputs is transmitted to their output. Therefore, if a logic zero is supplied to the control input of block 5, then the code 11 ... 1 is generated at the first output of block 5, and the code 00 ... O at the second output. If a logical unit is supplied to the control input of block 5, then information from the first and second information inputs will be transmitted to the first and second information outputs of block 5.

The reference voltage generator b (Fig. 6) includes the first and second digital-to-analog converters 45 and 46, as well as the first and second amplifying elements 47 and 48. The operation of the unit is to convert digital information to the first and second information inputs block 6 to the analog reference voltages for block 1.

The clock generator 7 is, for example, a clock selector for extracting frame and line clocks from a full television signal to the first and second outputs of the clock generator 7, as well as a clock generator, while clock pulses from the output of the clock generator go to the third output of the clock generator 7 in-phase with horizontal sync pulses.

Unit 8 for determining the coordinates of information areas (Fig. 7) includes, for example, frame memory 72 and computer 73. Unit 8 operates as follows. At the command of the operator or software, the computer 73 generates a reset signal at the second output of block 8. Further, with the arrival of the first frame sync pulse after the Reset signal, the television frame of the fourth information input of block 8 is recorded in the frame memory 73. After the television frame is recorded in the frame memory 72, the computer 73 determines information areas on it containing images of objects whose contrast need to improve. The coordinates of the information areas can also be set from external devices, and they arrive at the fifth information input of block 8. After determining the coordinates of the information areas, the computer 73 encodes the pixels of the recorded frame in accordance with their belonging to a particular selected information area. This is done, for example, in the following order:

Area number Code pixel background 00000000 1- area 00000001 2- area 00000010

256 area

11111111

After completing the above operations, the computer 73 generates a Ready signal at the first output of block 8, and with the arrival of the next frame pulse to the information output of block 8

pixel codes of the recorded television frame begin to arrive in scan order. Read pixels from the frame memory 72 is carried out before the formation of the next

Signal Reset. The recording and reading of the pixel codes of a television frame is carried out synchronously, with frame and horizontal sync pulses.

The buffer register 9 represents

a register with parallel loading of data, the information is recorded into which by the positive difference of clock pulses at its synchronization input.

The mode selection unit 10 (Fig. 8) includes, for example, an OR element 50. a counter 51 and a decoder 52. The Reset signal resets the counter 51, which then goes into the counting state of the frame clock arriving at the third input of block 10, since its counting enable input HS receives a logical unit from the output of the OR element 50, one of whose inputs receives a logical unit with

the output of the decoder 52, and on the other - a low logical signal level Ready. As the next frame sync pulse arrives at the third input of block 10, the counter state will increase by one and by

the output Q i of the decoder 52 has a logic zero, thus the frame clock count is disabled by the counter 51. The frame clock count will resume when on. the first input of block 10 will receive a high active signal level Ready.

In addition to reading the counter 51, the deflector 52 generates at the first, second and third outputs of block 10, respectively, the control signals P1, P2, PZ (active level-low), which translates the device into the first, second and third modes of operation, respectively.

Timing diagrams explaining the operation of the mode selection unit 10 are shown in FIG. 9. After the end of the pulse signal, the Reset (Fig. 9a), according to the first frame sync pulse (Fig. 9.6), the control signal P1 (Fig. 9d) is activated for a duration of T1, which puts the device into normal operation. The device operates in the first mode until the Ready signal is activated (Fig. 9, c), which goes into the active state after block 8 determines the coordinates of the information areas. Further, according to the first frame sync pulse (Fig. 9, e), which arrived after the Ready signal was activated, the control signal P1 (Fig. 9, d) goes into a passive state, and the control signal P2 (Fig. 9, d) - o active state. The duration T2 of the signal P2 is equal to the time of one frame. According to the second frame sync pulse (Fig. 9.6), which came after the activation of the Go-too signal, the control signal P2 (Fig. 9, e) goes into the passive state, and the control signal PZ (Fig. 9, e) - in an active state. The device operates in the third mode of operation until the next Reset signal arrives (Fig. 9a), under the action of which the Ready signal (Fig. 9c) and the control signal RE (Fig. 9f) pass into the passive state.

The control unit 11 (FIG. 10) includes a first OR element 53, a register 54, an inverter 55, a decoder 56, a comparison circuit 57, a first trigger 58, an inverter 59, a second and third OR element 60 and 61, a second and third trigger 02 and 63, multiplexer 64, elements AND 65-69, fourth and fifth elements OR 70 and 71. The operation of the unit is as follows. Signal Reset reset to zero; register 54 and the first trigger 58. Further, with the arrival of signal P1, the operation of the And 66-69 elements on one of the inputs is blocked. Thus, at the first output of block 11, a logical O is generated using the fourth OR element 70, one of the inputs of which receives a logical O from the output of the And 66 element, and the other input receives a logical O from the output of the And 67 element. At the second output of the block 11 a logical zero is formed using the OR element 71, one of the inputs of which receives a logical zero from the output of the And 68 element, and

to the second input, a logical zero from the output of the And 69 element. At the third output of block 11, all signals VK1 ... VK8 are formed of a low active level, since under the action

of signal P1, the multiplexer 64 transitions to a state when the information present at its first input is supplied to its output. At the fourth output of block 11, a logical zero is generated using element AND 65, one of the inputs of which receives a logical zero from the output of trigger 58, and to the second, a signal from output 0 of decoder 56.

With the arrival of the second input of block 11

5 of signal P2, the first OR 53 element is allowed to work on one of its inputs, to the other input of which pulses from the comparison circuit 57 are received. These pulses are transmitted through the OR 53 element to the clock input of register 54, which records a digital code from the information input of block 11 the positive edge of the clock pulse generated at the output of the comparison circuit 57, which compares the digital code of the information input of block 11 with the digital iodine recorded in register 54. If they do not match, it forms a positive edge ble levels na.svoem output A-FT, which

0 sets triggers 62 and 63 to a single state. In this case, a logical zero from the inverse output of the trigger 62, arriving at one of the inputs of the OR element 60, allows the latter to work on the second input,

5 to which the signal from the fifth input of block 11 arrives. With the positive difference arriving at the fifth input of block 11, a logic zero is written to the trigger input 62 of the trigger 62. Similar to

0, a logical zero is written to the third trigger 63 upon receipt of a positive edge at the sixth input of block 11. The signal from the output of the trigger 62 through the AND 6G element and the OR element 70 goes to the first

5 the output of block 11, and the signal from the output of the trigger 63 through the And 67 element and the OR element 71 is fed to the second output of the block 11. The decoder 56. decrypts the code from the information input of the block 11 to the voltage

0 low logic level, appearing on one of its outputs 0-8. The number of the selected decoder output corresponds to the number of the current information area or background. The signals from the outputs de5 of the encoder 56 through the multiplexer 64 are fed to the third output of block 11, generating signals VK1..VKZ. Using trigger 58 and AND element 65, a logical zero is generated at the fourth output of block 1T.

With the arrival of the RH signal, the first flip-flop 58 is set to a single state. At the same time, at the first output of block 11, a logical unit is formed, buying up (Looking at the output of the fourth OR element TiO, which is blocked one by one from the input of the logical unit from the output of the And element 67, since one of the inputs of the last receives a high level of signal P1 , and On the second logical unit from the output of the trigger 58. In the same way, a logical unit using the fifth OR element is formed on the second output of block 11, Control signals VK1 ... 8K8 on the third output of block 11 are formed in the same way as in the second operation mode Signal on Thursday The second output of block 11 repeats the signal from the output 0 of the decoder 56. Block 11 is in the third mode until the next Reset signal arrives.

 The display unit 13 is a standard video monitoring device.

In general, the image contrasting device operates as follows: the unit 8 for determining the coordinates of the information areas by the operator’s command or programmatically generates a reset signal at its second output, which sets unit 10 and unit 11 to the Initial state. With the arrival of the first after the Reset frame sync pulse, the mode selection unit 10 sets the signal P1 and thereby puts the device into the first operation mode. In this mode, using the initial installation unit 3 in the registers 26-33 of the storage unit 4, the code 00 ... О is written. and to the registers 34-41-code 11 ... 1, which serve as the initial Reference codes for respectively the peak detectors of the levels of white and black. In this mode, the selection block 5 generates a code 11 ... 1 on its first output, and a code 00 ... О on the second output, which corresponds to the limiting reference voltages, which are supplied from the first and second outputs of the reference voltage generator b, respectively to the second and third inputs of the analog-to-digital converter 1. In this case, the analog-to-digital converter 1 operates in the signal conversion mode with the maximum possible dynamic range, corresponding to the nominal amplitude of the video signal. In P1 mode, a television frame is recorded in the frame memory 72 of the information area coordinate unit 8. After recording a television frame, the computer 73 determines information areas on it that contain images of objects whose contrast needs to be increased, or receives the coordinates of information areas from external devices at the second input of the device, numbers these 5 areas, and encodes pixels in accordance with their belonging to one or another information area and generates a Ready signal. Under the action of the Ready signal, the mode selection block 10

0 sequentially transfers the device to the second and third modes of operation, respectively, by signals P2 and RE (Fig. 9). In these modes of operation from block 8 determine the coordinates of the information areas through

5, a buffer register 9 to the information input of the control flea 11 is read in scanning order, pixel codes synchronously with the video signal supplied to the first input of the device. The pixel code corresponds to the number of the information area to which it belongs.

In the second mode of operation, the control unit 11 determines the beginning of any information area for each line and its

5 number, the codes of the pixels coming to its information input from the buffer register 9 are decoded and generates control signals VK1 ... VK8, which are selected in the storage unit 4 one register

0 for a white level code and one register for a black level code for each information area. In addition, the control unit 11 at the beginning of any information area for each line forms a logical unit at its first and second outputs, which puts the registers selected in the storage unit 4 into the reading mode of the initial reference codes recorded in them. The initial reference code for the peak white level detector from the first output of the storage unit 4 is supplied to the second information input of the detector 2, and the initial reference code for the peak black level detector from the second output of the block

5 4 of the storage is fed to the third information input of the detector 2. The logic units from the first and second outputs of the control unit 11 peak detectors are put into operation, in which they compare the digital code received at the first information input of the detector 2 with the corresponding initial reference codes .

As soon as the stroke at the first input of detector 5 exceeds the reference code of the peak white level detector, it will go to the first information output of detector 2, and a positive logical level difference will be formed at its third akho ..- j. The initial installation unit 3 is

in a state where the code from the first output of the detector 2 is transmitted to the first input of the storage unit 4. The positive differential control unit 11 from the third output of the detector 2 generates a logic zero at the first output, which transfers the selected register and the storage unit 4 to the initial reference code for the peak white level detector to write the code from the first output of detector 2. In addition, the logic zero from the first output of the storage unit 11 switches the peak white level detector to an operation mode in which the maximum pixel code from the current information area arriving at the first information is output to the first output of the detector 2 detector descent 2. This code will be recorded in the selected register for storing the white level code of the storage unit 4. Thus, at the end of any information area for each line in the selected register of snore block 4, the maximum pixel code from this area will be recorded. At the beginning of the next line of the same information area, this code will be the new reference code for the peak white level detector. At the end of the last line of the information area in the selected register of the storage unit 4, a code will be written that corresponds to the white level from this area,

As soon as the code at the first input of detector 2 becomes less than the reference code of the peak black level detector, it will arrive at the second information output of detector 2, and a positive logic level difference will be generated at its fourth output. The initial setting unit 3 is in a state where the code from the second output of the detector 2 is transmitted to the second input of the storage unit 4. Control unit 11: for a positive difference from the fourth output of detector 2, generates a logical zero at the second output, which transfers the register selected in storage unit 4 with the initial reference code for the peak black level detector to the code recording mode from the second output of detector 2. In addition, the logical zero from the second output of the storage unit 11 transfers the peak level-dimensional detector to the operating mode, about which the minimum pixel code from the current information area arriving at the first ormatsionny input detector 2, this code will be written into the selected register of the storage unit 4 storing the black level code. Thus, at the end of any information area for each line in the selected register of the storage unit 4, the minimum pixel code from this area will be recorded. At the beginning of the next line of the same information area, this code will be the new reference code for the peak black level detector. At the end of the last line of the information area, a code will be written in the register of the storage unit 4 selected for it, which corresponds to the black level from this area.

The selection unit 5, the driver 6 of the reference voltage and the analog-to-digital converter 1 in the second mode of operation work similarly to the first mode.

5 As a result, the white level and black level codes of these areas will be recorded in the registers of the storage unit 4 selected for each information area.

In the third operating mode, the control unit 11, by analogy with the second mode, selects registers from the storage unit 4 for each information area and transfers them to the read mode by signals at the first and second outputs. Read 5 from the registers the information corresponding to the black and white level for each information area is supplied through the selection unit 5 to the first and second inputs of the reference voltage generator 6. WITH

0 of the first and second outputs of the driver; the reference voltages are supplied respectively to the second and third control inputs of the analog-to-digital converter 1. Thus, the input signal is within

5 of each information area is converted by an analog-to-digital converter 1 using a full conversion scale, i.e. maximum contrast. Analog-to-digital converter output 1 converted video signal

arrives at the input of the recognition unit 14 and

through a digital to analog converter 12

to the input of the video monitoring device 13.

Independent contrasting of 5 portions of the television frame (information areas) improves the efficiency of image analysis and recognition.

Claims (1)

The claims An image contrast device comprising an analog-to-digital converter, a detector, a reference voltage generator, a display unit, and a clock generator, the input of the clock generator and the input of the analog-to-digital converter being the first information input of the device, the information output of the analog-to-digital converter is connected to the first information input detector, first and second outputs the reference voltage driver is connected respectively to the second and third control inputs of the digital-to-digital converter, the synchronization input of which is connected to the clock output of the clock generator, characterized in that, in order to expand the functionality, an initial installation block is introduced, the first and second Information inputs of which connected respectively to the first and second information outputs of the detector, the storage unit, the first and second information inputs of which are connected but you p er m; and secondly, with the information outputs of the initial installation unit, the first and second information outputs are connected respectively to the second and third information inputs of the detector and the first and second inputs of the selection unit .. the first and. the second outputs of which are connected to /, respectively, with the first and second information inputs of the reference voltage generator, the outputs of which are connected to the second and third inputs of the analog-to-digital conversion, ate a unit for determining the coordinates of information areas, the first and second inputs of which are connected. clock to the first and second outputs of the synchro generator, the third information input is connected to the output of the buffer register, the first and second outputs are connected to the first and second inputs of the mode selection block, the third information output q is connected to the input of the buffer register, the fourth information input is connected to the inputs of the recognition unit, the input of the digital-to-analog converter and the first input of the detector, and the fifth input is the second information input of the device, the synchronization input is connected to the clock output of the clock and the sync input buffer register, a mode selection unit, the first and second control inputs of which are connected respectively to the first and second outputs of the unit for determining the coordinates of information areas, one third input connected to a first output clock, a first output connected to a control input of the initial setting unit, a control unit Infor- matsirnny input coupled to 5 information output of the buffer register, the first, second and third control inputs are connected respectively to the first, second and third outputs of the mode selection unit, the fourth control 0, the input is connected to the second output of the unit for determining the coordinates of the information areas, the fifth and sixth inputs are connected respectively to the third and fourth outputs of the detector, the first and second outputs 5, respectively, to the third and fourth control inputs of the storage unit, as well as, respectively, to the fourth and fifth control inputs of the detector, the third output with the fifth control input of the block 0 storage, the fourth output is with the control input of the selection block, the recognition block, the information input of which is connected to the information output of the analog-to-digital converter, block 5 digital-to-analog conversion, the information input of which is connected to. an analog-to-digital conversion information output, the output is connected to an input of the display unit. Fi $ .1 FIG. 4 J L 75 L JL ±. lGoto & s , Reset1 J ,5 . 7 FIG. 9 GL Reset a y / e / a5 Pf v. „P 331 , P3 3 t  V -rt -2 7e . l.,., J