JPH0581113B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal storage device for storing video signals in a storage circuit.

[Conventional technology]

For example, when making a hard copy of a video displayed by a video signal, the video signal must first be stored in a storage circuit and later read out at low speed and applied to the copy device due to limitations in the operating speed of the copying device. In this way, video signals may be stored in the storage circuit for various purposes. By the way, there are two types of video signals: interlaced (interlaced scanning) and non-interlaced (non-interlaced scanning), and the difference between these systems must be taken into account when writing and reading operations of the memory circuit. That is,
In the case of the interlace method, the video signal consists of two fields that constitute one image, and in the first field, signals related to even-numbered scanning lines are generated sequentially,
In the second field, signals related to odd-numbered scanning lines are sequentially generated. On the other hand, in the case of the non-interlace method, one field constitutes one image, and the signals are generated in the order of scanning lines. Therefore, it is necessary to make the addressing order when writing to the memory circuit the same as the addressing order when reading from the memory circuit.

[Problem that the invention seeks to solve]

By the way, if one of the interlaced and non-interlaced video signals is always stored in the storage circuit, there is no problem because it is sufficient to design write and read address circuits suitable for that system. However, it would be convenient if the storage device had versatility so that it could automatically store both interlaced and non-interlaced video signals in the storage circuit.

Accordingly, an object of the present invention is to provide a video signal storage device capable of storing both interlaced and non-interlaced video signals in a storage circuit.

[Means for solving problems]

In order to solve the above problems, the video signal storage device of the present invention includes a pulse generator that generates two pulses during the horizontal synchronization period of the video signal, and a pulse generator that identifies whether the video signal is an interlace format or a non-interlace format. a first identification circuit for determining whether the video signal is an interlaced field, a second identification circuit for identifying whether it is an odd field or an even field, and a synchronization of the output signal of the pulse generator or the video signal according to the output signal of the first identification circuit. a first selection circuit that selects a signal; a counter that counts the output signal of the first selection circuit; and a storage circuit that determines an address regarding the scanning line order of the video signal based on the output signal other than the least significant bit of the counter and the output signal of the second selection circuit, and stores the video signal. It is growing.

[Effect]

In the present invention, when the first identification circuit identifies that the video signal is of the interlaced format, the first and second selection circuits select the output signal of the pulse generator and the output signal of the second identification circuit, respectively. Therefore, since the counter counts two pulses for each scanning line and replaces the least significant bit of the count output with the output signal of the second identification circuit, the address regarding the scanning line order of the storage circuit is an odd number for each field. Or every second address is an even numbered address. Therefore, the video signal can finally be stored in the storage circuit in the same state as when the video was displayed, that is, in the order of the scan lines of the video. Also,
When the first identification circuit identifies that the video signal is of a non-interlaced format, the first and second selection circuits select the synchronization signal of the video signal and the least significant bit of the output signal of the counter, respectively. Therefore, the counter counts the synchronization signals, and the output of this count directly becomes an address regarding the scanning line order, so that the video signals can be stored in the storage circuit in the order of the video scanning lines. Therefore, according to the present invention, the video signal can be stored in the storage circuit in the same state as the video is displayed, regardless of whether it is an interlace method or a non-interlace method. As a result, the read operation of the memory circuit is
This means that there is no need to consider differences in methods.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of a preferred embodiment of the present invention. The video signal is supplied to a comparator 14 and a sync separation circuit 16 via an input terminal 10 and a buffer amplifier 12. In this embodiment, since the video signal has two levels, white and black, the comparator 14 compares this video signal with a reference voltage Vref (an intermediate voltage between the white level and the black level) to adjust the level of the video signal. The synchronization separation circuit 16 is a clamp circuit or a comparison circuit, and separates a composite synchronization signal (including horizontal and vertical synchronization signals) from the video signal. The sampling pulse generator 18 generates sampling pulses synchronized with the horizontal synchronization signal during the horizontal scanning period in response to the output signal from the synchronization separation circuit 16. This sampling pulse is generated, for example, 2048 (=2 ¹¹ ) times in one horizontal scanning period. Sampling circuit 20 responds to the sampling pulse from sampling pulse circuit 18 by
This is a shift register that samples the video signal from. The storage circuit 22 is the sampling circuit 20
This is, for example, a random access memory (hereinafter simply referred to as RAM) that stores the output signals of , and its address is specified by a horizontal address signal and a vertical address signal. The horizontal address space of this RAM is 2048 and the vertical address space is 1024
(=2 ¹⁰ ), so an image of 2048 pixels in the horizontal direction and 1024 scanning lines in the vertical direction can be stored in correspondence with the display. The stored contents of this storage circuit 22 are sequentially read out and supplied to a hard copy device 24.

On the other hand, the field identification/vertical synchronization circuit 26
In response to the composite synchronization signal from the synchronization separation circuit, a field identification signal F indicating whether the current field is an even field or an odd field and a vertical synchronization signal V are generated. In addition, the field identification signal F
is a logic signal that is inverted for each field when the video signal is of an interlaced format; for example, it is at a high level during odd-numbered field periods and is at a low level during even-numbered field periods. Furthermore, when the video signal is of a non-interlaced format, the field identification signal F always maintains either a high level or a low level, regardless of the field, depending on the state in which the video signal is first received. Control circuit 2
8 is control of writing and reading of the memory circuit 22;
It generates a control signal W/R for controlling the copy start of the hard copy device 24 and controlling the selection of a multiplexer, which will be described later.

The interlace identification circuit 30 determines whether the input video signal is an interlace format or a non-interlace format in accordance with a field identification circuit F from the field identification/vertical synchronization circuit 26 and a control signal W/R from the control circuit 28. Generates an identification signal. This identification signal is low level in the interlaced system and is non-
High level in interlaced format. The pulse generator 32 receives the composite synchronization signal from the synchronization separation circuit 16 and the identification signal from the interlace identification circuit 30, and generates two pulses in the horizontal synchronization period. On the other hand, hard copy device 2
4 generates a horizontal read clock HY for horizontal addresses, a horizontal reset signal HR, a vertical read clock VY for vertical addresses, and a vertical reset signal VR in order to read the memory circuit 22 at low speed.

A multiplexer (hereinafter simply referred to as a selection circuit)
A MUX 36 selects the output signal of the pulse generator 32 in the case of an interlace method, and selects the sync signal from the sync separation circuit 16 in the case of a non-interlace method, according to the identification signal from the interlace identification circuit 30. select. MUX38
selects the output signal of the MUX 36 in the write mode and selects the output signal of the hard copy device 24 in the read mode according to the control signal W/R from the control circuit 28.
Select the vertical readout clock VY from On the other hand, in response to the control signal W/R from the control circuit 28, the MUX 40 selects the vertical synchronization signal V from the field identification/vertical synchronization circuit 26 in the write mode, and selects the vertical synchronization signal V from the field identification/vertical synchronization circuit 26 in the read mode.
Select the vertical reset signal VR from . 10-bit counter 4 for vertical address of memory circuit 22
2 receives the output signals of MUX 38 and 40 at its clock terminal and reset terminal R, respectively. The MUX 44, which is a selection circuit, selects the field identification signal F from the field identification circuit 26 when the writing mode is an interlace method, in accordance with the control signal WR from the control circuit 28 and the identification signal from the interlace identification circuit 30. In the non-interlaced write mode and in the read mode, the least significant bit of the output signal of the counter 42 is selected. The count output of the counter 42 excluding the least significant bit and the output of the MUX 44 are combined to form a vertical address signal for the memory circuit 22. Note that MUX 44 becomes the least significant bit of the vertical address signal.

In the write mode, the MUXs 46 and 48 select the sampling pulse from the sampling pulse generator 18 and the synchronization signal from the sync separation circuit 16, respectively, in response to the control signal W/R from the control circuit 28, and read them. In the mode, the horizontal read clock HY and horizontal reset signal HR from the hard copy device 24 are selected, respectively. 11-bit counter 50 for horizontal address of memory circuit 22
is connected to its clock terminal and reset element R.
It receives the output signals of MUX 46 and 48 and uses the count output as a horizontal address signal.

Next, the operation of the circuit shown in FIG. 1 will be explained in more detail. First, in the write mode, the counter 50 is
Since the sampling pulses are counted and reset by the synchronizing signal, the horizontal addresses in the memory circuit 22 are sequentially advanced in accordance with the sampling pulses for each scanning line of the video signal. On the other hand, in the case of the interlaced system, the counter 42 counts the output signal of the pulse generator 32, and is reset by the vertical synchronizing signal V. As mentioned above, since the pulse generator 32 generates two pulses during the horizontal synchronization period, the counter 42
is counted by two for each scanning line, that is, for each horizontal synchronization signal. Also, since the MUX 44 selects the field identification signal F as the least significant bit of the vertical address signal instead of the least significant bit of the counter 42, the identification signal F is at a low level in even-numbered fields, and the even-numbered scanning An even vertical address corresponding to a line is selected for each horizontal synchronization signal. Similarly, in odd fields, the identification signal F is at a high level,
An odd numbered address corresponding to an odd numbered scanning line is selected for each horizontal synchronization signal. In the case of non-interlacing, counter 42 counts the synchronization signals and is reset by vertical synchronization signal V, and MUX 44 selects the least significant bit of the output signal of counter 42. Therefore, the vertical address is the output signal of the counter 42 itself, and simply advances the vertical address by one for each horizontal synchronization signal.

By the address signals of counters 42 and 50,
The memory circuit 22 stores (writes) video signals, but in the interlaced method, writing is performed at every other scanning line (vertical address), and in the non-interlaced method, consecutive scanning lines are sequentially written in consecutive vertical addresses. Do the following. Therefore, the storage state of the video signal in the storage circuit 22 is the same state (address arrangement) as the video display, regardless of whether it is an interlace method or a non-interlace method.

In read mode, counters 42 and 50:
Read clock from hard copy device 24
Count VY and HY and reset signals VR and HR
The MUX 44 is reset by the counter 42.
, the storage circuit 22 can be read using the reading method required by the hard copy device 24. It should be noted that during this readout, it is not necessary to consider whether the video signal is interlaced or non-interlaced. To perform reading in the horizontal direction, the horizontal read clock HY may be made faster than the vertical read clock VY, and to perform read in the vertical direction, the vertical read clock VY may be made faster than the horizontal read clock HY.

FIG. 2 shows the field identification/vertical synchronization circuit 26.
FIG. 3 is a circuit diagram of the circuit, and FIG. 3 is an operating waveform diagram thereof. Composite synchronization signal W1 from synchronization separation circuit 16
is applied to the clock terminal of monostable multivibrator 52 and the data terminal D of flip-flop 54. In addition, if the video signal is of the interlaced format, the area around vertical blanking is W1 in Figure 3.
The waveforms are as shown in FIG. 2, where the upper waveform shows a change from an even field to an odd field, and the lower waveform shows a change from an odd field to an even field. Monostable multivibrator 5
2 makes the pulse width of the composite synchronization signal W1 constant to prevent errors in subsequent circuits. Phase Lock Loop (PLL) Integrated Circuit (IC) 56
is, for example, a 4046 type, which generates a pulse W3 having twice the frequency of the horizontal synchronizing signal at pin 4, and generates a voltage at pin 13 corresponding to the phase difference between the input signals at pins 3 and 14. Since the input voltage at pin 9 of IC56 controls the phase of the output signal at pin 4, pin 1
Apply a voltage of 3 to pin 9. The flip-flop 58 divides the pulse W3 of the IC 56 by half to make it the same frequency as the horizontal synchronizing signal, and outputs the Q signal W2.
is applied to data terminals D of flip-flops 62 and 64.

On the other hand, since the phase of the output pulse W3 at pin 4 of the IC 56 is inverted by the inverter 66, the output W4
becomes a pulse delayed by half a period from pulse W3. With this pulse W4, flip-flops 54 and 6
2, so flip-flop 54
The Q output of the flip-flop 62 becomes the vertical synchronizing signal W6 (V), and the Q output W5 of the flip-flop 62 becomes the pulse W2 delayed by one-fourth period. Also, since pulse W6 clocks flip-flop 64, its Q output becomes field identification signal W7(F). OR gate 70 receives pulses W5 and W6 along with the output of monostable multivibrator 52, so that the equivalent pulses of the video signal are removed from its output. Similarly, since OR gate 60 receives pulses W5 and W6 along with the output of flip-flop 58, its output is free from the effects of equivalent pulses. Pins 3 and 14 of IC 56 receive the outputs of OR gates 60 and 70, respectively, to ensure that pulse W3 is synchronized to the horizontal sync signal. In addition, pins 3 and 1 of IC56
When the 4 pulses are out of sync, pin 1 goes low and the flip
Reset flops 54 and 62. Therefore, when pulse W3 is not completely synchronized with the horizontal synchronization signal, this circuit 26 stops operating.

In this way, the field identification/vertical synchronization circuit 26 in FIG. 2 generates the vertical synchronization signal V, and in the interlaced system, the level is inverted for each field, and the field identification/vertical synchronization circuit 26 in FIG. Field identification signal F indicating the field
occurs. In addition, in the non-interlace method, depending on the state when the composite sync signal is added,
Field identification signal F is always maintained at either a low or high level. Note that the upper and lower waveforms of the pulses W6 and W7 correspond to the upper and lower waveforms of the pulse W1, respectively.

FIG. 4 is a circuit diagram of the interlace identification circuit 30. Flip-flop 82 receives a positive voltage (high level) at its data terminal D and is clocked by field identification signal F. On the other hand, flip-flop 84 receives a positive voltage at its data terminal D and is clocked by field identification signal F whose phase is inverted by inverter 80. These flip-flops 82 and 84 are controlled by control signals W/R
is reset in read mode.
OR gate 86 receives the Q outputs of flip-flops 82 and 84 and generates an interlace identification signal.

When the write mode begins, flip-flops 82 and 84 are released from reset. If the video signal is of an interlaced format, the field identification signal F is inverted for each field, so that at least one of the flip-flops 82 and 84 is clocked within two field periods, and the Q output of at least one of them is high. level. Therefore, the output signal of NOR gate 86, the interlace identification signal, goes low. On the other hand, if the video signal is of a non-interlaced format, the field identification signal F is maintained at either a high or low level and does not change, so the flip-flop 8
Even when the resets of 2 and 84 are released, their Q outputs both remain low. Therefore, the interlace identification signal from NOR gate 86 is high. In this manner, it is possible to identify whether the circuit of FIG. 4 is an interlaced type or a non-interlaced type.

FIG. 5 is a circuit diagram of the pulse generator 32, and FIG. 6 is a waveform diagram illustrating its operation. When the video signal is of an interlace type, the interlace identification signal is at a low level, so that both monostable multivibrators 90 and 92 can be triggered. When the horizontal synchronization signal P of the composite synchronization signal from the synchronization separation circuit 16 triggers the multivibrator 90, its output N triggers the multivibrator 92. AND gate 94 receives synchronization signal M and output O of multivibrator 92, so its output P generates two pulses during the horizontal synchronization period. Note that the time constants of the multivibrators 90 and 92 are selected so that their output pulse width is approximately one-third of the horizontal synchronization period.

Although the preferred embodiments of the present invention have been described above, various modifications and changes can be made without departing from the gist of the present invention. For example, the memory circuit 22
Rather than using horizontal and vertical addressing (row and column addressing), the address of a memory circuit with a series of address spaces is divided into upper bits and lower bits, which correspond to vertical and horizontal addresses, respectively. It can be anything. Also, the comparator 14 is removed and the sampling circuit 20
An A/D converter may be inserted between the memory circuit 22 and the memory circuit 22. Furthermore, a circuit such as that disclosed in Japanese Utility Model Publication No. 57-37557 by the applicant of the present application may be used as the field identification circuit. Furthermore, the interlace identification circuit can be constructed arbitrarily by combining various logic elements.

〔Effect of the invention〕

As described above, according to the present invention, video signals of both interlaced and non-interlaced formats can be stored in the storage circuit without any special operation by the operator. Furthermore, since the storage state of the memory circuit is the same regardless of these methods, there is no need to change the reading method depending on the method. Therefore, the configuration of the readout circuit becomes simple.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment suitable for the present invention, FIG. 2 is a circuit diagram of the field identification/vertical synchronization circuit used in FIG. 1, and FIG. 3 is a waveform diagram explaining the operation of FIG. 2. 4 is a circuit diagram of the interlace identification circuit used in FIG. 1, FIG. 5 is a circuit diagram of the pulse generator used in FIG. 1, and FIG. 6 is a waveform diagram explaining the operation of FIG. 5. In the figure, 22 is a memory circuit, 26 and 30 are identification circuits, 32 is a pulse generator, 36 and 44 are selection circuits, and 42 is a counter.

Claims (1)

[Claims] 1. A pulse generator that generates two pulses during the horizontal synchronization period of the video signal, a first identification circuit that identifies whether the video signal is an interlace format or a non-interlace format, and an odd-numbered pulse generator that identifies whether the video signal is an interlace format or a non-interlace format. a second identification circuit for identifying whether the field is an even field or an even field; a first selection circuit for selecting the output signal of the pulse generator or the synchronization signal of the video signal according to the output signal of the first identification circuit; a counter that counts the output signal of the first selection circuit; a second selection circuit that selects the least significant bit of the output signal of the counter or the output signal of the second identification circuit in accordance with the output signal of the first identification circuit; a storage circuit that determines an address regarding the scanning line order of the video signal based on the output signal other than the least significant bit of the counter and the output signal of the second selection circuit, and stores the video signal;
When the video signal is in an interlaced format, the first and second selection circuits select the output signal of the pulse generator and the output signal of the second identification circuit, respectively, and when the video signal is in a non-interlaced format, A video signal storage device, wherein the first and second selection circuits select the synchronization signal of the video signal and the least significant bit of the output signal of the counter, respectively.