KR960004508B1 - Memory real time transfer control circuit in multi-screen - Google Patents

Abstract

The image data of 1 horizontal line is transferred completely by expanding limited horizontal address through vertical axis. The control circuit includes a transmission clock gating circuit(118) for sending input clock signal to a serial clock terminal(SC), a transmission clock counter(125) for receiving a frame division mode data and for counting the loaded data, a counter controller(136) for sending load data to the transmission clock counter(125) by operating a multi control signal and frame division mode control signal, and a transmission control signal generator(150) for decoding the load data to generate a transmission control signal.

Description

Memory Real-Time Transfer Control Circuit for Multi-Screen Functions

1 is a diagram illustrating a division state of a multi-screen.

2 is a state diagram of image data storage in a horizontal period in the image memory.

3 is a real-time transmission control circuit diagram according to the present invention.

4 to 7 are waveform diagrams for explaining the operation of FIG.

* Explanation of symbols for main parts of the drawings

118: transmission clock gating circuit 125: transmission clock counter

136: counter control circuit 150: transmission control signal generating circuit.

The present invention relates to an image memory control circuit of an image display apparatus capable of displaying a multi-screen, and in particular, to transmit image data of one horizontal line without missing the horizontal address area by extending it to the vertical side. A real time transfer control circuit of a video memory.

In general, a video display device, for example, a digital video cassette recorder (VCR) or a digital television, has a function of dividing and displaying one screen into 4 screens, 9 screens, and 16 screens such as 1a, 1b, and 1c. It is getting added. As described above, dividing and displaying one screen into a plurality of screens is called a multi-screen display.

FIG. 1A shows a state in which a video signal of one video screen is divided and reduced into four screens 1 to 4, and FIG. 1B shows a state in which video signal of one video screen is divided and reduced to nine screens 1 through 9. 1C shows a state in which a video signal of one video screen is divided and reduced into 16 screens.

In order to divide and display one video screen into 4 screens, 9 screens, and 16 screens as shown in FIGS. 1a, 1b, and 1c, sampling of an image signal input in the form of analog, according to the screen division mode, is known. Digital conversion by clock should reduce the amount of video data for one video screen. In addition, the digitally converted image data may be stored in the image memory as another read clock in a screen division mode, and the data stored in the image memory may be read by a normal read clock to display the reduced-divided screen on the monitor. do.

In this case, the video memory may be used by combining a plurality of video memories having a storage area of a predetermined amount (storage amount as bit units), or may use a dual port memory having a capacity of 1 Mbit (M-Bit). have. The dual port memory has a random access memory (RAM) for accessing parallel data and a sam port (SAM port: serial access memory) for accessing serial data. The dual port RAM as described above can write data to the RAM in parallel and output the parallel data written to the RAM as serial data using a sam.

As mentioned above, the base clock of a multi-screen display using a 1-megabit dual port memory uses 4fsc (14.3MHZ), which is four times the color subcarrier (3.58MHZ) fsc. The screen clock has 2fsc, the screen clock has 3 / 4fsc, and the screen clock has 16 fsc. As described above, image data written in the image memory according to the screen division mode can be displayed as a multi screen on one monitor only by setting 4fsc as the basic clock regardless of the screen division mode.

However, because of the structure of 1-megabit dual port memory, it is impossible to display the image of one horizontal line by reading the data recorded in one row. Since the image corresponding to the horizontal line can be displayed, the RAM area of the 1-megabit dual port memory is 512 row x 512 coulmn x 4 bits, as shown in FIG. This is because the data of the section) becomes 512 x 4 bits or more, so that the image data of the 1H section is recorded over two rows of RAM in the 1 megabit dual port memory as shown in the solid line of FIG. Therefore, in order to read and display data of one horizontal line of the video signal as the image data recorded in the dual port memory, the data of the beginning of the next row must be read continuously even after reading one row of data.

The control signal required for this purpose is a data transfer (DT) pulse, and the DT pulse is a single row (512 × 4 bit) data stored in a RAM area of the dual port memory. access memory). Since the DT pulse is related to the RAS (Row Address Strobe) and CAS (coulmn Address Strobe) signals required for reading the dual port memory, the pulse width should be different according to each screen mode.

Therefore, an object of the present invention is to read all data written from the column address of a single row of dual port memory, and then data transfer control that can continuously read the data of the first open dress of the next row without interruption of data. In providing a circuit.

Another object of the present invention is to provide a circuit for generating a pulse for controlling write disable and write data delay during a data transfer operation.

Hereinafter, with reference to the accompanying drawings, the operation of a preferred embodiment of the present invention will be described in detail.

)를 출력하는 전송클럭 게이팅회로(118)와, 상기 독출개시신호(RDST)의입력에 의해 분할모드에 다른 로드 데이터를 입력(loading)하고 상기 전송클럭 게이팅회로(118)에서 출력되는 클럭으로 상기 로딩된 데이터로부터 10비트 2진 카운팅하는 전송클럭 카운터(125)와, 멀티제어신호(MULTI)와 화면 분할모드 제어신호(P4,P9,P16)의 입력을 논리조합하여 분할모드에 따른 로드데이터를 상기 바와 같이럭 카운터(125)로 출력하는 카운터제어회로(136)와, 상기 전송클럭 카운터(125)와 상기 카운터 제어회로(136)의 출력을 디코딩하여 각각 소정의 듀레이션을 가지는 데이터전송 요구신호 DTRQ(Data Transfer Request)와 DTRQR을 발생하는 전송제어신호 발생회로(150)로 구성된다.3 is a data transmission control circuit diagram according to the present invention, wherein a dual port memory (not shown) is connected to the serial clock terminal SC having a clock 4fsc terminal and a read start signal RDST terminal. In operation, an input of the read start signal RDST is performed to gate the clock 4fsc and transmit the same to the serial clock SC.

And a different load data in the split mode by the transmission clock gating circuit 118 for outputting the signal and the read start signal RDST and the clock output from the transmission clock gating circuit 118. The load data according to the division mode is logically combined with a transmission clock counter 125 for performing 10-bit binary counting from the loaded data and the input of the multi control signal MULTI and the division mode control signals P4, P9, and P16. As described above, a data transmission request signal DTRQ having a predetermined duration by decoding the counter control circuit 136 outputting to the clock counter 125 and the transmission clock counter 125 and the counter control circuit 136 respectively. (Data Transfer Request) and a transfer control signal generation circuit 150 for generating a DTRQR.

The transmission clock gating circuit 118 of FIG. 3 configures the inverter 112 for inverting the clock 4fsc, the NAND gate for outputting the output of the read start signal RDST and the inverter 112 by negative logic. And an inverter 116 for inverting the output of the NAND gate 114.

As shown in the transmission clock 125, the JK flip-flop 120 divides the output of the NAND gate 114 by two, and the signal output from the JK flip-flop 120 is controlled by the clock of the NAND gate 114. The JK flip-flop 121 outputs by dividing in two, the AND gate 124 for logically multiplying the outputs of the two JK flip-flops 120 and 121, and the load data output from the control circuit 136 as described above. A first counter 126 for loading the data into an internal register by the input of the read start signal RDST and counting the loaded data as an output of the inverter 112, and slave connection to the first counter 126. And a second counter 128 that counts a predetermined number. At this time, among the above configurations, the JK flip-flop 120, the JK flip-flop 121, and the end gate 124 have the transmission clock gating circuit 118 reading the clock 4fsc by the start start signal RDST. Corresponding to the initial counting means for outputting the two-bit binary counting of the transmission clock output from the (). The transmission clock counter 125 configured as described above is composed of a total of 10-bit binary counters.

In addition, the counter control circuit 136 shown in FIG. 3 is the same as one inverter 130 and two oragates 132 and 134, and the transmission control signal generation circuit 150 includes five NANDs. The gate 138, 140, 142, 144, 148 and one end gate 146 are formed. At this time, the data transmission request signal DTRQ output from the NAND gate 148 and the DTRQR output from the second counter 128 are applied as a write address and a timing control signal of a data processing block (not shown). .

4 is an operation waveform diagram of FIG. 3, which is an operation waveform diagram in the four-screen mode.

FIG. 5 is a waveform diagram illustrating the operation of FIG. 3, where 4fsc is a clock, DTRQ is a DT request signal, and RSA and CAS are row / coulmn address strobes output from an address processing block (not shown). , DT is a DT pulse generated by DTRQ in the data processing block. T6 is a page mode write period, T7 is a data transfer period (Data Transfer: Read period), T8 is a write lead / write address reassignment period, and T9 is a page mode write period. And T10 is the lead and write redirection period.

6 is an operational waveform diagram of FIG. 3, which is an operational waveform diagram in the nine-screen mode.

FIG. 7 is an operation waveform diagram of FIG. 3, which shows waveforms of DTRQ4, DTRQ9, and DTRQ16 in 4, 9, and 16 screen modes, and the duration change of DT pulses.

Hereinafter, an operation example of a circuit configured as shown in FIG. 3 according to the present invention will be described in detail with reference to the operation timing diagrams of FIGS. 4 to 7.

Now, when the clock 4fsc as shown in FIG. 4 (a) is input to the inverter 112 and the read start signal RDST as shown in FIG. 4 (b) is input to the NAND gate 114, the NAND gate ( 114, the input clock 4fsc is output to the clock terminal CLK of the JK flip-flop 120 and 121, and is input to the inverter 116. At this time, the inverter 116 briefly inverts the clock 4fsc from FIG. 4c to input the serial clock SC into the dual port memory (not shown). The clock SC output from the inverter 116 is a clock that outputs the data input and written to the dual port memory as data as shown in FIG.

When the multi-control signal MULTI (# 1 'is active) and the multi-screen mode signals P4, P9, and P16 are input to the four-screen mode (# 1100') in the operation state as described above, the oragate 132 and 134 outputs the logic # 0 'and # 1'. Therefore, when the number of data bits of the transmission clock counter 125 including the JK flip-flop 120 (121) and the first and second counters (126, 128) is 10 bits in total, the inverter 130 and the oragate The counter control circuit 136 composed of 132 and 134 can load load data having values of 4, 8, 12, and 16 into the register in the counter 125. And when it is not a multi function (the value of multi control signal MULTI is ＂0＂), it is ＂4 4, when it is 4 screen mode (P4 is high), when it is 8＂ and 9 screen mode (P9 is high). In the case of " 12 " and 16-screen mode (P16 is " high "), a value of " 16 " is loaded into the counter 125 by the follow-up of the read start signal RDST.

Therefore, as described above, when the 4-screen mode control signal of # 1100 is input, the output of the transmission counter 125 counts the output clock of the inverter 112 in the state where # 8 is loaded as shown in FIG. do. As described above (refer to FIG. 4d), when the transmission clock counter 125 counts the clock 4fsc and the counting value becomes 512 seconds in the state in which 8k is loaded (504 in the state of 8k loaded). The output of the output terminal QD of the counter 128 is " high " and the DTRQR becomes " high " as shown in FIG. At this time, the lead data by the clock of the inverter 116 outputs the 504th data as shown in FIG.

The signal of the DTRQR as shown in FIG. 4E is used as a signal for controlling the write control signal, and the DTRQ signal, which is the output of the NAND gate 148, becomes low because the signal of the DTRQ becomes high. The NAND gate 148 maintains the logic flow of the DTRQ until the output of the AND gate 146 goes high.

In this way, in the four-screen mode, only the AND gate 140 is enabled (outputable state) while the DTRQ signal is turned low as shown in FIG. Therefore, when the transmission clock counter 125 further counts # 10 from the value of 512 and the QC of the first counter 126 becomes "high", it outputs a low. When the count value of the transmission clock counter 125 becomes 528 and the output terminal QC of the first counter 126 becomes high, the output of the NAND gate 140 outputs a low, which causes the AND gate. The output of 146 becomes the yellow. Accordingly, the first and second counters 126 and 128 are disabled by the output of the AND gate 146, and the NAND gate 148 outputting the DTRQ signal as shown in FIG. The output goes high and stays on until the next horizontal section.

Meanwhile, the address and data processing block for inputting the DTRQ and DTRQR signals generated from the NAND gate 148 and the QD terminal of the counter 128 in FIG. 3 stops the write mode by the generation of the DTRQ signal and the internal RAM area. A DT pulse for reading data from is generated as shown in FIG. 4 (g).

This will be described in detail with reference to FIG. 5 below. When a DTRQ occurs, it remains high in the horizontal sync signal if the DTRQR goes Risig and remains high until the end of one horizontal line. At this time, the CAS signal is switched to the four times the cycle (that is, 1/4 frequency) of the CAS by the DTRQ, and the RAS maintains a low state, but when the DTRQ occurs, it generates a pulse as shown in FIG. 5 according to the screen mode. do. One section is generated between the rising edge and the rising edge of the RAS of FIG. Therefore, in the 4-screen mode, the DT has a (4fsc x 16) period.

If the nine-screen mode control signal 1010 is input to the counter control circuit, the transfer clock counter 125 loads # 12. When the counting value of the transmission clock counter 125 becomes 512 as shown in FIG. 6 (d) in the 9-screen mode loaded with # 12 as described above, the DTRQ becomes low as shown in FIG. 6 (f). If the counting value reaches 536 again, the DTRQ becomes “high” as shown in the sixth (o). Therefore, the period of the DTRQ is 12 cycles of the serial clock SC. Similarly, in the 16-screen mode, 16 is loaded into the counter 125 to decode the value obtained by counting 32 from 512 to generate DTRQ and DTRQR.

Therefore, the generation cycle of DTRQ in the 4 screen, 9 screen and 16 screen modes is shown in FIG. In fact, since the DT pulse is related to the RAS and CAS time of the memory, the DT pulse width varies according to each screen mode unless it is constant according to each screen mode. That is, the 512th data, which is the last data of one row of memory by the serial clock SC, is read at the rising edge position of the DT pulse, and then the first data of the next row must be ride. In other words, regardless of the screen mode, the read data must be continuously displayed over two rows in order to be displayed on the screen. For this purpose, since the data transfer operation is required during writing, the DTRQ signal is applied to effectively read data during memory writing. Needed. At this time, in order to effectively generate DT which is related to the timing timing pulses in time, a DTRQ signal is generated for each screen mode so that data can be read in real time without affecting the data ride. The DTRQ and DTRQR signals generated here are actually basic signals used in the memory timing control circuit and the address and data processing circuit. That is, it is used for delay of write data which could not be written during data transfer operation, disable of write column address counter, DT pulse generation, RAS, CAS control and so on.

According to the circuit of the present invention, an effective real time transfer (read operation) operation is performed according to each multi-screen mode, and at the same time, a control signal for controlling the read operation is generated during read operation, and recording is also performed. Can be controlled without

Claims (4)

In a memory real time transfer control circuit having a multi-screen function having a dual port memory, an output terminal is connected to a serial clock terminal (SC) of the dual port memory and is input in response to an input of a read start signal (RDST). A transmission clock gating circuit 118 that transmits a clock to the serial clock terminal SC, and screen division mode data is input in response to an input of the read start signal RDST and output from the transmission clock gating circuit 118. A division mode by combining a transmission clock counter 125 for counting a value of a preset data from the loaded data and an input logic combination of a multi control signal MULTI and a screen division mode control signal P4, P9, and P16. A counter control circuit 136 for supplying load data according to the transmission clock counter 125, a counting value output from the transmission clock counter 125, and the counter. Memory real time transfer control in a multi-screen function, characterized in that the transmission control signal generation circuit 150 for decoding the value of the load data output from the control circuit 136 to generate a DTRQ and a DTRQR, respectively, having a predetermined duration. Circuit. The transmission clock counter 125 is connected to the transmission clock gating circuit 118, the initial counting means for outputting the two-bit binary counting the output transmission clock, and the counter control circuit 136 A first counter 126 which loads the load data outputted from the data into an internal register by the input of the read start signal RDST and counters the loaded data by the transmission clock in response to the output of the initial counting means. And a second counter 128 that is cascaded to the output of the first counter 126 and that counts the output of the first counter 126 at a predetermined time. Control circuit. The method of claim 2, wherein the initial counting means outputs a first flip-flop 120 for dividing the transmission clock by two, and a two-minute transmission clock output for two minutes from the first flip-flop (120). The second flip-flop 121 and the output terminals of the first flip-flop 120 and the second flip-flop 121, and each bit divided by two bits in response to the output having the first level. A memory real time control circuit for a multi-screen function, comprising: an end gate 124 for outputting a binary counting signal. The inverter clock gating circuit 118 of claim 3, further comprising an inverter 112 connected to a clock terminal and inverting the transmission clock 4fsc inputted to the first and second counters 126 and 128, respectively. And a NAND gate 114 which negatively multiplies the read start signal RDST and an output of the inverter 112 to supply the clock terminals of the first and second flip-flops 120 and 121, and the NAND gate. And a inverter 116 for inverting the output of the 114 and outputting the serial clock SC.

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