JPS60236536A - Digital word synchronizing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Background of the invention The present invention relates to a digital word synchronization method.

More particularly, the present invention relates to an apparatus or method for achieving synchronization with digital synchronization words provided at selected intervals in a digital message.

A series of digital signals is often used to transmit data because such a series of digital signals can be transmitted quickly and efficiently. However, such high speed transmission requires that the data receiver provide fast and efficient synchronization of the words forming the information of the transmitted data message. Without such synchronization, it would not be possible to know the beginning and end of each information word, resulting in meaningless data. This often occurs when the transmission medium is noisy or subject to fading, for example when the transmission medium is a wireless channel, in which case synchronization becomes a major problem. . For these reasons and others, predetermined synchronization words are provided sequentially at spaced locations or times within a data message to provide an opportunity for the data receiver to identify and synchronize the synchronization words and to It allows us to detect exactly where an information section or word begins and ends.

SUMMARY OF THE INVENTION Briefly, in accordance with the present invention, a received digital signal in a message is compared to a predetermined stored digital synchronization word. Once the first correct comparison result indicating that the sync word was correctly received is obtained, the next four received sync words are compared to the stored predetermined sync word. If the results of any two of these four sequential comparisons indicate that the synchronization word was correctly received, then the synchronization in progress indicates that word synchronization has been achieved. -sync
A signal is generated, which also indicates that the information word can be read and utilized correctly. However, if fewer than two of these four sequential comparisons indicate a correctly received sync word, subsequent digital Resume signal comparison. Then, the next four synchronization words are compared, and if any two are correct, a synchronization signal is generated. If there are fewer than 2 correct ones, the comparison starts again. This process is repeated as many times as required or until no synchronization words are detected.

The subject matter of the invention is particularly pointed out and distinctly claimed in the claims. The structure, operation, and advantages of the present invention will be better understood from the following description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION Those skilled in the art will appreciate from this description that the present invention can be used with a variety of formats of data messages having a variety of synchronization words. - By way of example, the series of data formats of FIG. 1 will be used for the detailed description of the invention. This data format is commonly used to transmit data messages in cellular radiotelephone systems. Although the present invention is described using data in binary format, it will be appreciated by those with expertise in the art that other formats of data may be used, such as ternary signals. Good morning. 1-
The tough format has a total of 1032 bits], and a 1-bit number indicates the beginning of each part of the format.
It's been done. The format of FIG. Starting from
An 11-bit first sync word is transmitted.

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, this synchronization word is 1 1 100010010. Although other synchronization words may be used with ε, the format shown is desirable in that there are relatively few repeats in the message word. Following the first synchronization word, a first message of 40 bits starting at bit 113 is transmitted. These bits have a binary format that conveys the desired message.

Next, 37 dot pits starting from bit 153 are transmitted. These bits are followed by a second sync word that is the same as the first sync word. The second synchronization word is followed by a second message word, which is typically the same as the first message word. In this way, the sequence consisting of the driver 1 to bit, synchronization word, and message word is repeated to create a total of 11 sequences. The synchronization words are typically evenly spaced by a message word of ~40 bits plus 37 synchronization bits, or 77 bits. However, such equal intervals are not constant.

One reason for choosing this format is that typically wireless receivers can achieve bit and word synchronization in a relatively short amount of time and with reasonable accuracy. This accuracy is improved by using the word synchronization scheme according to the invention.

FIG. 2 is a block diagram illustrating a synchronous MIN according to the present invention. The glue of the present invention! A typical preferred embodiment is Microno [! Although this may be accomplished by a Lelli and associated metering circuit, the block diagram of FIG. 2 is shown to facilitate understanding of the apparatus of the present invention.

As shown, the synchronizer includes a receiver 10 that receives and processes input signals from wired or wireless AIR sources and demodulates these signals as required.

If these input signals contain audio or other information, this information is fed into appropriate circuitry. The data signal is fed to a signal conditioner 11, which signal conditioner comprises:
If the data is in the form of modulated signals, these signals are converted to digital signals with appropriate or desired voltage levels. These digital signals are applied to a bit synchronization circuit 12 which generates a clock signal of an appropriate frequency synchronized to the input bit signal, as is known in the art. The clock signal is supplied to various parts of the synchronizer as required (it picture 6 movie 1 - signal is supplied to a synchronization word comparator or comparator circuit 13 which converts the input bit signal to a storage circuit 14). This comparison may be in serial or parallel form. ■ A different sequence of sync word bits. (For example, 1 mentioned above
1100010010) is detected by this comparison, the comparator 13 generates an output signal, which output signal is passed to the sync word argument device I F5 which arguments the correct sync word.
supplied to Reset! Comparator 13 then operates bit by bit, examining each new bit to determine whether this new bit and the previous (10) bits form a correct synchronization word. . After first detecting the correct synchronization word, comparator 13 operates in position comparison mode and the 11 that occurs at the time or position of the next synchronization word
(or the appropriate number) of bits.

Counter 15 counts one correct word as shown, or two (L) numbers of bad words, or three
Cl a (ifl) of the above preferred words each has an appropriate output. Count value of 1, or
An actuation signal is supplied to the synchronization word position indicator 16 when the value 1 or 61 of 3 is reached.

If the count value of counter 15 is less than 1, indicator 16 is not activated.

The sync word position indicator 16 is configured to count clock bits from the circuit 12 so that the clock bits from the circuit 12 are Δ5.
When activated upon detection of the first sync word, it takes a number of bits as an argument to indicate the time or position at which the next sync word will occur. After being actuated by the first detection of a synchronization word, the indicator 16 is activated to indicate the time or position at which the next subsequent synchronization word 1.2.3 or 4 appears, respectively. 4. Referring again to FIG. 1, when the first synchronization word (bits 102-112) is detected, the indicator 16 will beep from 1 to 1. The second
of the synchronization word (17). This n1 value is the first number 1!
When bit 190 of the second sync word appears, indicator 16 produces an output signal at output 1, indicating that the first sync word after detection of the first sync word is to indicate that it is in the correct position. 2nd, 3rd J3 J: and 4th after first detection of sync word
Output signals are generated at outputs 2, 3 and 4, respectively, to indicate the time or position of the synchronization word M. Of course,
The first detection may occur anywhere in the message shown in FIG. The signals at each of outputs 1.2.3 and 4 are fed to a sync one-node comparator 13, causing the comparator 13 to operate in position comparison mode μ, to check for the presence of a sync word at the correct time or location. .

When the sync word position indicator 16 produces a signal at output 4, this indicates that four sync word positions after the first detected sync word have occurred. The signal of this output 4 is fed to the activation input of the output gate 18 during synchronization.

When this output 4 is supplied from the indicator 16, the output gate 18 is released or activated during synchronization. The synchronization word R1 counter 1 ri has reached hI number (1t1) of 31 strokes, and the signal of output 33 at is goo i・I F3
and this sort the same! ! 11 detects the first synchronization word and another two 11] between the next four synchronization words FW! Detection of the V1 word. This synchronized transmission signal that has passed through channels 1 to 18 is used by the decoding circuit 21 as 1 and received>;"+ a or other circuits to achieve synchronization. ] 7 Tagatsu (Metsu 1 in Figure 1 = ~ Shiwa - Scream・' is sure =) + I will return) °J
will be used, and will be used (-dogade・' includero1゜1ii
] jllll ”7- Toy Cl f8 li? Small item 1 (: 1.L 11 /Jfil tvl '7
I' 4 (equipped with an output indicating the end of device 4).

This 111 power resets the synchronization word comparator 13 for /El of the 1-bit comparison) 31, 1. T-supplied desk, maikoti-111111 word 81 number counter 15A
3 J, and the synchronization word position v1 indicator 16 is pressed [1 to 1-7J 0, this relay! Temporarily, regardless of whether the synchronization signal output is R/I, device GJ opens the search operation again for the first synchronization word.

FIG. 3 shows a flowchart illustrating the operation of the apparatus of FIG. 2, and which may be accomplished by a microprocessor and appropriate memory circuitry to accomplish the same functions as are accomplished by the apparatus of FIG. This is an example. In Figure 3, the start function is the start circuit 3.
Starting at 0, various circuits are cleared or reset as indicated by block 31. This sequentially loads a series of digital pits into the sync word comparator as shown at block 32.

Bits continue to be loaded into the sync word comparator as long as the first sync word is not detected as indicated by decision block 33. However, once the first sync word is detected, the circuit has another sync and message word as shown at block 34. Each time a subsequent synchronization word occurs, decision block 35 determines whether the correct synchronization word is present, ie, detected. If the decision is no, another synchronization word counter (indicator) is incremented in block 37.

If the decision is Yes, the sync word counter that counts i1 the correct sync words in block 36 is incremented, and the counter in block 37 is also incremented. The G1 counter of block 37 is incremented each time this J, uni, ilE 1) is equal to -1 or an incorrect synchronization word appears.

The count output of block 37 is provided to a decision button 38 which determines when five sync words (including the first sync word) have been received. Received sync word (iT
If there are fewer than five E (including empty and incorrect sync words), decision block 38 instructs block 34 to organize the sync and message words. When five sync words are received (including the correct sync word and the incorrect sync word), block 39 opens the output gate 18. Decision block 40 determines whether three of these five synchronization words are erroneous synchronization words. If no, the device restarts to find the first sync word in a hit-by-hit comparison. i), if
A synchronizing signal is sent by block 41 to output gate 18 of FIG. If the decision block 42 determines that gate 1B is open, a synchronizing signal is provided to block 43 to decode the message word. After this Wi issue, the circuit restarts to search for another message.

”-1 From the above explanation, after detecting the first correct synchronization word, word synchronization is performed in response to detecting another two correct synchronization words between the next four synchronization word positions r. It will be appreciated that a working improved word synchronization circuit has been provided.

Although the case where the synchronization words are equally spaced in time has been described, this may not be necessary depending on the application. 1st
In a synchronizer operating using the data message shown in the figure,
When the pit error rate is 0.05, a strong synchronization output signal is generated for 69.2% of the time, and 39. ．． It has been found that only once every 8 hours does a false or erroneous web status display occur. 1 While the apparatus shown and described is a preferred embodiment, it will be appreciated that many modifications may be made by those skilled in the art. Therefore, while the invention has been described with reference to particular embodiments, it is to be understood that numerous changes, particularly to circuitry, may be made without departing from the spirit or scope of the invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a digital message that can be used in a synchronization device according to the present invention. FIG. 2 is a block diagram of a synchronous YR according to the present invention. FIG. 3 is a flowchart II.--T showing the operation of Ha in FIG. Patent applicant General Electric Kanbai representative (76
30) Raw Swamp Virtue °.

Claims (1)

Claims: 1. An apparatus for achieving synchronization with a data message that includes a synchronization word transmitted at multiple points in the data message, comprising: a) input means for receiving the transmitted synchronization word; b) storage means storing predetermined synchronization words; C) connected to said input means and said storage means for comparing each received synchronization word with said stored synchronization word; d) comparing means for generating a first signal if each received synchronization word matches said stored synchronization word; d) being connected to said comparing means and after generating one said first signal; output means for generating a synchronizing signal when at least two of the first signals occur during the next four comparisons between the received synchronization word and the stored synchronization word; Synchronizer with. 2. The synchronization device according to claim 1, wherein the transmitted synchronization words are provided at equal intervals in the message, and the comparison means performs the four comparisons at equal intervals. . 3. In the synchronization device according to claim 2, the transmitted synchronization words are arranged at predetermined intervals, and the comparison means is arranged at predetermined intervals.
A synchronizer that performs the four comparisons at predetermined intervals. 4. having at least one transmitter at the first location;
A synchronizing device for use in a communication system having a receiver for receiving digital messages from said transmitter at a location comprising: a) a plurality of synchronizers connected to said receiver and occurring at predetermined spaced locations; b) retrieval means for retrieving a digital message having a synchronization word of; b) synchronization signal generating means connected to said retrieval means for generating a synchronization signal in response to each retrieved synchronization word having a predetermined sequence of digital values; d) a counting means connected to the c>m entry means for counting the position of the synchronization word and connected to the synchronization signal generation means for counting the synchronization signal; d) connected to the counting means; means for generating a synchronizing output signal in response to at least two synchronizing signals between the next four counted synchronizing word positions following the occurrence of the first synchronizing signal in the digital message. 5. A synchronization device according to claim 4, wherein the digital message has a plurality of identical synchronization words occurring at predetermined equally spaced positions. 6. A method for detecting a digital synchronization word comprising a series of digital signals having predetermined characteristics and appearing at predetermined times spaced apart in a digital message, the method comprising: a) said series of digital signals; b) generating a first detected word signal if a first said series of digital signals in a message is the same as said stored digital word; Comparing the series of digital signals and the stored digital words at the predetermined times following the occurrence of the first detected word signal, the series of digital signals at these subsequent predetermined times is compared to the stored digital words. the second digital word if it is the same as the digital word being
c) counting said second sensed word signals following said first sensed word signal; and d) at least two sensed word signals are generated during said four subsequent predetermined times. A method having steps in which a synchronizing signal is generated in response to a synchronizing signal. 7. The method of claim 6, wherein if at least two detected word signals are not generated during the four subsequent predetermined time periods, the series of detection word signals is not generated until the first detected word signal is generated. and said stored digital word. 8. In the method according to claim 6, if two second detected word signals are not generated during the four subsequent predetermined times, further calculating the count value of the detected word signals. Resetting to zero and comparing the series of digital signals with the stored digital word until the first detected word signal is generated. 9. An apparatus for achieving synchronization of any data message having serial bits forming a synchronization word transmitted at multiple times in a data message, comprising: a) input means for receiving said transmitted synchronization word; b) ) a storage means for storing a predetermined synchronization word; generating a first signal in response to a first comparison result that matches a stored sync word; and generating a correct word signal for each subsequent comparison when each serial bit matches said stored sync word. d) a comparison means connected to said comparison means for generating at least two said overwhelming word signals in the next four successive comparisons of said stored synchronization word with the next successive series of bits; output means for generating a synchronizing signal in response to the occurrence of a synchronizing signal. 10. In the synchronization device according to claim 9,
A synchronizer in which the first comparison is performed each time a new bit is received. 11. In the synchronizing device according to claim 9, 1
．． A synchronizer in which each of said subsequent comparisons is made in response to an indication of a synchronization word position. 12. The synchronizer of claim 10, wherein each of said subsequent comparisons is performed in response to an indication of a synchronization word position. 13. In the synchronization device according to claim 9,
A synchronization device comprising means for restarting said first comparison following said next four comparisons of said group of bits. 14. A synchronizer as claimed in claim 10, including means for restarting said first comparison following said next four comparisons of said bit group. 15. A synchronizer according to claim 11, including means for restarting said first comparison following said next four comparisons of said bit group. 16. A synchronizer as claimed in claim 12, including means for restarting said first comparison following said next four comparisons of said bit groups. 17. A method for detecting a digital synchronization word comprising a series of digital signals having predetermined characteristics and appearing at a plurality of predetermined spaced times in a digital message, comprising the steps of: a) first detecting said series of digital signals; Each time a new digital signal occurs, the series of digital signals is compared with the stored digital word, and the first series of digital signals in the message is the same as the stored digital word. b) sequentially comparing said series of digital signals with said stored digital words based on time position at said predetermined time following generation of said first signal; C) generating a second signal if each successive digital signal at a subsequent predetermined time is the same as the stored digital word; C) counting the second signal following the first signal; d) generating a synchronizing signal in response to the occurrence of at least two of the second signals during the four subsequent predetermined time periods; A method with each step to start the first comparison.