JPS57162553A - Protecting system for frame synchronization - Google Patents

Protecting system for frame synchronization

Info

Publication number
JPS57162553A
JPS57162553A JP56046232A JP4623281A JPS57162553A JP S57162553 A JPS57162553 A JP S57162553A JP 56046232 A JP56046232 A JP 56046232A JP 4623281 A JP4623281 A JP 4623281A JP S57162553 A JPS57162553 A JP S57162553A
Authority
JP
Japan
Prior art keywords
signal
circuit
bit
frame
collation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56046232A
Other languages
Japanese (ja)
Inventor
Keiji Tomooka
Makoto Ogawa
Shinji Sekihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56046232A priority Critical patent/JPS57162553A/en
Publication of JPS57162553A publication Critical patent/JPS57162553A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To equivalently increase the number of bits and to ensure the stable synchronization of frames, by carrying out the collation of patterns including the blank part which is right before the frame synchronizing bit in the pull-in mode. CONSTITUTION:In the pull-in mode, a frame synchronizing bit detecting circuit 10 detects the n-bit out of the synchronizing bit FB within the first frame F1 of an input signal (a) and feeds it to a gate circuit 20 (signal b). A frame syncronizing bit reproduced output circuit 30 receives the signal C from the circuit 20 and feeds the signal (d) to a signal processing part. Then a pattern collation signal (e) of the (m+n)-bit including the blank part of m-bit which is right before the synchronizing bit of a frame F2 is fed to a synchronization protecting circuit 40. The signal (a) fetched through a sampling circuit 42 is collated according to the signal and through a pattern collating circuit 44. The result of this collation is fed to a majority circuit 46 through an OR gate 45. If the majority is obtained for the frames F2-Fi, the syncronizm set-up signal (f) is transmitted.
JP56046232A 1981-03-31 1981-03-31 Protecting system for frame synchronization Pending JPS57162553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56046232A JPS57162553A (en) 1981-03-31 1981-03-31 Protecting system for frame synchronization

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56046232A JPS57162553A (en) 1981-03-31 1981-03-31 Protecting system for frame synchronization

Publications (1)

Publication Number Publication Date
JPS57162553A true JPS57162553A (en) 1982-10-06

Family

ID=12741363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56046232A Pending JPS57162553A (en) 1981-03-31 1981-03-31 Protecting system for frame synchronization

Country Status (1)

Country Link
JP (1) JPS57162553A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60236536A (en) * 1984-03-15 1985-11-25 エリクソン　ジーイー　モービル　コミュニケーションズ　インコーポレーテッド Digital word synchronizing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60236536A (en) * 1984-03-15 1985-11-25 エリクソン　ジーイー　モービル　コミュニケーションズ　インコーポレーテッド Digital word synchronizing system

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