JPS5762647A - Synchronizing circuit - Google Patents

Synchronizing circuit

Info

Publication number
JPS5762647A
JPS5762647A JP55137114A JP13711480A JPS5762647A JP S5762647 A JPS5762647 A JP S5762647A JP 55137114 A JP55137114 A JP 55137114A JP 13711480 A JP13711480 A JP 13711480A JP S5762647 A JPS5762647 A JP S5762647A
Authority
JP
Japan
Prior art keywords
reference pulse
signal
inputted
circuits
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55137114A
Other languages
Japanese (ja)
Inventor
Takashi Wakabayashi
Takeo Fukushima
Tetsuo Murase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55137114A priority Critical patent/JPS5762647A/en
Publication of JPS5762647A publication Critical patent/JPS5762647A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0605—Special codes used as synchronising signal
    • H04J3/0608—Detectors therefor, e.g. correlators, state machines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To restore rapidly synchronization for input data. CONSTITUTION:A frame pattern detected by a frame pattern detecting circuit 1 is inputted to collating circuits 2-1-2-n in parallel. A clock control circuit 3 inputs a clock signal to a reference pulse generating circuit 4, and the reference pulse generating circuit 4 generates reference pulse (1)-(n) on a basis of this clock signal. Reference pulse (1)-(n) are inptted to collating circuits 2-1-2-n respectively and are collated with frame pulses inputted from the frame pattern generating circuit 1. Each of collating circuits 2-1-2-n generates a coincidence signal and inputs this signal to a corresponding protection circuit if the inputted frame pulse and the reference pulse coincide with each other. If this coincidence signal is inputted three times continuously, each of protection circuits 5-1-5-n outputs a signal indicating coincidence of synchronization; and otherwise, it outputs a signal indicating step out.
JP55137114A 1980-10-01 1980-10-01 Synchronizing circuit Pending JPS5762647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55137114A JPS5762647A (en) 1980-10-01 1980-10-01 Synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55137114A JPS5762647A (en) 1980-10-01 1980-10-01 Synchronizing circuit

Publications (1)

Publication Number Publication Date
JPS5762647A true JPS5762647A (en) 1982-04-15

Family

ID=15191154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55137114A Pending JPS5762647A (en) 1980-10-01 1980-10-01 Synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS5762647A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0227827A (en) * 1988-07-18 1990-01-30 Matsushita Electric Ind Co Ltd Frame synchronizing circuit
EP0487943A2 (en) * 1990-11-29 1992-06-03 Siemens Aktiengesellschaft Frame error detection system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0227827A (en) * 1988-07-18 1990-01-30 Matsushita Electric Ind Co Ltd Frame synchronizing circuit
EP0487943A2 (en) * 1990-11-29 1992-06-03 Siemens Aktiengesellschaft Frame error detection system

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