JPS57152255A - Frame synchronizing device - Google Patents

Abstract

PURPOSE:To shorten a synchronous reset time by eliminating the need for a synchronizing circuit for a high-order group by inhibiting the output of a frequency dividing means in response to the output of each discriminating circuit of a synchronizing circuit, and then performing synchronization by using a low-order group synchronizing circuit. CONSTITUTION:A high-order group signal obtained by multiplexing a prescribed number of multiplexed low-order signals on time-division basis is applied to a signal input terminal 16, and a clock synchronizing with the signal is applied to an input terminal 17. The frequency of the clock from the terminal 17 is divided by a counter circuit 13 after passing through a gate circuit 11 to separate the high-order group signal, inputted to a series-parallel converting circuit 12, into the low-order group signals. The output of this circuit 12 and that of the counter circuit 13 are supplied to low-order group synchronizing circuits 20 and 30 respectively. Those circuits 20 and 30 are provided with a gate circuit 8, counter circuits 14 and 15, synchronizing pulse detecting circuits 60 and 61, and synchronous protecting circuits 70 and 71. In response to the outputs of the circuits 20 and 30, a gate circuit 10 is controlled to inhibit the output of the counter circuit 13, and then synchronization is performed by only the low-order group synchronizing circuit to shorten a synchronous reset time.