JPS56157154A - Clock synchronizing circuit - Google Patents

Clock synchronizing circuit

Info

Publication number
JPS56157154A
JPS56157154A JP6091180A JP6091180A JPS56157154A JP S56157154 A JPS56157154 A JP S56157154A JP 6091180 A JP6091180 A JP 6091180A JP 6091180 A JP6091180 A JP 6091180A JP S56157154 A JPS56157154 A JP S56157154A
Authority
JP
Japan
Prior art keywords
clock
circuit
synchronous signal
counter
synchronizing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6091180A
Other languages
Japanese (ja)
Inventor
Hiroshi Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6091180A priority Critical patent/JPS56157154A/en
Priority to US06/245,281 priority patent/US4404672A/en
Priority to AU68841/81A priority patent/AU537975B2/en
Priority to CA000374013A priority patent/CA1163734A/en
Priority to DE8181102349T priority patent/DE3171775D1/en
Priority to EP81102349A priority patent/EP0037107B1/en
Publication of JPS56157154A publication Critical patent/JPS56157154A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To realize a small-scale circuit constitution, by setting a counter circuit at a prescribed value by the frame synchronous signal extracted through a synchronous signal extracting circuit and then performing a counting with the 2nd clock after setting the counter circuit. CONSTITUTION:A synchronous signal extracting circuit 11 works by the clock 9 supplied from the main device and extracts a frame synchronous signal 14 out of a received signal 10. A clock generator 13 generates a clock 15 of a higher frequency than the clock 9. A counter 12 works by the clock 15 to store a prescribed value with the signal 14 and delivers a clock 16 of the same frequency as the clock 9.
JP6091180A 1980-03-28 1980-05-08 Clock synchronizing circuit Pending JPS56157154A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP6091180A JPS56157154A (en) 1980-05-08 1980-05-08 Clock synchronizing circuit
US06/245,281 US4404672A (en) 1980-03-28 1981-03-19 Subscriber terminal for use in a time shared bidirectional digital communication network
AU68841/81A AU537975B2 (en) 1980-03-28 1981-03-27 Subscriber terminal for digital network
CA000374013A CA1163734A (en) 1980-03-28 1981-03-27 Subscriber terminal for use in a time shared bidirectional digital communication network
DE8181102349T DE3171775D1 (en) 1980-03-28 1981-03-27 Subscriber terminal for use in a time shared bidirectional digital communication network
EP81102349A EP0037107B1 (en) 1980-03-28 1981-03-27 Subscriber terminal for use in a time shared bidirectional digital communication network

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6091180A JPS56157154A (en) 1980-05-08 1980-05-08 Clock synchronizing circuit

Publications (1)

Publication Number Publication Date
JPS56157154A true JPS56157154A (en) 1981-12-04

Family

ID=13156024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6091180A Pending JPS56157154A (en) 1980-03-28 1980-05-08 Clock synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS56157154A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6069933A (en) * 1983-08-03 1985-04-20 ゼネラル・エレクトリック・カンパニイ Multiple bus system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5434602A (en) * 1977-08-22 1979-03-14 Nec Corp Holding system for bit synchronization

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5434602A (en) * 1977-08-22 1979-03-14 Nec Corp Holding system for bit synchronization

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6069933A (en) * 1983-08-03 1985-04-20 ゼネラル・エレクトリック・カンパニイ Multiple bus system

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