JPS5696526A - Timing signal generating system - Google Patents

Timing signal generating system

Info

Publication number
JPS5696526A
JPS5696526A JP17319179A JP17319179A JPS5696526A JP S5696526 A JPS5696526 A JP S5696526A JP 17319179 A JP17319179 A JP 17319179A JP 17319179 A JP17319179 A JP 17319179A JP S5696526 A JPS5696526 A JP S5696526A
Authority
JP
Japan
Prior art keywords
signal
output
circuit
delay
delay time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17319179A
Other languages
Japanese (ja)
Inventor
Akio Munakata
Taiho Higuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17319179A priority Critical patent/JPS5696526A/en
Publication of JPS5696526A publication Critical patent/JPS5696526A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To enable to obtain accurate new timing pulses simply, by the constitution that delay elements for adjustment are selected with a switching means so that they are sequentially in series connection. CONSTITUTION:When a signal CLOCK is applied to an AND circuit 3, signals DLLOP1, 2 are input sequentially via an AND circuit 4. When this signal DLLOP2 is input, the signal CYEND is output from the circuit 4. Thus, a multiplexer MPX12 operates to output a signal from the output terminal of a delay element D2. Further, if the delay time obtained with delay elements D1, D2 is slightly smaller than the required delay time, this is detected at a synchronizing detection circuit 15 and a counter 13 counts 1. Thus, MPX12 controls to output the output signal from a delay element d1. If the delay time obtained by this is further smaller than the required delay time, it is detected at the circuit 15, the counter 13 counts 2, and MPX12 selects the output signal from a delay element d2.
JP17319179A 1979-12-28 1979-12-28 Timing signal generating system Pending JPS5696526A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17319179A JPS5696526A (en) 1979-12-28 1979-12-28 Timing signal generating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17319179A JPS5696526A (en) 1979-12-28 1979-12-28 Timing signal generating system

Publications (1)

Publication Number Publication Date
JPS5696526A true JPS5696526A (en) 1981-08-04

Family

ID=15955774

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17319179A Pending JPS5696526A (en) 1979-12-28 1979-12-28 Timing signal generating system

Country Status (1)

Country Link
JP (1) JPS5696526A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6270922A (en) * 1985-09-04 1987-04-01 Fujitsu Ltd Clock phase control system
JPH01175408A (en) * 1987-12-29 1989-07-11 Matsushita Electric Ind Co Ltd Signal delay device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6270922A (en) * 1985-09-04 1987-04-01 Fujitsu Ltd Clock phase control system
JPH01175408A (en) * 1987-12-29 1989-07-11 Matsushita Electric Ind Co Ltd Signal delay device

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