JPS6449416A - Detection circuit for plural pulse train - Google Patents

Abstract

PURPOSE:To reduce the number of pulse detectors and to simplify the constitution of a circuit, by inputting the output of an OR gate passing through a two- frequency division circuit, and detecting the output signal of a flip-flop which receives the output of an AND gate as clock input. CONSTITUTION:Pulse trains (a) and (b) are inputted to the OR gate 11 and the AND gate 12. The output pulse train (c) of the OR gate 11 is inputted to the clock CL of the two-frwquency division circuit 13, and two frequency- divided, and the output Q goes to a pulse train (f), and is inputted to data D in th flip-flop 14. The output, the inverse of Q goes to a pulse train (e), and is fed back to the data in the two-frequency division circuit 13. The output pulse train (d) of the AND gate 12 is inputted to the clock CL of the flip-flop 14. The output pulse train (g) of the flip-flop 14 is inputted to the pulse detector 15. When two pulse trains (a) and (b) are normal, the pulse train (g) is generated, and is detected by the pulse detector 15. When even one of the pulse trains (a) and (b) is cut-off and held at '0', the pulse train (d) goes to '0', and the pulse train (g) goes to pulse cut-off, and when it is held at '1', the pulse train (c) goes to '1', and the pulse trains (f) and (g) go to pulse cut-off.