JPS55118232A - Pulse count circuit - Google Patents
Pulse count circuitInfo
- Publication number
- JPS55118232A JPS55118232A JP2506679A JP2506679A JPS55118232A JP S55118232 A JPS55118232 A JP S55118232A JP 2506679 A JP2506679 A JP 2506679A JP 2506679 A JP2506679 A JP 2506679A JP S55118232 A JPS55118232 A JP S55118232A
- Authority
- JP
- Japan
- Prior art keywords
- inversion
- pulse
- circuit
- phase
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
Landscapes
- Measuring Phase Differences (AREA)
Abstract
PURPOSE:To enable circuit integration, by gating the path to the counter of the output signal phase-discriminated with the circuit output detecting the zero of the counter, in the count circuit counting the two-phase pulse train with the phase difference. CONSTITUTION:If the pulse PA is in phase advance of pi/2 than the pulse PB, the pulse PA1 is outputted from the phase discriminating circuit 11 and pulse PB2 is outputted if in delay phase. The distribution gate circuit 12 outputs pulses with the operation of PA2= inversion (PA1.S<+>). inversion (PB1.S<->) and PB2= inversion (PB1.S<+>). inversion (PA1.S<->), (where; S<+>, S<-> are code signals), and the up count is made with pulse PA2 and down count is made with pulse PB2 for the counter 14. The zero of the counter 14 is detected with the zero detection circuit 15, the output Z is fed to the polarity discrimination circuit 13, the operation of S<+>= inversion PA1+ inversion Z, S<->= inversion PB1+ inversion Z is made, and the signals S<+>, S<-> are fed to the distribution gate circuit 12. Accordingly, the output signal in response to the phase of the pulses PA and PB from the counter 14.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2506679A JPS55118232A (en) | 1979-03-06 | 1979-03-06 | Pulse count circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2506679A JPS55118232A (en) | 1979-03-06 | 1979-03-06 | Pulse count circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS55118232A true JPS55118232A (en) | 1980-09-11 |
Family
ID=12155542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2506679A Pending JPS55118232A (en) | 1979-03-06 | 1979-03-06 | Pulse count circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55118232A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59161915A (en) * | 1983-02-24 | 1984-09-12 | テキサス・インスツルメンツ・インコ−ポレイテツド | Synchronization decoding circuit |
| JPH0744444B1 (en) * | 1984-10-08 | 1995-05-15 |
-
1979
- 1979-03-06 JP JP2506679A patent/JPS55118232A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59161915A (en) * | 1983-02-24 | 1984-09-12 | テキサス・インスツルメンツ・インコ−ポレイテツド | Synchronization decoding circuit |
| JPH0744444B1 (en) * | 1984-10-08 | 1995-05-15 |
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