JPS57168542A - Synchronizing method of digital communication system - Google Patents
Synchronizing method of digital communication systemInfo
- Publication number
- JPS57168542A JPS57168542A JP57038603A JP3860382A JPS57168542A JP S57168542 A JPS57168542 A JP S57168542A JP 57038603 A JP57038603 A JP 57038603A JP 3860382 A JP3860382 A JP 3860382A JP S57168542 A JPS57168542 A JP S57168542A
- Authority
- JP
- Japan
- Prior art keywords
- counter
- pattern
- frame
- ultraframe
- detector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0605—Special codes used as synchronising signal
Abstract
PURPOSE:To assuredly perform the multiplication, separation, scramble and discramble of information with a small error factor, by distributing the frame synchronizing codes for every integer-fold value of ultraframe synchronization and performing the ultra-frame synchronization with use of the ultraframe synchronizing code. CONSTITUTION:An input signal is supplied to a detector 2 of pattern A as well as to a detector 3 of pattern B in parallel. A frame synchronizing circuit 4 functions so that the pattern A is detected at the time expected by a frame counter 5. Then the frame synchronization is estabilished at the counter 5 when the pattern A is stabilized. On the other hand, an ultraframe counter 6 has the free running with period Tp by the frame pulse supplied from the counter 5. The detector 3 detects an ultraframe synchronizing pattern at a time point expected by the counter 5. At this moment, the detector 3 applies the reset pulse to the counter 6 to ensure the working with a correct phase.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57038603A JPS5912059B2 (en) | 1982-03-11 | 1982-03-11 | How to synchronize digital communication methods |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57038603A JPS5912059B2 (en) | 1982-03-11 | 1982-03-11 | How to synchronize digital communication methods |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13393777A Division JPS5467310A (en) | 1977-11-08 | 1977-11-08 | Synchronizing method and circuit for digital communication system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57168542A true JPS57168542A (en) | 1982-10-16 |
JPS5912059B2 JPS5912059B2 (en) | 1984-03-21 |
Family
ID=12529846
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57038603A Expired JPS5912059B2 (en) | 1982-03-11 | 1982-03-11 | How to synchronize digital communication methods |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5912059B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61274538A (en) * | 1985-05-30 | 1986-12-04 | Nec Corp | Method for transmitting control signal in digital transmission system |
-
1982
- 1982-03-11 JP JP57038603A patent/JPS5912059B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61274538A (en) * | 1985-05-30 | 1986-12-04 | Nec Corp | Method for transmitting control signal in digital transmission system |
JPH0588580B2 (en) * | 1985-05-30 | 1993-12-22 | Nippon Denki Kk |
Also Published As
Publication number | Publication date |
---|---|
JPS5912059B2 (en) | 1984-03-21 |
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