GB2156189A

GB2156189A - Digital word synchronizing arrangements

Info

Publication number: GB2156189A
Application number: GB08505771A
Authority: GB
Inventors: Melvin Webb Sutphin; Theodore Edward Taylor
Original assignee: General Electric Co
Current assignee: General Electric Co
Priority date: 1984-03-15
Filing date: 1985-03-06
Publication date: 1985-10-02
Also published as: JPS60236536A; HK21890A; GB8505771D0; KR850006804A; GB2156189B; SG73989G

Abstract

Word synchronization of a digital message comprised of spaced predetermined synchronizing words is indicated by a first initial detection of a synchronizing word followed by detection of two synchronizing words out of the next four synchronizing words. <IMAGE>

Description

SPECIFICATION Digital word synchronizing arrangements Our invention reiatesto a digital word synchroniz ing arrangement. in particu lar, ou r invention relates to an arrangement or a method for achieving synchro nization with digital synchronizing words provided at selected intervals in a digital message.

Sequences of digital signals are frequently used to transmit data, because such sequences can be transmitted rapidly and efficiently. However, such rapid transmission requires equally rapid and efficient synchronization ofthe data receiver with the words forming the information ofthe transmitted data message. Withoutsuch synchronization, the beginning and end of each information word is unknown, resulting in meaningless data. The synchronization problem is increased ifthetransmission medium is n4sy or subject to fading, as itfrequently is if the medium is a radio channel.Forthese and other reasons, predetermined synchronizing words are provided sequentially at spaced locationsortimes in a data message to provide a data receiver with the opportunity to recognize the synchronizing words and synchronize itself so as to accurately detect where the information parts orwords ofthe data message begin and end.

Briefly and in accordance with our invention, we compare the received digital signals in a message with a stored predetermined digital synchronizing word.

Upon the initial correct comparison indicating a correctly received synchronizing word, we compare the nextfoursubsequently received synchronizing words with the stored predetermined synchronizing word. If anytwo of these four subsequent comparisons indicates a correctly received synchronizing word, we produce an in-synchronization signal to indicate that word synchronization has been achieved, and to indicate that information words can then be accurately read and utilized. However, if less than two ofthese four subsequent comparisons indicate a correctly received synchronizing word, we resume comparison ofthe subsequent digital signals until another initial correct synchronizing word is indicated.

We then compare the nextfoursynchronizing words, and if any two are correct, we produce an insynchronization signal. If less than two are correct, we start again. This process is repeated as often as needed, or until no more synchronizing words are received.

In the accompanying drawings, by way of example only: FIGURE lisa diagram illustrating a digital message for which a synchronizing arrangement embodying the invention can be used; FIG URE 2 is a block diagram illustrating the synchronizing arrangement; and FIGURE 3 is aflowchartofdiagram illustrating the operation of the synchronizing arrangement of Fl GURE2.

While persons of ordinary skill in the art will, after reading this description, appreciate that our preferred synchronizing arrangement can be used with various formats of data messages having various synchronizing words, we have selected the sequential data format of FIGURE 1 to explain the operation of our arrangement. This data format is intended to be used totransmita data message in cellular radiotelephone systems. And while we describe our preferred arrangement with binary types of data, persons skilled in the artwill appreciate that it can be used with other types of data, such as ternary signals. The data format comprises a total of 1032 bits, and the bit numberthat starts each part of the format is indicated.The format of FIGURE 1 starts with 101 dotting bits, which typically are alternate 1's and 0's to achieve bit synchronization. Next, starting with bit 102, the first synchronizing word of 11 bits is transmitted. In the ceilulardata message standard mentioned, this synchronizing word is comprised as follows: 11100010010. While other synchronizing words can be used, the indicated format is desirable in that it has a relatively small chance of being repeated in a message word. Following the first synchronizing word, a first message word of 40 bits starting with bit 113 is transmitted. These bits have binary values that convey the desired message. Next, starting with bit 153,37 dotting bits are transmitted. These are followed by the second synchronizing word which is identical to the first synchronizing word.The second synchronizing word is followed by a second message word, which typically is the same asthefirst message word. This sequence is repeated to provide a total of 11 sequences comprised of dotting bits, a synchronizing word, and a message word. And, the synchronized words are typically equally spaced by 77 bits: 40 bits of a message word plus 37 synchronizing bits.

However, such equal spacing ortime interval is not essential.

One of the reasons that this format was selected was that it typically enables a radio receiver to achieve bit synchronization and word synchronization in a relatively shorttime and with reasonable accuracy. This accuracy is improved if a word synchronizing arrangement in accordance with our invention is utilized.

FIGURE 2 shows a block diagram that illustrates our synchronizing arrangement. While a typical preferred embodiment of our invention would more likely be achieved by means of a microprocessor and associated memory circuits, we have provided the block diagram of FIGURE 2 in ordertofacilitatethe understanding of our arrangement.

As shown, our arrangement includes a receiver 10 which receives and processes incoming signals from either a wire or radio medium, and if necessary, demodulates these signals. If these signals include speech or other information, they can be applied to appropriate circuits. The data signals are applied to a signal conditioner 11 which, if the data is in the form of modulated signals, converts these signals to digital signals having the appropriate or desired voltage levels. These digital signals are applied to a bit synchronization circuit 12 which, as known in the art, produces a clock signal orthe appropriate frequency that is synchronized with the incoming bit signals. The clock signal is applied to various portions of our arrangement as needed.The bit signals are applied to a synchronizing word comparator or comparison circuit 13 which compares the incoming bit signals with a stored synchronizing word having the desired or predetermined bit sequence in a storage circuit 14.

This comparison may be either in series or in parallel.

Each time a correct sequence of synchronizing word bits (such as the 11100010010 mentioned) is found from this comparison, the comparator 13 produces an output signal that is applied to a good synchronizing word counter 15. When reset, the comparator 13 operates in a bit by bit mode to look at each new bitto determine ifthatnew bit plusthe prior (ten) bitsform the correct synchronizing word. After an initial detection of a correct synchronizing word, the comparator 13 operates in a position mode and only looks at the 11 (or appropriate number of) bits which occur at the time or position of the next synchronizing word.

The counter 15 has appropriate outputs that respectively indicate a count of 1 good word, or a count of 2 good words, our a count of 3 or more good words as shown. Each timea countof 1,ora countof2, ora countof3is reached, an enablesignal isappliedtoa synchronising word position indicator 16. If the count of counter 15 is less than 1, the indicator 16 is disabled.

The position indicator 16 is arranged to count clock bits from the circuit 12 so that when the indicator 16 is enabled by the initial detection of a synchronizing word, it can countthe number of bits to indicate the time position or location ofthe next expected synchronizing word. After being enabled by an initial detection of a synchronizing word, the indicator 16 produces an output 1,2,3 or 4 respectivelyforthe time or position in which succeeding synchronizing words 1,2,3 or4 should appear.Thus, with reference to FIGURE 1 again, ifthe first synchronizing word (bits 102 th rough 112) is correctly detected,the position indicator 16 can then count the number of bits to indicate the position ofthe second synchronizing word. This count would be thefirst message word of 40 bits plusthe next 37 dotting bits, so that atthe appearance of bit 190 ofthe second synchronizing word,the indicator16 provides an output signal at output 1 to indicate that the first synchronizing word, after a detection ofthe initial synchronizing word, is in position.An output signal is provided at outputs 2,3 and 4to indicate the time or position ofthe second, third and fourth synchronizing words respectively afterthe initial detection of a synchronizing word. Of course, the initial detection may occur at any location in the message shown in FIGURE 1. Each of the outputs 1,2,3 and 4 are applied to the synchronizing word comparator 13 to cause the comparator 13 to operate in the position mode and lookfora synchronizing word atthe propertime or position.

When the word position indicator 16 produces an output4, this indicatesthatfoursynchronizing word positions have occurred since the initial correctly detected synchronizing word. This 4 output is applied to an enable input of an in-synchronization output gate 18.

This 4 outputfrom the indicator 16 is applied to open or enable an in-synchronization output gate 18. If the good word counter 15 has reached a count of 3 or more, its 3 output is passed by the enabled gate 18 to indicate thatword synchronization has been achieved by detection ofa first correct synchronizing word, and by detection oftwo additional synchronizing words during the nextfoursynchronizing word positions.

When passed by the gate 18, this in-synchronization signal can be utilized by a decode circuit 21 to indicate to the receiver 10 or other circuits that word synchronization has been achieved, and hencethe message words of FIGURE 1 can be accurately and correctly decoded or utilized.

The position indicator 16 is also provided with an output to indicate the end ofthe position ofsynchro- nizing word 4. This output is applied to resettheword comparator 13 for bit by bit comparison, and to reset the word counter 15 and the position indicator 16to zero. Upon this reset, the arrangement starts looking for an initial synchronizing word again, whether an in-synchronization output was produced orwas not produced.

FIGURE 3 shows a flowchart ordiagram illustrating the operation of the arrangement of FIGURE 2, and also illustrating the operation that wouid be performed by a microprocessor and appropriate memory circuits to achieve the same function as that provided bythe arrangement of FIGURE 2. With respect to FIGURE 3, a startfunction is initiated by a start circuit 30 to clear or resetthevarious circuits as indicated by the block 31. This permits the sequential digital bits to be shifted into the word comparator as indicated by the block 32.

Bits continue to be shifted into the word comparator as long as no initial synchronizing (sync in FIGURE 3) word is detected as indicated by the decision block 33.

However, once an initial synchronizing word is detected, the circuit waits for additional synchronizing and message words as indicated bythe block 34. Each time a subsequent synchronizing word position occurs, the decision block 35 determines whether a correct synchronizing word is present or detected. If the determination is no, a word counter 37 is incremented. If the determination is yes, a correct synchronizing word counter 36 is incremented, which in turn increments the word counter37. Thus the word counter 37 is incremented each time a correct or incorrectsynchronizing word appears or is detected.

The count output of the block 37 is applied to a decision block 38 which determines when five synchronizing words (including the initial synchronizing word) have been received. As long as less than five synchronizing words (including correct and incorrect) have been received, the decision block 38 keeps the block34waiting forsynchronizing and message words. When five synchronizing words (including correct and incorrect) have been received, a block39 opens the output gate 18.Adecision block40 determines whether three of these five words are correct. If not, the arrangement is restarted to look for an initial synchronizing word on a bit by bit comparison. lfthreewords are correct, an in-synchronization signal is sent by the block 41 to the output gate 18 of FIGURE 2. If the decision block 42 indicates the gate 18 is open, the in-synchronization signal is applied to a block43 two decode the messagewords.Afterthis decoding, the circuit is restarted to lookfor another message.

Summary It will thus be seen that we have provided an improved word synchronizing circuit which operates to provide word synchronization in response to a first good synchronizing word detection, followed by two additional good synchronizing word detections during the nextfoursynchronizing word positions. And while we contemplate that the synchronizing words are equally spaced in time, this may not be necessary in some applications. With our synchronizing arrangement operating with the data message of FIGURE 1, we have found that with a bit error rate of 0.05, our synchronizing arrangement produces a correct insynchronization output signal for 69.2% ofthe time, and with an error orfalse indication of an insynchronization condition only once every 39.8 hours.

While the arrangement shown in the FIGURES and described is our preferred embodiment, persons skilled in the art will appreciate that modifications may be made. Therefore, while our invention has been described with reference to a particular embodiment, it is to be understood that modifications, particularly in terms of circuit implementation, may be made without departing from the spirit of the invention or from the scope ofthe claims.

Claims

1. An improved arrangementforachieving syn chronizationwith a data message comprising a synchronizing word transmitted a plurality oftimes during said message, comprising: a. input means for receiving said transmitted synchronizing words; b. means for storing a predetermined synchronizing word; c. means coupled to said input means and to said storing meansforcomparing each received synchronizing word with said stored synchronizing word, and producing a first signal in response to each received synchronizing word that corresponds to said stored synchronizing word;; d. and output means coupled to said comparing means for producing an in-synchronization signal in reponse to one of said first signalsfollowed by the production of at least two more of said first signals during the nextfour comparisons of said received synchronizing words with said stored synchronizing word.

2. The improved arrangement of claim 1 wherein said transmitted synchronizing words are spaced at uniform intervals during said message, and wherein said comparing means makes said next four compari- sons at said uniform intervals.

3. The improved arrangement of claim 2 wherein said transmitted synchronizing words are spaced at predetermined intervals during said message, and wherein said comparing means makes said next four comparisons at said predetermined intervals.

4. For use in a communication system having at least a transmitter at a first location and a receiver at a second location for receiving digital messages from said transmitter, synchronizing apparatus comprising: a. means coupled to said receiver for deriving digital messages therefrom, each derived digital message having a plurality of synchronizing words occurring at locations therein which are spaced at predetermined intervals; b. means coupled to said deriving means for producing a synchronizing signal in response to each derived synchronizing word having a predetermined sequence of digital values; c. counting means coupled to said deriving means for counting said synchronizing word locations, and coupled to said producing meansforcountingsaid synchronizing signals;; d. and means coupled to said counting means for producing an in-synchronization output signal in responseto at leasttwo synchronizing signals during the next four counted synchronizing word locations following the production of the first synchronizing signal during a digital message.

5. The synchronizing apparatus of claim 4 wherein said digital message has a plurality of identical synchronising words occurring at locations therein which are spaced at predetermined equal intervals.

6. An improved method for detecting a digital synchronizing word comprised of a sequence of digital signals having a predetermined characteristic and appearing at a plurality of spaced predetermined times in a digital message, said method comprising the steps of: a. comparing said sequence of digital signals with a stored digital word and producing a first detected word signal in responsetothefirstsequence of digital signals in a message being the same as said stored digital word; b. comparing said sequence of digital signals with said stored digital word at said predetermined times subsequentto said first detected word signal being produced, and producing a second detected word signal in response to each sequence of digital signals at subsequent predetermined times being the same as said stored digital word;; c. counting said second detected word signals subsequentto said first detected word signal; d. and producing an in-synchronization signal in responseto production of at leasttwo detected word signals during said next four subsequent predetermined times.

7. The improved method of claim 6 and, in the absence of at leasttwo detected word signals during said next four subsequent predetermined times, comparing said sequence of digital signals with said stored digital word until said first detected word signal is produced.

8. The improved method of claim 6 and, in the absence of two second detected word signals during said four subsequent predetermined times, further comprising the step of resetting the count of detected word signals to zero, and comparing said sequence of digital signals with said stored digital word until said first detected word signal is produced.

9. An improved arrangement for achieving synchronization with a data message comprising serial bits forming a synchronizing word transmitted a plurality of times during said message, comprising: a. input means for receiving said transmitted synchronizing words; b. meansforstoring a predetermined synchroniz ingword; c. means coupled to said input means and to said storing means for comparing received serial bits with said stored synchronizing word, and producing an initial signal in response to an initial comparison in which a series of bits correspond to said stored synchronizing word, and producing a good word signal in response to each subsequent comparison in which each series of bits correspond to said stored synchronizing word;; d. and output means coupled to said comparing means for producing an in-synchronization signal in response to at leasttwo ofsaid good word signals during the next four subsequent comparisons of said groups of subsequent series of bits with said stored synchronizing word.

10. The improved arrangement of claim 9 wherein said initial comparison is made each time a new bit is received.

11. The improved arrangement of claim 9 wherein each of said subsequent comparisons is made in response to a synchronizing word position indication.

12. The improved arrangement of claim 10 where- in each of said subsequent comparisons is made in response to a synchronizing word position indication.

13. The improved arrangement of claim 9 and comprising means to restart said initial comparison following said nextfour comparisons of said groups.

14. The improved arrangement of claim 10 and comprising means to restart said initial comparison following said nextfour comparisons of said groups.

15. The improved arrangement of claim 11 and comprising means to restart said initial comparison following said nextfour comparisons of said groups.

16. The improved arrangement of claim 12 and comprising means to restart said initial comparison following said nextfour comparisons of said groups.

17. An improved method for detecting a digital synchronizing word comprised of a sequence of digital signals having predetermined characteristic and appearing ata pluralityofspaced predetermined times in a digital message, said method comprising the steps of:: a. initially comparing said sequence of digital signals each time a new signal occurs in said sequence with a stored digital word and producing an initial signal in response to the first sequence of digital signals in a message being the same as said stored digital word; b. subsequently comparing said sequence of digital signals on a time position basis with said stored digital word at said predetermined times subsequent to said initial signal being produced, and producing a second signal in response to each sequence of digital signals at subsequent predetermined times being the same as said stored digital word; c. counting said second signals subsequentto said initial signal; ; d. producing an in-synchronization signal in re sponseto production of at leasttwo of said second signals during said nextfoursubsequent predeter mined times; e. and starting said initial comparison following said four predetermined times.