JPH06131827A - Error detection correction processing device - Google Patents

Abstract

PURPOSE:To reduce a correction word storage region and a storage region of error flags which indicate the result of error detection and correction, to reduce IC chip areas and to reduce the cost. CONSTITUTION:Against the reproduced signals to which dual correction words are added, detection correction processes are performed by a first error detection correcting circuit 103 and a second error detection correcting circuit 104. Then, data processing is performed using one frame which constituted by a specific number of tracks, for example 12, as a unit and in order to synchronize video signals and audio signals, equivalent to three frames of a data word storage region is secured in a data word and correction word RAM 106. By conducting error detection correction processes for every track, no need exists to have equivalent to three frame correction word storage region against equivalent to three frame data words. Moreover, two error flag storage regions caused by the first and the second error detection correction processes are shared in an error flag RAM 105.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing apparatus, and more particularly to an error detection / correction processing apparatus used for voice signal recording / reproducing processing of a consumer digital VTR.

[0002]

2. Description of the Related Art In recent years, error detection / correction processing devices have been developed by CD (Com
It is used in various digital signal recording / reproducing devices such as a pact disk) and a DAT (Digital Audio Tape). As a conventional error detection and correction device, for example, Japanese Patent Publication No. 3-136
There is one disclosed in Japanese Patent Publication No. 70.

The conventional error detection / correction processing apparatus will be described below. FIG. 7 shows a block diagram of this conventional error detection / correction processing device. In FIG. 7, 7
Reference numeral 01 is a signal source to be reproduced, 702 is a reference signal generator that is the basis of digital signal processing, 703 is a digital signal arithmetic circuit for executing error detection and correction processing, 704 is a signal word RAM, and 705 includes an interpolation processing circuit section. The D / A converter 706 is a crystal oscillator that serves as a reference for the output signal.

The operation of the error detection / correction processing apparatus configured as described above will be described below.

A signal source 701 inputs a signal in a format in which a correction word is added to a data word. The digital signal arithmetic circuit 703 performs error detection and correction processing on this input signal, and an error flag is generated as the processing result. After the correction processing, the correction word written in the correction word storage area in the RAM 704 is no longer necessary, and it remains empty until a new correction word is written. Utilizing this empty state, the used correction word storage area is set as the error flag storage area, and the error flag indicating the correction result is set to R.
Write to AM704. The D / A conversion circuit 705 uses the corrected data and the error flag to interpolate the data that cannot be completely corrected, and the crystal unit 706.
The audio signal is output with reference to.

With the above configuration, an error detection / correction processing device is realized which has a reduced storage area which does not require a dedicated RAM for an error flag indicating the result of error detection / correction processing.

[0007]

The above-mentioned conventional structure is C
It is intended for D, and is premised on the processing of a signal recorded on one continuous track. However, in the case of processing data in units of frames, which is a basic unit for performing error detection and correction processing, in order to secure a storage area for error flags, it is necessary to correspond to each track forming a frame. There has been a problem that the correction word storage area must be provided, and the correction word storage area also becomes large as the number of tracks constituting a frame increases.

The present invention solves the above-mentioned problems of the prior art by performing error detection and correction processing for data of a plurality of frames within a correction word storage area for several tracks to reduce the storage area of a memory such as a RAM. It is an object to provide a correction processing device.

[0009]

Since a correction word is necessary only during error detection and correction processing, when data processing is performed in units of frames composed of a plurality of tracks,
The error detection / correction process is performed for each track of the input signal, so that the correction word that needs to be retained can be reduced from the frame to several tracks. Therefore, in order to achieve the above object, the error detection / correction processing device of the present invention is provided with, as a correction word storage area, only a storage area for several tracks as a RAM for a data word storage area for a plurality of frames.

Since the correction word storage area has only the tracks necessary for the correction process, it is not possible to write the error flags for all the data of a plurality of frames in this area, and it is necessary to secure the error flag storage area exclusively. is there.

In the process of performing error detection and correction processing on a signal sequence in which a double correction word of an inner code which is a first error correction word and an outer code which is a second error correction code is added to a data word. Two types of error flags occur.

The error detection / correction processing performed on the data word and the outer code using the inner code is referred to as a first error detection / correction processing, and the error flag indicating the processing result is referred to as a first error flag. By referring to the first error flag, the error detection / correction processing performed on the data word using the outer code is referred to as the second error detection / correction processing, and the error flag indicating the processing result is referred to as the second error flag. As described above, the first and second types of error flags occur.

The first error flag is used in the second error detection / correction processing and is no longer necessary after the second error detection / correction processing. In addition, the second error flag is used for the interpolation process for the data word that could not be corrected even by the double error detection and correction process, and is not necessary after the reference. The first error flag is generated in several bits for the data word and the arrangement of several bytes of the inner code and the arrangement of the several bytes of the outer code and the inner code, while the second error flag is generated for the data word. Since the error occurs every byte, the storage area for the second error flag becomes larger than the storage area for the first error flag. Therefore, only the storage area for the second error flag is provided as a RAM, and the storage area for the first error flag is secured in the storage area for the second error flag that has become empty after the interpolation processing. It is possible to share the storage area for the types of error flags.

As described above, the error detection and correction process can be performed by using the RAM composed of the data word storage area for a plurality of frames, the correction word storage area for several tracks, and the error flag storage area.

[0015]

According to the present invention, the data word of the input signal to be reproduced is stored in the unit of frame composed of a plurality of tracks by the above-mentioned structure, thereby enabling the processing such as editing in the unit of frame, and each track. By writing the more reproduced correction word in the old correction word storage area after error detection and correction processing, even if the correction word storage area that needs to be secured as a RAM is significantly reduced, the correction word RAM for each track It is possible to realize an error detection / correction processing device that performs the same error detection / correction processing as that of the above-described case without deteriorating the ability.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an error detection / correction processing device according to an embodiment of the present invention. Reference numeral 101 is a signal source composed of a magnetic tape / recording / reproducing system, 102 is a reference signal generator that is the basis of digital signal processing, 103 is a first error detection / correction circuit, 104 is a second error detection / correction circuit, and 105 is an error. R for error flag indicating detection and correction result
AM and 106 are RAs for data words and correction words
M and 107 are interpolation circuits, and 108 is a D / A converter.

The embodiment shown in FIG. 1 is a block of error detection and correction processing for reproducing a voice signal of a digital VTR, and FIG. 2 shows the entire structure of the digital VTR. 201 is an A / D converter for video signals, 202 is a recording video signal processing circuit,
203 is an error correction outer code generator for video signals, 204 is an A / D converter for audio signals, 205 is a recorded audio signal processing circuit for performing processing such as shuffling, and 206 is an error correction outer code generator for audio signals. 207 is a multiplexer for multiplexing video and audio signals, 208 is an error correction inner code generator, 209 is a modulator, 210 is a VTR recording / reproducing system for recording / reproducing the modulated signal on a tape, and 211 is a demodulator ,
212 is an error correction inner code decoder, 213 is a demultiplexer, 214 is an error correction outer code decoder for video signals, 2
15 is a reproduction video signal processing circuit, 216 is a video signal D /
An A converter, 217 is an error correction outer code decoder for audio signals, 218 is a reproduced audio signal processing circuit for performing processing such as deshuffling, and 219 is an audio signal D / A converter.

In the embodiment shown in FIG. 1, the error correction inner code decoder 212 and the voice signal error correction outer code decoder 21 shown in FIG. 2 are used.
7, a reproduced voice signal processing circuit 218 and a D / A converter for voice signals.

FIG. 3A shows an example of the tape format when recording / reproducing on the VTR magnetic tape, and FIG. 3B shows the structure of the cylinder head. In the 525/60 (number of horizontal scanning lines / frame frequency) system, 10 tracks are 1 frame, and in the 625/50 system, 12 tracks are 1 frame. In the present embodiment, it is assumed that the pair head as shown in FIG. 3B is used to record / reproduce on / from the magnetic tape. Therefore, the error detection / correction processing is executed for every two tracks of the reproduced signal. The video signal and the audio signal are written on the same track, and when the target audio signal data portion is taken out and arranged in an array to which a correction code is added, it becomes as shown in FIG.

Six blocks from the first sync block to the sixth sync block are composed of a data word and an inner code which is a correction word for the data word, and three blocks from the seventh sync block to the ninth sync block are the second blocks. It is composed of an outer code which is a correction word used for the correction process of 1 and an inner code which is a correction word for the outer code.
These 9 blocks are sequentially recorded from the first sync block in the audio signal area on the magnetic tape shown in FIG.

The signal reproduced from the signal source 101 is a signal obtained by adding a correction word to a data word of 2 channels which is quantized by 16 bits, and the data word per track is 768 (128 × 6) bytes. The error correction outer code is 384 (128 × 3) bytes, and the error correction inner code is 72 as the correction word added to this data word.
It is (8 × 9) bytes.

RAM 10 for voice data and correction words
6 has an 8-bit structure, and an example of its RAM map is shown in FIG.

A storage area for a plurality of frames is required as a data word storage area in order to absorb the jitter of the reproduction synchronization signal generated from the reproduction signal and adjust the processing time of the video signal and the audio signal. Therefore, a data word storage area for three frames is provided as a RAM for data words and correction words.
Reserved on 106. Here, the data word storage area for one frame has a large number of constituent tracks 625/50.
A storage area for 12 tracks is secured corresponding to the system. The correction word storage area is a storage area for four tracks R
Secure on AM 106. Since the second error flag is generated for each byte of the data word, the storage area for three frames corresponding to the data word storage area is secured in the error flag RAM 105.

The operation of the error detection / correction processing apparatus of the present embodiment having the above-described configuration will be described below.

The first error detection / correction processing is executed for each sync block of the signal reproduced from the signal source 101, and 6 sync blocks of data words and the latter half 3 sync blocks are assigned to designated addresses of the data word and correction word RAM 106. Write the outer code of the minute. Since the inner code is no longer needed after the first error detection / correction process, no storage area for the inner code is provided. As a result of the first error detection / correction process, for example, 2 bits per 1 sync block, that is, 18 per track The first error flag generated in bits is set to RAM1
Write to the free area of 05.

With respect to the data word and the error correction outer code written in the RAM 106, the first error flag is referred to for the second code.
Error detection / correction processing is performed, and the corrected data is written again in the same address of the RAM 106. After this process, the outer code, which is the correction word written in the correction word storage area in the RAM 106, is no longer necessary, and the next state for writing the outer code is waited. The second error flag is set in the RAM 106.
Corresponding to the data word of
Interpolation processing is performed on the data that could not be corrected by the second error detection and correction processing.

It is preferable to store two kinds of both error flags in the RAM 105 in association with the track in which the data word to be processed is written, but it is preferable that the first error flag is stored in the second error detection / correction process. When reference is made, if the reference data is written in the storage area in the same track, it may occur that both data must exist at the same address at the same time. There is a need.
The second error flag is referred to by the interpolation circuit 107 for confirmation of the presence / absence of interpolation in 1.5 frames after the track on which the error detection / correction process is performed. After the reference, the second error flag is no longer necessary and the error flag storage area becomes empty. The offset is added to the address of the first error flag, the second error flag is referred to in the interpolation process, and then the second error detection and correction process is performed on the same track to write the second error flag. It is necessary to write the first error flag to the second error flag storage area that is in the empty state until the error is written to prevent the write addresses of both error flags from matching.

The interpolation circuit 107 calls the data words after error detection and correction written in the RAM 106 in chronological order, refers to the second error flag written in the error flag RAM 105, and performs double error detection and correction processing. Interpolation processing such as pre-holding and binary averaging is performed on the data that cannot be corrected. The D / A converter 108 converts the interpolated signal into an analog audio signal and outputs it.

625 while referring to the RAM map diagram (FIG. 5) and the operation timing diagram of the error detection / correction process (FIG. 6)
In the case of the / 50 system, the operation timing with the means for utilizing the storage area on the RAM will be described.

The audio signal data of two channels are divided into the first to sixth tracks and the seventh to twelfth tracks for each channel and stored. The error detection and correction processing for the data words on the first to sixth tracks uses the first and second correction word storage areas, and the error detection and correction processing for the data words on the seventh to twelfth tracks uses the third and fourth corrections. Use word storage area.

Data words and correction words for two tracks are reproduced from the signal source 101, and error detection and correction processing is performed by the first error detection and correction circuit 103 so that the data words are stored in the first and second tracks of the RAM 106. In the area,
The outer code of the correction word is written in the first and second correction word storage areas of the RAM 106. At the same time, the first error flag is written in the RAM 105.

In the second error detection / correction circuit 104,
R is generated by generating an address for the data of the first and second tracks.
Read data word and correction word from AM106,
At the same time, the second error detection / correction process is performed by referring to the first error flag written in the RAM 105. After the correction process, write the corrected data word to the same address,
RAM for the second error flag corresponding to each data word
Write to 105. When the second error detection and correction processing is completed for all the data words in the first and second track storage areas of the RAM 106, the first and second correction word storage areas of the RAM 106 become empty.

Subsequently, the first error detection and correction are performed on the reproduced signals for the two reproduced tracks, the data words are written in the third and fourth tracks of the RAM 106, and the outer code which is the correction word of both tracks is written. Are written again in the first and second correction word storage areas used in the above processing. The correction words of the seventh to twelfth tracks are the third and third.
This error detection / correction processing is repeated using the fourth correction word storage area, and the error detection / correction processing of the data word for one frame is performed.

The data word after error detection and correction is read out by the interpolating circuit 107 after 1.5 frames, so that the first
Of the error detection and correction circuit 103 and the second error detection and correction circuit 104, and the RAM 10 of the interpolation circuit 107
5,106 can always be accessed for data on different tracks.

In the case of the 525/60 system, of the data word storage areas shown in FIG. 5, 10 track storage areas other than the 6th track and the 12th track are used as the 1-frame data word storage area. The operation timing of FIG. 6 is the same as that of the 625/50 system as the operation of the error detection / correction processing except that one frame is changed from 12 tracks to 10 tracks.

When the storage area for the correction word is secured for each track as in the conventional example, 13824 (3 × 12 × 3 × 128) is used instead of the RAM for the interpolation flag.
It requires RAM for byte correction words. On the other hand, in the present invention, the RAM for the correction word is 153
It only requires an area of 6 (4 x 3 x 128) bytes. The error flag RAM that is newly required is 172
8 bytes (3 × 12 × 3 × 128 bits) is enough,
The RAM area of about 10560 bytes can be saved.

Although the error detection and correction of the voice signal are described in the present embodiment, conversely, when encoding, a correction word storage area for several tracks is provided for one frame of data word to form a frame. By performing the encoding for each track, the processing can be performed with the same RAM configuration as that at the time of decoding, and the RAM can be shared during recording and reproduction. The same applies to the case where the error detection and correction processing is performed on the data word of one frame in the correction word storage area for several tracks even for the video signal to which the double correction word is added.

As described above, according to the present embodiment, by using the unused RAM free area, the storage area of the memory such as RAM can be reduced and effectively utilized.

[0040]

As described above, according to the present invention, error detection and correction processing is performed in a correction word storage area for several tracks for data of a plurality of frames, and two types of data generated in the process of the error detection and correction processing are performed. By sharing the storage area of the error flag, it is possible to realize an error detection / correction processing apparatus in which the storage area of a memory such as a RAM is reduced, and it is possible to save the IC chip area and reduce the cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an error detection / correction processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an entire digital VTR including the same embodiment.

FIG. 3 is a schematic view showing an example of a tape format of a digital VTR and a configuration of a cylinder head included in the embodiment.

FIG. 4 is a schematic diagram showing an example of a configuration of a track which is a basic unit for performing error detection and correction processing of the embodiment and an example of a recording order on a tape when processing is performed in a recording / reproducing system.

FIG. 5 is a schematic diagram showing an example of a map diagram of a RAM in the same embodiment.

FIG. 6 is an operation timing chart of error detection / correction processing in the embodiment.

FIG. 7 is a block diagram showing a configuration of an error detection / correction processing device in a conventional example.

[Explanation of symbols]

 101 Signal Source 102 Reference Signal Generator 103 First Error Detection and Correction Processing Circuit 104 Second Error Detection and Correction Processing Circuit 105 Error Flag RAM 106 Data Word and Correction Word RAM 107 Interpolation Circuit 108 D / A Conversion Circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobuaki Mizuguchi 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Toshihide Ishimoto 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (2)

[Claims] 1. A digital signal processing circuit for performing error detection / correction and interpolation processing on an input signal in which first and second double correction words are added to a data word, and the data word, first and second A first memory circuit having a memory area for the correction word, a first error flag indicating a result of performing the first error detection and correction processing on the input signal, and first and second error detection and correction processing. A second storage circuit having a storage area for a second error flag indicating the result of the execution, and a signal train in which the first and second double correction words are added to the data word is defined as one track, and When one frame is made up of a predetermined number of the tracks, the error detection and correction process is performed for each track in the frame, and the correction word reproduced from each track is finished in advance. An error detection / correction processing device characterized by performing error detection / correction processing in a storage area smaller than the total number of tracks constituting one frame by writing in the old correction word storage area. 2. An input signal is subjected to a first error detection / correction process, and a first error flag indicating a result of the first error detection / correction process is generated, and then the first error flag is referred to. , A second error detection / correction result which is used to perform a second error detection / correction using the data word subjected to the first error detection / correction processing and the second correction word, and which is used for interpolation processing of uncorrectable data. 2. In the process of generating the second error flag, the storage area for the first error flag is written in a storage area in the storage area for the second error flag in which error detection and correction processing has been completed. The error detection and correction processing device described.