JPH04241389A - Image processor - Google Patents

Abstract

PURPOSE:To always excellently display a video image on a window display screen even when the display position or the screen size of the window display screen is changed and to display the video image on the window display screen by optionally enlarging and reducing it. CONSTITUTION:The video image data (A) of one frame is stored in a dual port video RAM 3. After the display position and the screen size of the window display screen are set to an X direction FIFO (dual port serial access memory) 10 and a Y direction FIFO 11, address data that the access of the RAM 3 should be executed is written. Then, dot data among the data (A) corresponding to the specified variable power rate of an image read out of the RAM 3 by the address data and superimposed on the data displayed on a computer side. Then, it is displayed on a computer screen.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for displaying a video image in a window formed in a part of a display screen of a personal computer or the like.

0002

2. Description of the Related Art Conventional image processing devices that display video images on the display screen of a personal computer, etc. generally have a fixed size and display position of the window display screen for the video image. Video R
AM is designed to have a capacity that corresponds to the window display screen size, and the video image data from the TV or VTR is not loaded into the video RAM with the specified capacity in an appropriately thinned state. , the decimated video image data is read out and displayed on a window display screen.

[0003] When the video image is a moving image, the video image data is taken in at a thinning level according to the window display screen size specified by the computer, so that the video image data can be displayed well within the window display screen that has been enlarged or reduced in screen size. can be displayed.

0004

However, if the video image is a still image, the video image data once loaded into the video RAM is constantly displayed, so even if the window display screen size is expanded, The video image can only be displayed in the original size window area, and cannot be displayed in the enlarged screen area. Reducing the window display screen size will result in parts of the video image being missing. Furthermore, it is not possible to enlarge and display a portion of the video image on a window display screen of a fixed size.

[0005] The present invention was devised in view of the above-mentioned circumstances, and the present invention always maintains a good quality even when the size or display position of the window display screen is changed, regardless of whether the video image is a moving image or a still image. It is an object of the present invention to display a video image on a window display screen of the same size, and to arbitrarily enlarge or reduce the video image for display on a window display screen of the same size.

[0006]

[Means for Solving the Problems] An image processing device according to the present invention includes a dual port video RAM that temporarily stores video image data for one frame, and a window display screen whose display position and screen size can be freely controlled on a computer screen. In addition to writing address data on the dual port video RAM according to the specified image scaling ratio (enlargement/reduction ratio) that can be set to The present invention is characterized by comprising a dual port serial access memory that sequentially reads out the address data in accordance with a corresponding range of dot clocks and provides the address data to the dual port video RAM.

[0007]

[Operation] The dual port video RAM temporarily stores one frame of video image data, whether it is a moving image or a still image. On the computer side, a command is given to the dual port serial access memory to set the window display screen from one position to another on the computer screen, and to set the image scaling ratio (enlargement/reduction ratio). . The dual port serial access memory sets the display area (display position and screen size) of the window display screen on the computer screen according to the command, and writes address data according to the image magnification ratio. Then, by accessing the dual port video RAM with the address data, dot data corresponding to the image magnification is read out of one frame of video image data stored in the dual port video RAM.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the electrical configuration of an image processing apparatus according to an embodiment of the present invention.

In the figure, 1 is a decoder that extracts R, G, and B signals from a video signal input from a television receiver or video tape recorder, and 2 is a decoder that converts each of the R, G, and B signals into digital data. /D converter 3 converts the digitally converted R, G, B video image data into 1
Dual port video RA that temporarily stores only frames
It is M. This dual port video RAM 3 serially writes one frame worth of video image data via its serial port, and selects one frame worth of video image data according to the address data given from the enlargement/reduction address generation circuit 4. It is configured to read an appropriate number of dot data from a random port. 5 is R read from the random port,
A D/A converter that converts G, B dot data into analog R, G, B signals, 6 is the R, G from the D/A converter 5
, B signals and the R, G, B signals on the computer side. 7 is a video RAM for temporarily storing display data on the computer side, and 8 is a D/A converter.

FIG. 2 is a block diagram showing the configuration of the enlargement/reduction address generation circuit 4 in FIG. 1. As shown in FIG.

10 and 11 are dual-port serial access memories (hereinafter simply referred to as FIFO) consisting of FIFO (first-in, first-out) that temporarily stores address data (relative addresses) in the X and Y directions, and 12 is a FIFO 10. , converts the relative address input from 11 into a physical address and connects it to the dual port video RA.
This is a memory address generation circuit that is applied to the random port of M3.

The X-direction FIFO 10 receives a reset signal RS.
When the write reset port RS (W) becomes active, the address pointer is initialized, and when the write clock port WCK becomes active due to the chip select signal CS1, the relative address data sent via the data bus is incremented by the address pointer. Write them down one by one.

The manner in which relative address data is written into the X-direction FIFO 10 will be explained in detail with reference to FIG. [A] shows one frame of video image data stored in the dual port video RAM 3, and [B] shows window display image data displayed in a window on the computer screen. In addition, (a) shows the storage area corresponding to the display area in the X direction where the window display image data [B] is displayed on the computer screen, and (b) shows the storage area corresponding to the display area in the Y direction. Shows the area. The display position of the window display image data [B] is set depending on where the starting points of the X-direction storage area (a) and the Y-direction storage area (b) are determined.
The screen size of the window display image data [B] is set depending on how the sizes of the direction storage area (a) and the Y-direction storage area (b) are determined.

Assume that video image data [A] has, for example, 512 dots in the X direction. The X-direction FIFO 10 has a storage capacity equivalent to the X-direction resolution (for example, 1280 lines) of the computer screen, and the Y-direction FIFO 11 has a storage capacity equivalent to the Y-direction resolution (for example, 1024 lines). In the storage areas other than the X-direction storage area (a) in the X-direction FIFO 10, the dummy address is, for example, 600 (
Any address other than 0 to 511 is acceptable). In the X direction storage area (a), the video image data [A] is stored in the X direction as the window display image data [B].
For example, if you want to reduce the size to 1/5 in the direction, it means thinning out the video image data [A] every 5 dots, and creating relative address data like 0, 5, 10, 15, 20...510. is written. If a part of the video image data [A] is to be enlarged, for example, twice in the X direction as the window display image data [B], then the dots of the video image data [A] will be repeated, and 3
Relative address data such as 0, 30, 31, 31, 32, 32, . . . is written. When the size is the same, 0,
Relative address data is written like 1, 2, 3, 4...511. The same applies to writing relative address data to the Y-direction FIFO 11.

Relative address data is read out from the X-direction FIFO 10 as follows. Horizontal synchronization signal HDI
When the read reset port RS (R) is activated by SP, the address pointer is initialized, and when the read clock port RCK is activated by the dot clock signal DotCK from the computer side, the relative address data is sent from the X-direction FIFO 10 while incrementing the address pointer. are sequentially read out and sent to the memory address generation circuit 12. The process is basically the same when relative address data is read from the Y-direction FIFO 11, but the address pointer is initialized using the vertical synchronization signal VDISP.
The address pointer is incremented by the horizontal synchronization signal HDISP.

The memory address generation circuit 12 operates in the X direction F.
By generating physical address data based on the relative address data input from the IFO 10 and the Y-direction FIFO 11 and giving this to the dual port video RAM 3, predetermined dot data in the video image data [A] is transferred from the random port to the D/ Output to A converter 5.

The D/A converter 5 converts the video image data of predetermined dots read from the random port of the dual port video RAM 3 into analog R, G, B signals and sends them to the mixing circuit 6. On the other hand, on the computer side, out of the display data temporarily stored in the video RAM 7, data corresponding to the window display screen is read out serially and converted into analog R, G, B signals by the D/A converter 8. After being converted, the mixing circuit 6
will be sent to. The mixing circuit 6 superimposes the R, G, B signals from the dual port video RAM 3 side on the R, G, B signals from the computer side, and sends the superimposed signals to a display device (not shown). As a result, on the computer screen, the video image is displayed on the window display screen under the specified image magnification ratio.

In this case, since the dual port video RAM 3 temporarily stores one frame of video image data, it can be used in any display area (display position and screen size) without distinguishing between moving images and still images. Window display image data [B] with image magnification ratio of
can be displayed.

[0019]

Effects of the Invention The display position and screen size of the window display screen can be arbitrarily set in the dual port serial access memory. In addition, one frame of video image data is stored in the dual port video RAM regardless of whether it is a moving image or a still image, and dot data is thinned out and read out from that one frame of video image data according to the image magnification ratio (in the case of reduction). ), reading out the same dot data repeatedly (in case of enlargement)
Therefore, even though the display area of the window display screen is variable, a good video image can always be displayed. Further, on a window display screen having an arbitrary screen size determined as described above, a video image can be reduced or enlarged to an arbitrary size and displayed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the electrical configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of an enlargement/reduction address generation circuit in the embodiment.

FIG. 3 is a conceptual diagram of image processing in the embodiment.

[Explanation of symbols]

3 Dual port video RAM 4 Enlargement/reduction address generation circuit 6 Mixing circuit 10 X direction FIFO (dual port serial access memory) 11 Y direction FIFO (dual port serial access memory) 12 Memory address generation circuit

Claims (1)

[Claims] 1. A dual-port video RAM that temporarily stores video image data for one frame, and a display position and screen size of a window display screen on a computer screen that can be arbitrarily set and a specified image scaling ratio (
Address data is written on the dual port video RAM according to the scaling ratio), and sequentially according to the dot clocks in the range corresponding to the display position and screen size of the window display screen among the dot clocks output from the computer. and a dual port serial access memory for reading out the address data and applying it to the dual port video RAM.