KR950004217B1 - Vga system - Google Patents

Abstract

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Description

VG's Cursor Processing System

1 is a general cursor data processing block diagram.

2 is a block diagram of the cursor processing system of the present invention VG.

3 is a detailed block diagram of a cursor data output unit in FIG. 2;

* Explanation of symbols for the main parts of the drawings

100: cursor data output unit 110: interface

111: decoder 112: latch

120: memory control unit 121: light control unit

122: lead control unit 130: S RAM

140: data buffer 150: address generator

160: display using memory 170: first-in, first-out

180: register unit 190: CALTI control unit

200: attribute part 210: Dee

220: screen

The present invention relates to VGA's cursor data processing technology. In particular, in displaying a cursor on a screen, the cursor data is not stored in an external display memory but stored in an SRAM to increase efficiency. It is related to VG's cursor processing system.

FIG. 1 is a block diagram of a general VG cursor processing. As shown in FIG. 1, a register section 1 for temporarily storing various information about a cursor and a display memory 3 for accessing a normal mode and cursor data at the same time. A memory control unit 2 for generating an address, a display memory using a DRAM, which is divided into two areas for storing video data to be displayed on a screen, and stores cursor data having a predetermined size (64 × 64 × 2 bits). A control unit 4 for controlling the access of the display memory 3 while controlling the access of the display memory 3 by receiving a control signal of a cursor from the display unit 3 and the register unit 1; Cursor data for controlling the cursor data supplied from the display memory 3 to the attribute unit 200 under the control of the controller 4. A furt 5 and a SALTI control unit 6 which receives a normal display signal ND from the outside, receives a X and Y coordinate value of a cursor from a register unit 1, and controls a display on a STI. A first-in first-out machine (7) for receiving video data from the display memory (3) and first-in first-out, and the output and first-in-first-out machine of the cursor data buffer (5) under the control of the CALTI control unit (6). An attribute unit 8 for controlling the output of (7), and a decibel 9 for converting the digital data for red, green, and blue output from the attribute unit 8 into an analog signal and outputting the analog signal to the CRT. The operation of the conventional system configured as described above is as follows.

The central processing unit (not shown) stores data relating to the enable, shape, and mode of the cursor in the control register Rl of the register unit 1, and the cursor data is stored in the pattern register R2. Is stored in the X coordinate register (R3) from the upper left corner of the screen to the coordinates where the cursor is located horizontally, and in the Y coordinate register (R4) the cursor is located vertically from the upper left corner of the screen. The coordinates of where the is located

When the display period is reached, the normal display signal ND is output on the CALTI control unit 6 so that the display memory 3 is accessed by the memory control unit 2 in the normal mode. In this case, the data for the display area is accessed.

The video data output from the display memory 3 is supplied to the DC 9 through the first-in, first-out part 7 and the attribute part 8 under the control of the control part 4, and is output from the red, Green and blue analog signals (R), (G) and (B) are output to CALTI to form a screen 10.

In the state where the cursor position data values of the registers R3 and R4 of the register unit 1 are the same as the horizontal and vertical position values of the current screen, the hardware cursor data is read at the horizontal rare time. The display memory 3 is accessed by sequentially increasing the address starting from the time point at which the signal CPA is input to 3A), and the cursor data is stored in the non-display area by the central processing unit when the power is turned on. Stored at 3B.

The stored cursor data is once stored in the cursor data buffer 5, and then normal screen data is input to the first-in first-out part 7. When the X and Y coordinates are reached to display the cursor as shown in the screen 10, If the attribute unit 8 operates the output data of the first-in first-out unit 7 and the output data of the cursor data buffer 5 and supplies it to the DC 9, the screen 10 is displayed. It shows that the size of the cursor is standardized as 64 x 64 pixels, and the size of the cursor can be arbitrarily changed by the user.

However, in such a conventional system, since the data for the cursor is stored in the display memory, the capacity of the memory is always larger than the amount of data on the current screen, which requires a large amount of memory. Since the area data and the cursor data must be accessed simultaneously on a single memory bus, it is difficult to divide the time, which causes a defect in the efficiency of the CPU.

The present invention has been made to increase the efficiency of the central processing unit without the need for a non-display area provided that the capacity of the external DRAM is as large as the display resolution to solve such a conventional defect. It demonstrates in detail by drawing.

FIG. 2 is a block diagram of the cursor data processing system of the VG of the present invention. As shown therein, the data port enable signal EN of the SRAM 130 is decoded by decoding an address Ad supplied from the central processing unit. _DP 110 and an interface 110 for generating an index address (Add _ind ), a data port enable signal EN _Dp and an index 110 for generating an index address (Add _ind ) output from the interface 110 and A memory controller 120 storing the cursor data D _{cur in the} RAM 130 using the data port enable signal EN _DP and the index address Add _ind output from the interface 110; The data buffer 140 temporarily stores the cursor data output from the SRAM 130 in synchronization with the synchronization signal Sync output from the CALTI controller 190 and the disk according to the normal display address NDA. An address generator 150 for reading the video data D stored in the ray memory 160 and storing the video data D in the first-in first-out unit 170, and a register unit 180 storing cursor control signals and X and Y coordinate values of the cursor. And the cursor control signal and X and Y coordinate values of the cursor from the register unit 180 according to a register control signal CTL. The CD controller 190 outputs the control signal of the 200 and the synchronization signal Sync of the data buffer 140, the cursor data output from the data buffer 140, and the video data output from the first-in, first-out unit 170. The attribute unit 200 and the data output from the attribute unit 200 to perform arithmetic operation for displaying a cursor of a specified type at a desired place at the same time receiving the analog red, green, blue signal (R), And convert it to (G), (B) Be configured as a seed dieyi 210 for output to, when describing the actions and effects of the present invention such a structure in detail as follows:

The register unit 110 is composed of a control register R5, an X-coordinate register R6 of the cursor, and a Y-coordinate register R7 of the cursor. ), (R6), and (R7) record the appropriate values

Data relating to the shape of the cursor enable signal threshold cursor is recorded in the control register R5 of the cursor, data relating to the horizontal position of the cursor is recorded in the X coordinate register R6, and cursors are stored in the Y coordinate register R7. Data about the vertical position of is recorded.

The STI product (l90) receives each data outputted from the registers (R5), (R6), and (R7) and the register control signal (CTL), and the size of the screen, the synchronization signal (Sync), the position of the cursor, and the like. Generate timing related to screen

Meanwhile, an address port for writing cursor data through a central processing unit to store corresponding information for displaying a cursor having a desired shape in the internal RAM 130 is generated, and the S Store the cursor data in the RAM 130

When the address Ad and data Da related to the cursor port are supplied from the central processing unit to the interface 110, it accesses the cursor data of the SRAM 130 through the memory control unit 120 and the data is stored. Stored in buffer 140

Data stored in the data buffer 140 is supplied to one side input of the attribute unit 200 in synchronization with the synchronization signal Sync output from the CALTI controller 190, and on the other hand, the address generator 150 is normally displayed. According to the NDA, the video data Data of the display memory 160 is read and the video data Data is written to the first-in first-out unit 170. It is supplied to the other input of the attribute unit 200 under control.

The video data output from the first-in, first-out unit 170 is data for displaying a portion where normal video data of a screen is output, that is, a portion except for a cursor.

Accordingly, the attribute unit 200 simultaneously receives cursor data input from the data buffer 140 and video data input from the first-in first-out unit 170, calculates the same, and outputs the same. Through the red, green, blue signal (R), (G), (B) of the analog is converted to display as shown on the screen 220

Meanwhile, the operation of the cursor data output unit 100 will be described in more detail with reference to FIG. 3.

The address Ad input from the central processing unit is decoded and output through the decoder 111. If the input address Ad is an index port address, the index port enable signal EN _ind is activated therefrom, and the input address is input. If (Ad) is a data port address, the data port enable signal EN _dp is activated therefrom.

When the index port enable signal EN _ind is output from the decoder 111, the cursor data D _cur is latched in the latch 112, and the latched data is used as an index of the write control unit 121. This index is used as the address of the SRAM 130 when writing the cursor data to the SRAM 130.

When a data port address is input to the decoder 11 and a data port enable signal EN _dp is output therefrom, data latched to the latch 112 is written by the enable signal EN _dp . The write control unit 121 is supplied to the index address IND of the control unit 121, and the write control unit 121 generates the write enable signal EN _w from the data port enable signal EN _dp output from the decoder 11. In addition, the write address AD _w of the SRAM 130 is generated by the index address IND output from the latch 112, and the cursor data D _cur is directly generated by the data D of the SRAM 130. It is used as, through this process is to write the entire SRAM 130 by 16 bits.

After the data is written to the SRAM 130 in the central processing unit by the above process, an address Ad input from the CALTI control unit 190 is supplied to the read control unit 122. ), The address of the SRAM 130 is sequentially read by 8 bits at the portion where the hard arch cursor appears on the screen.

The read address AD _R and the read enable signal EN _R of the SRAM l30 are generated by the read controller 122 of the memory controller 120, and the address AD _R and the read enable When the signal EN _R is activated, the 8-bit data of the SRAM 130 is temporarily stored in the data buffer 140 and then the SRAM (SYN) is supplied by a synchronization signal Sync supplied from the SALTI controller 190. The 8-bit video data stored in 130 is supplied to the attribute unit 200 side, and the 8-bit data and the video data supplied from the first-in first-out unit 170 are operated.

As described in detail above, the present invention allows the hardware cursor data to be stored in the internal RAM 130, thereby eliminating the need for a non-displayed area, and having only the capacity required for the resolution of the external DRAM. By saving the cursor data in the SRAM, it is possible to increase the efficiency of the CPU by eliminating the problem of bringing the video data and the cursor data together on the same memory bus.

Claims (3)

An interface 110 which _decodes an address Ad supplied from the central processing unit to generate a data port enable signal EN _dp and an index address Add _ind of the RAM 130, and the interface 110. The memory control unit 120 for storing the cursor data D _{cur in the} SRAM 130 using the data port enable signal EN _dp and the index address Add _ind , The data buffer 140 temporarily stores the cursor data output from the RAM 130 in synchronization with the synchronization signal Sync outputted from the SRAM 130, and is stored in the display memory 160 according to the normal display address NDA. An address generator 150 for reading and storing the video data D in the first-in, first-out unit 170, the register unit 180 for storing the cursor control signal, the X and Y coordinate values of the cursor, and the register control signal CTL. According to the register section 1 The control signal of the memory controller 120, the first-in first-out unit 170, the attribute unit 200, and the synchronization signal of the data buffer 140 are supplied from the cursor control signal, the X and Y coordinate values of the cursor from 80. And a cursor of a specified type in a desired place by simultaneously receiving the cursor data output from the data buffer 140 and the video data output from the first-in-first-out unit 170. Attribute unit 200 for performing arithmetic operation for the data, and the data output from the attribute unit 200 is converted into analog red, green, blue signals (R), (G), (B) and output to VG cursor processing system characterized by consisting of the (210). The method of claim 1, wherein the interface 110 activates the index port enable signal EN _ind when the index port address is input from the CPU, and the data port enable signal EN _dp when the data port address is input. And a latch (112) for latching cursor data (D _cur ) when the index port enable signal (EN _ind ) is output from the decoder (111). Cursor Processing System. 2. The memory controller 120 of claim 1, wherein the memory controller 120 generates the write enable signal EN _w of the SRAM 130 using the data port enable signal EN _dp output from the decoder 11. The write control unit 121 generates a write address AD _w of the SRAM 130 using the index address IND output from the 112, and the address Ad input from the cialty control unit 190 is used. And a read control unit 122 for generating a read address AD _{R such} that the address of the SRAM 130 is sequentially read by a predetermined bit in a portion where a hardware cursor appears on the screen. .