JPS62271291A - Memory device - Google Patents

Abstract

PURPOSE:To attain a successive serial input by providing a pair of registers, performing the serial input and output in one of the pair, transferring data to a memory cell array in the other of the pair and preparing the next serial input and output. CONSTITUTION:For instance, when serially outputting, a display controller 51 initially sets a selection signal LRS to '0' to select an (a) side, reads and transfers data B to the data register 31a from the memory cell array 1a and in this case, the start address of the data B is not designated. Then, the selection signal LRS is set to '1' to select a (b) side and the data A is read and transferred to the data register 31b from the memory cell array 1b. Under this state, if the display controller 51 sets a serial enable signal SEN to '1', a serial output mode signal SOM is outputted from an AND gate, it is supplied to the enable ends of data buffers 67a, 67b and as a result of this, the outputs of the data registers 31a, 31b are supplied to serial data gates 66a, 66b.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a memory device suitable for use as a frame buffer memory of an image display device, and particularly relates to a so-called dual port memory. It relates to improvements in memory devices called.

U Prior Art] In the field of image display, image data such as figures and characters drawn on a frame buffer memory according to instructions from a CPU is sequentially read out by a display controller.
Devices that display images on Rusk scan type display devices are widely used.

With this type of display device, accesses from the CPU side and accesses from the display controller side compete with each other. This f
For this reason, it is possible to allow access from the CPU only during blanking periods of horizontal scanning and vertical scanning, and to divide the memory access timing into X'J) time slots and assign specific time slots to the display controller. The remaining time slots are allocated to the CPU.

However, access from the CPU side is severely restricted by any of the above methods.

Therefore, in recent years, dual port memories that can be accessed from the CPU side and from the display controller side in parallel have come into widespread use.

This dual port memory has a random port that can be written and read like normal R, AM, and
It also has a serial port that allows serial input/output of data, a random port for access from the C and PU, and a serial port for access from the display controller (Nikkei Electronics, 1985 May 20, No. 369, I
) p195-219).

FIG. 6 is a block diagram showing an example of this type of dual port memory. In the figure, memory cell arrays 1 to 4 each have 256 rows and 256 columns, and data in memory cell arrays 1 to 4 can be accessed in two modes: random access and serial access.

First, in normal random access mode, the addresses of memory cell arrays 1 to 4 are stored in the address buffer 5.
The row address and column address sequentially supplied from the address line are decoded by the row decoder 6 and column decoders 11-14. Then, the 4-bit data read from the same address in each memory cell array 1-4 is transferred to the input/output cover sofas 21-24 via the sense amplifier/I10 gates 15-18, and is output to the outside as output data 100-I03. Output to.

On the other hand, write data 10 to memory cell array [~4]
0 to 103 are sent from the input/output buffers 21 to 24 to the sense amplifier/I10 gates 15 to 18 in units of 4 pins, and written to the same address in the memory cell arrays 1 to 4. In this way, the above components 11-18 and 21-
24, it is possible to simultaneously write and read data for 11 times to any address of 4 memory cell arrays (1 to . It has become.

Next, the serial access mode will be explained. First, data registers 31-34 each having a length of 256 hints are connected to each memory cell array 1-4, so that data can be transferred to and from the memory cell arrays 1-4 row by row. First, the data written into the memory cell arrays 1 to 4 is transferred row by row to the data registers 31 to 34 (read data transfer), and the data is serially input to the data registers 31 to 34. is transferred (write data transfer) and written to memory cell arrays 1 to 4 row by row.

In addition, data registers 31 to 311 contain pointers 35 to 311.
38 is attached, and one of the 256 bits of data registers 31 to 34 is input/output (focus address).
Specify. The pointers 35 to 38 use the clear address supplied from the address buffer 5 as an initial value, and the initialized values are softened one bit at a time by the serial control clock SC, and then set to the hit addresses of the data registers 31 to 34. Output as 25
This is a 6-bit knot register.

In the case of serial output, data registers 31 to
The read data transferred to SDO 34 is sequentially sent to the serial input/output buffers 41 to 44 starting from the bit address indicated by the initial value, and the serial output data SDO to
Output as SD3. On the other hand, in the case of serial input, serial input data SDO to SD3 are sequentially serially input to the bit addresses of data registers 31 to 34 indicated by pointers 35 to 38 via serial input/output buffers 41 to 44, and serial input When the data registers 31 to 34 are completed, the write data is transferred all at once to the memory cell arrays 1 to 4. In this way, serial input/output can be performed from any bit address of the row data.

In addition, in FIG. 6, 45 is a row address strobe signal RA.
46 is a refresh address counter that sequentially outputs fresh addresses; 47 is a write clock generator that outputs a clock when writing data; 418 is a memory cell array 1 to
4 and data registers 3 (-34).

FIG. 7 is a timing chart showing the operation of the conventional dual port memory described above.

First, when performing normal random access, at the rising edge of the row address strobe signal RAS, the output enable signal ○E is set to "0" to indicate random access ((f) in the same figure), and the memory cell array Indicate row addresses 1 to 4 ((C) in the same figure). Further, at the rising edge of the column address strobe signal CAS, a column address is designated ((C) in the same figure). As a result, memory cell arrays I to 4 and data registers 31 to 34
No data transfer is performed between the two, and normal reading or writing is performed. That is, the signal RAS.

By CAS, the row address is sent to the row decoder 6 and the column address is sent to the column decoders 11-14, respectively, and for the corresponding address of the memory cell arrays 1-4,
Reading or writing of 4-bit data too-103 is executed (see (e) in the same figure).

Next, when the signal RAS rises, output enable signal OE is set to "1" (data transfer), write enable signal WE is set to "0" (read) to instruct read data transfer, and a row address is specified. In the data transfer cycle, as the output enable signal OE falls, part of the row data specified by the row address is transferred from the memory cell arrays 1 to 4 to the data registers 31 to 3 =1. Note that the column address at this time is used to initialize the serial output custard addresses in the pointers 35-38.

The data thus transferred to the data registers 31 to 34 are serially output while the serial enable signal SE is "1", as shown in (g) to (i) of the figure. That is, the bit addresses of pointers 35 to 38 are updated by 1 by the serial control clock SC, and the data register 3 specified by this bit address is updated.
Data within 1 to 34 or serial input/output buffer 41 to
44, the serial data SDO to SD3 are output in units of 4 bits. Incidentally, serial input is performed in substantially the same manner, and the serial input data input to data registers 31-34 is written to memory cell arrays 1-4 by write data transfer.

E Problems to be Solved by the Invention] By the way, the above-mentioned conventional dual port memory had the following problems.

(1) As shown in FIGS. 7(f) and (h), when serial output is to be avoided continuously, it is necessary to synchronize the output enable signal OE and the serial control clock SC. That is, the times tSDD and tS in the figure
Dit must be set to a value greater than or equal to fOns. For this reason, the timing had to be adjusted, which caused restrictions and difficulties in circuit design.

(2) It is not possible to rewrite only part of the row data of memory cell arrays 1 to 1↓ by serial input.

In order to do this, first read data is transferred to the data registers 31 to 34 for the row data, serially input only the part to be rewritten to the data registers 31 to 34 to rewrite it, and then read data to the data registers 31 to 34. 34 to the original row of memory cell arrays 1 to 4 by write data transfer, but in conventional dual port memory, the data registers 31 to 34 heritage data is transferred from memory cell arrays 1 to t. After 1 step, only serial output is possible and only serial input is possible. Therefore, after transferring data from memory cell arrays 1 to 1 to data registers 31 to 3.1, it is impossible to rewrite part of data registers 31 to 34 manually. ), Ki, (branch),
Partial rewriting of line data D: It will not come back.

(3) Serial manual labor can only be performed continuously.

That is, serial input is made to data registers 31 to 37t, and after one write, part of the written data is transferred to memory cell arrays 1 to 4, so serial input must be stopped during this time, and serial input must be continuously input. I couldn't do it.

The present invention was made against this background, and an object of the present invention is to provide a memory device having the following functions (1) to (4).

(1) There is no need to synchronize the output enable signal that instructs data transfer with the serial control clock that advances serial input/output.

(2) Part of the row data can be kept as is, and only the remaining parts can be rewritten by serial input.

(3) Continuous serial input is possible.

(4) Serial input/output of row data or a serial runout signal will be output to the solution that ends [Means for solving the problem:- In order to solve the above problem, this invention provides A pair of memory cell arrays that separately transmit and receive data in the first half column and the second half N- column of any row of the memory cell array, and alternately input and output the data serially. a data register, an initializable pointer that indicates a serial input/output position in the data register, and data transfer between the data register that is not performing serial input/output among the pair of data registers and the memory cell array. The gist is to provide means to permit

Further, when the serial input/output position indicated by the pointer switches from one of the pair of data registers to the other, a serial runout signal is output from the pointer.

[Operation] According to the above configuration, one of the paired data registers is 7
While the real I/O is being performed, the other is idle. It is possible to transfer data between the data register and the memory cell array in this idle state, so if you transfer data to the serial input/output end surface and end the serial input/output, serial input/output can be performed. It can be done continuously. In other words, if one side of the pair transfers data while the other is doing serial input/output, and one side transfers data while the other is doing serial input/output. can be executed.

However, at this time, there is no need to synchronize serial input/output and data transfer.

In this case, switching of data registers for performing serial input/output is automatically performed by a pointer, and the trace of this switching is transmitted to the display controller side by the serial runout signal. This allows the display controller to execute data transfer between the data register on the IJ side performing serial input/output, that is, the data register on the idle side, and the memory cell array.

When using serial manual input, the data of 7140 rows of memory cells is transferred to the register in advance, and after rewriting part of this data 7) using serial manual input, the data register is transferred to the data register. By returning the data to the original row of the memory cell array, data that cannot be rewritten manually can be saved.

In other words, part of the row data can be rewritten.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

Overall Configuration of Image Display Apparatus FIG. 1 is a block diagram showing the configuration of an image display apparatus to which a memory device according to an embodiment of the present invention is applied. In the figure, 50 is a CPU.

The CPU 50 supplies commands and data necessary for drawing and display to the display controller 51, while receiving responses to data and commands in the memory device 52 from the display controller 5I.

The display controller 51 performs drawing on the memory device 52, and also outputs a horizontal open IgI signal, a vertical and parallel 1tll signal,
A serial controller τ generates a timing signal such as a clock, sequentially reads display data from the memory device 52, and supplies the read data to a D/A converter 53. The DAC 53 converts the supplied digital signal into an analog signal, and displays the C1"tT display device 54.
to be displayed. Note that the display controller 51 and the memory device 52 are connected by control lines, address lines, and data lines as shown in the figure, which will be described later.

Configuration of this Embodiment FIG. 2 is a block diagram showing the serial configuration of the memory device 52. As shown in FIG. In the figure, Ia.

Each Ib is a memory cell array of 256 rows by 128 columns, and these correspond to the memory cell array l in FIG. In this example, 1.1 pairs of memory cell arrays (Ia, Ib) - (4a, 4.b)
are provided, but since they have similar configurations, only the memory cell arrays la and 'r b will be described below. Also, the memory cell array la.

The column address of 1b is i, j (i-0~I 27 , j=
l 28-255), and a suffix i is used after the code to indicate the component corresponding to this column address.

It is indicated by adding j.

In FIG. 2, 31a and 32b are data registers each consisting of 128 D flip-flops 31a-i and 31b-j, which correspond to the data register 31 in FIG. These data registers 31a, 31
b and each data input end of memory cell array I a, I
Data transfer gates 61a, 61b and data buffers 762a, 62b are interposed between data output terminals Q of data registers 31a, 31b and memory cell array la.

Data buffers 63a, 63b and the data transfer gates 61a, 61b are interposed between the memory cell arrays la and 1b (7), and data is exchanged with each row of the memory cell arrays la and 1b (7).

Here, the data transfer gates 61a and 61b are each +28
Consisting of 9 gate elements 61a-i and 61b-j,
The data buffers 62a to 63b each have 128 3
It is composed of state buffers 62a-i to 63b-j.

Each data input end of the data registers 31a, 31b is also connected to the serial input/output cover couch 41 shown in FIG. 6 through data buffers 65a, 65b and serial data gates 66a, 66b. Similarly, each data output terminal Q of the data registers 31a, 31b is connected to a data buffer 67a, 67b, a serial data gate 66a,
66b, it is connected to the serial input/output cover sofa 41.

As a result, data buffers y 65a, 65b, 67a,
67b is turned on, and the gate element (36a-i+6
By turning on 6b-j, the data register 31
Serial data SDO can be exchanged between a-i, 31b-j and the serial input/output cover sofa 41.

The circuit configuration for controlling the transmission and reception of these serial data is as follows. First, a pair of pointers 35a specifying hint addresses i and j of data registers 31a and 31b.
, 35b is installed. 22'L corresponds to the pointer 35 in FIG. 6, so each of them is composed of 128 D flip-flops and serves as an initial setting initializer. That is, the output of the address decoder 70 which converts 8-bit address data ADO~7 and outputs a 256-bit bit address is sent to the pointer 31 via AND gates 7I a-i and 7 l b-j.
Each element of a, 31b (D flip-flop) 35 a
-i, 35 b-'' is supplied to the cent end S, 2
Any one of the 56 D flip-flops 35a
-i, i or 35b-j is cented to "1", and this "1"
The bit address signal (bit address signal) is supplied to the clock end and is set to be knotted one hit higher by the serial control clock SC.

Then, the outputs of the D flip-flops 35a-127 and 35b-255, which correspond to the most significant bit during serial input/output, are supplied to the input terminal of the OR gate 72.
The serial runout signal SRO, which instructs the end of serial input/output, should be output.

On the other hand, the signals output from the respective output terminals Q of the D flipflops 35-i and 35-j constituting the pointers 35a and 35b are sent to the control terminals of the respective gate elements 66a-i and 66b-j of the serial data gates 66a and 66b. It is also supplied to the clock ends of each element 31a-i, 35b-j of the data registers 31a, 31b via AND gates 73a-i, 73b-j and OR gates 74a-i, 74b-j. There is. This results in a bit address (
The data register 31a-i (or 35b-D) outputting the “I” signal)
Alternatively, serial data SDO can be exchanged between 31b-D and the serial input/output buffer 41.

That is, during serial output, the data register 31a
(or 31b) bit data is D flip 70-
) from Q output terminal of gate 31a-i (or 31b-j) to data buffer y67a-i (or 67b-D) to serial data gate 66a-i (or 66b-j) to serial input/output buffer 4I, On the other hand, during serial input, the human data in the serial input/output buffer 41 is transferred to the serial input/output buffer 41 - serial data gate 66a-i (or 66b - D - data buffer y65a-i (or 65
b-D=D flip-flop Zlp 31a-i (or 3T
The data register 31 is connected to the data input end path of o-D.
a (or 31b). Then, this bit data is transferred from pointer 35a-i (or 35b-D to AND gate 73a-i (or 73b-D) to OR gate 74a-i (or 74b-D) to data register 31a-i (or 31b-D). -j) is taken into the data registers 31a-i (or 31b-D) by the bit address signal supplied to the clock end.

Next, the relationship between control signals of the memory device 52 will be explained. FIG. 3 is a block diagram showing the configuration of a circuit that generates main control signals.

In FIG. 3, output enable signal OE is provided to a first input of AND gate 81. In FIG.

The second input terminal of this AND gate 81 is connected to an inverter 8.
2, an inverted signal of the column address strobe signal C/'S is supplied, and a data transfer enable signal DTE output from the AND gate 81 is supplied to the data input end of the latch circuit 83. A row address strobe signal RAS is supplied to the latch end of the latch circuit 83, and the signal DTE is latched when it rises to "L".

(2) The data transfer control signal DTC outputted from the child circuit 83 is supplied to the AND gate 84, and is ANDed with the two-legged signal CAS and the inverted signal of the serial enable signal SEH supplied from the inverter 84a. This logical product is supplied as the signal IDTC from the AND gate 84 to the clock terminal of the D flip-flop 85. A write enable signal WE is applied to the data input end of this D flip-flop 85, so that it is taken in by the signal +DTC.

The "l" signal taken into the D flip-flop 85 is
)11 is a signal that instructs the input of the inverter 86.
The signal is inverted and supplied to the second input terminal of the AND gate 87, and is also directly supplied to the second input terminal of the AND gate 88. A serial enable signal SEN is supplied to each first input terminal of the AND gates 87 and 88, a serial output mode signal SOM is supplied from the AND gate 87, and a serial input mode signal SI is supplied from the AND gate 88.
M is output respectively.

Next, at the data input end of the D flip-flop 89,
When the selection signal LR8 is supplied and the row address strobe signal RAS supplied to the clock edge rises,
The signal is taken into the D flip-flop 89. Then, the output of the D flip-flop 89 is the transfer gate selection signal TGS.
becomes. Note that the selection signals ■ and RS are signals supplied from the display controller 5I to the memory device 52 in order to select one side of the memory cell arrays la, Ib, etc. When the value is "1" on the a side, the b side is selected.

Returning to FIG. 2 again, the transfer gate selection signal TGS is directly supplied to the first input terminal of OR gate 90d, and is inverted and supplied to the first input terminal of OR gate 90c. Further, the output of the OR gate 90c is supplied to the first input terminal of the AND gate 90a, and the output of the OR gate 90d is supplied to the first input terminal of the AND gate 90b. Further, a data transfer control signal DTC is supplied to each second input terminal of these AND gates 90a, 90b, and each output of AND gates 90a, 90b is supplied to each control terminal of data transfer gates 61a, 61b, respectively. Supplied. As a result, the transfer gate selection signal TGS becomes "1",
And when the data transfer control signal DTC is "l", a "l" signal is output from the AND gate 90b,
Each gate element 61b-j of data transfer gate 61b is turned on, and memory cell array tb and data register 31
It becomes possible to transfer data between the On the other hand, when the transfer gate selection signal TGS is "0" and the data transfer control signal DTC is "1", a "1" signal is output from the AND gate 90a, and data is transferred between the memory cell array la and the data register 31a. becomes possible.

In addition, a full serial buffer signal F'SB is supplied to each input terminal of the OR gates 90c and 90d, and when this becomes "L", the OR gates 90c and 90d switch to "L" regardless of the value of the transfer gate selection signal TCS. ” signal is output. Therefore, the data transfer control signal DTC
When becomes "1", the AND gates 90a and 90b simultaneously output "1" signals, and the data transfer gate 61a
and 61b are opened, allowing data transfer between memory cell arrays la and 1b and data registers 31a and 31b.

Next, 91 is a D flip-flop for switching between read data transfer and write data transfer. An inverted signal of the write enable signal WE is supplied to the data input end of this D flip-flop 91, and this is taken in at the rising edge of the row address strobe signal RAS applied to the clock end. Note that this row address strobe signal RAS is valid only when the data transfer enable signal DTE supplied to the enable terminal E is "1". As a result, when a data transfer command is issued, if the write enable signal WE is "0", the Q output terminal of the D flip-flop 91 becomes "1", and the read data transfer control signal RDTC is output.On the other hand, the write enable output When WE is “1”, the Q output terminal force is
Then, the write data transfer control signal WDTC is output. Then, the data buffers y62a and 6 are instructed to output the read data transfer control signal RDTC.
2b is enabled to enable read data transfer, and when a write data transfer control signal WDTC is output, data buffers 63a and 63b are enabled to enable write data transfer.

Next, an AND gate 92, a delay 93, AND gates 94a, 94b, and an OR gate 95a.

The gate 95b, in combination with the OR gates 74a and 74b, controls switching between the a side and the b side of read data transfer.

First, the AND gate 92 receives a read data transfer control signal RDTC and a column address strobe signal CA.
S is input, and the logical product of these is supplied via a delay 93 to the first input terminals of AND gates 94a and 94b. In addition, each of the second at gates 94a and 94b
Each output of OR gates 95a and 95b is supplied to the input end.

Since the OR gates 95a and 95b are for switching between the a side and the b side, the data register selection signal DR8 is "0".
”, “1” is output from the OR gate 95a,
When the surface selection signal DRS is “I”, the OR gate 95
“1” is output from b. Furthermore, when the full serial buffer signal FSB is "1", a "1" signal is output from both OR gates 95a and 95b, regardless of the signal DR9.

As a result, when the signal CAS rises during read data transfer and the "l" signal is output from the delay 93 after a certain delay time, the AND gates 9 and 1a are opened by the outputs of the OR gates 953 and 95b.

An "l" signal is output from 94b, which is sent to data register 31a via OR gates 7rla and 74b.

31b, and read data transfer is executed.

Next, the AND gate 96 outputs the serial enable signal S
This is a logical product of EN, serial input mode signal SIM, and serial control clock signal SC.
In the serial manual mode, AND gates 73a and 73b are opened every time the serial control clock SC is applied.

As a result, data registers 31a and 31a corresponding to the bit addresses specified by pointers 35a and 35b,
Serial manual data is sequentially taken into elements 31a-i (or 31b-D) of 31b.

That is, the "I" signal output from the AND gate 96 is supplied to the ant gate 73a-i (or 73b-D) together with the "I" output of the pointer 35a-i (or 35b-j) that specifies the focus address. , the “1” signal output from the AND gate 73a-i (or 73b-j) is output to the OR gate 74a-i (or 74b-j).
Data register 31a-1 (or 31b
-D is supplied to the clock end, and serial manual data is taken in.

The AND gate 97 performs the logical product of the signal [DTC and a signal obtained by delaying the signal [DTC] with the delay 98 . As explained in FIG. 3, the surface signal IDTC is the serial input/output mode signal SIM.

This is a signal for loading the SOM into the D flip-flop 85, and is output at the beginning of serial data input/output. This signal IDTC causes AND gate 9
When the “l” signal is output from 7, the AND gate 7.1
a and 71b open all at once, and of the pointers 35a and 35b, only one pointer 35a-1 or 35b-j to which the "I" signal is supplied from the address decoder 70 becomes "1", and the serial input/output starts. Address is initialized.

Finally, 99 is a latch circuit that latches 8-bit address data ADO-7. This latch circuit 99 is
Address data ADO~7 is taken in by the rise of column address strobe signal CAS and output as start address SAO~S, A7. These outputs SAO to SA7 are directly supplied to the input terminal of the address decoder 70 and inverters 70-0 to 70-70.
After being inverted by -7, it is supplied to the other input terminal of the address decoder 70. Note that the signal CAS is r only when the data transfer control signal DTC is “L”.
It becomes effective.

The above configuration can be summarized as follows.

(2) By switching the transfer gate signal TGS between "0" and "1", only one of the data transfer gates 61a or 61b can be turned on. This allows data transfer to be performed separately on the a side and the b side. Further, by setting the full serial buffer signal FSB to "1", data can be transferred in parallel on the a side and the b side.

(2) When transferring REIT data, enable the data buffers 62a and 62b using the REET data transfer control signal flDTc. On the other hand, when transferring write data, use the write data transfer control (No. WD).
TC enables data buffers 763a and 63b.

■When using serial manual power, serial manual power mode signal S
IM enables data buffers 65a and 65b. On the other hand, during serial output, the data buffer 67a is controlled by the serial output mode signal SOM.
and 67b.

■Specification of a bit address during serial input/output is performed using the pointer 35a or 35b, and the data register 31 corresponding to the specified address i, j is specified.
Serial input/output is performed to a-i and 3lb-j. A start address is initially set in the pointer 35a or 35b by a signal from the address decoder 70.

(2) When pointers 35a and 35b point to the highest hint address, OR gate 72 outputs serial runout signal SRO. Thereby, the display controller 51 can grasp whether serial input/output has been switched from the a side to the b side, or from the b side to the a side.

Operation of this Embodiment Next, with reference to FIGS. 1 to 4, the operations of the serial output mode, serial manual mode, and heavy-speed copy mode, which are the gist of this embodiment, will be sequentially explained. ,
Describe data transfer. Incidentally, input/output of the random access system can be performed in the same manner as in the conventional case, so a description thereof will be omitted.

In addition, the following operation will be explained only for the memory cell arrays 1a and 1b and the data registers 31a and 31b.
Exactly the same operation is performed for other memory cell arrays 2a-4a, 2b-4b and data registers 32a-34a, 32b-34b, and input/output is performed in units of 4 bits.

Now, the above-mentioned data transfer means that the memory cell array la (1b) and the data register 31a
(31b), data transfer from the memory cell array 1 side to the data register 31 side is called read data transfer, and data transfer in the opposite direction is called write data transfer. First, REIT data transfer will be explained.

(1) Read data transfer The operation of read data transfer is as follows.

■The display controller 51 is a
Switch the selection signal LRS and data register selection signal DR5 to either 0"/"l" depending on whether the side is a side or /b side. Also, when transferring data during surveying on the a side or b side, the full serial buffer signal Output PSB.

The selection signal LR5 is applied to the D flip-flop 8 in FIG.
9, and the selection signal DRS is supplied to the data input end of the second
It is supplied to the OR gates 95a and 95b in the figure. These signals Ll” (S, DRS are both “0” when a
When the side is "[", side b is selected.

On the other hand, when the full serial buffer signal F'SB is output, these are OR gates 90c, 90d, and 95a.

95b, and data can be transferred on both the a side and the b side.

■Next, the display controller 51 sets the output enable signal OE to "l" (data transfer) and the write enable signal W.
E is set to "0" (read), the row address to be transferred is placed on the address bus 0 to A7, and the row address strobe signal RAS is raised to "1" (time jl in FIG. 4). As a result, in the memory device 52, read data transfer (signal RDTC is "1") and the row address to which the read data is to be transferred are set.

In other words, the data transfer enable signal DTE (in this case, the "l" signal), which is the AND signal of the output enable signal OE and the inverted signal of the column address strobe signal CA S ) is output, and this signal DTE is supplied to the input terminal of the latch circuit 83 and the enable terminal of the D flip-flop 91. In this state, when the signal flAs rises at time jl in FIG. 4, the signal DTE is latched by the Lasoji circuit 83 and output as the data transfer control signal DTC. , "1") is taken into the D flip-flop 91, and the D flip-flop 2! A read data transfer control signal RDTC is output from the Q output terminal of the data buffer 762a, 6
2b is enabled. Further, the signal DTC is supplied to AND gates 90a and 90b. Furthermore, Fig. 4 (c
), row addresses ADO~7 are memory devices @5.
Incorporated into 2.

This point is the same as before.

At the above time t1, the selection signal LRS is also taken into eight D flip-flops, and the transfer gate selection signal TGS is sent to either O''/''I''.
GS opens data transfer gates 61a and 61b on the data transfer side (a side or b side), and opens AND gates 90a and 90b via OR gates 90c and 90d.
is supplied to the data transfer gate 61a on the a side when it is “0”, and the data transfer gate 61a on the b side when it is “I”.
1b is selected.

On the other hand, the display controller 51 uses the full serial buffer F.
When SB is output, data transfer gates 61a, 61
If b is turned on at the same time :), data transfer is possible on both sides a and b.

(2) Next, at time L2 in FIG. 4, the display controller 51 selects serial input/output and sets its start address.

That is, the display controller 51 puts the start address during serial input/output on the address buses AO to A7, and also puts the start address on the data register 31a.

The write enable signal WE, which indicates the serial input/output direction of 31b, is set to either "0" or "l" (serial output/real input), and the column address strobe signal CAS is set to "1" at time t2 in FIG. will be launched. As a result, in the memory device 52, the direction of serial input/output (serial input mode signal SIM or serial output mode signal SOM) and the start address for serial input/output are set.

More specifically, at time t2, the display controller 51
When the column address strobe signal CAS is raised,
The start address ADO~7 is latched in the latch circuit 99, and is decoded by the address decoder 70. Then, the address decoder 70 outputs “
The l'' signal (which is only one of 256) is provided to the ant gates 7Ia-i or 71b-j.

At the same time, at time t2, the signal rDTc is output from the AND gate 84 in FIG. or 71b
−j is opened. As a result, the start address is initialized to the pointer 35a-i or 35b-j.

Also at time L2, the write enable signal WE is taken into the D flip-flop 85 in FIG. 3 by the signal IDTC, and selection of serial output and serial input is performed. That is, the write enable signal WE
When is "1", the Q output of the D flip-flop 85 becomes "1", and preparations are made for outputting the serial manual control signal SIM from the AND gate 88.

Further, when the write enable signal WE is "0", the Ql output of the D flip-flop 85 becomes "0", and the serial output control signal s is output from the AND gate 87.

The end where M is output is performed.

■When read data transfer is completed in this way, a "1" signal is output from the delay 93 after a certain delay time from the rise time t2 of the signal CAS.
AND gates 94a and 94b are opened, and OR gate 74 is opened.
A “1” signal is sent to the clock ends of the data registers 31a and 31b through the memory cell arrays I and 74b.
The row data of a, 1 b is stored in the data registers 31a, 3
1b, and read data transfer is executed.

(2) Write data transfer Write data transfer? The differences from bipedal read data transfer are as follows.

■The display controller 51 receives the write enable signal WE.
is “I” (write), and output enable signal OE is “1”.
(data transfer), and the row address strobe signal RAS is raised at time L1 in FIG.

■As a result, the write data transfer control signal W D is transmitted from the Q output terminal of the D flip-flop 91 in FIG.
TC is output to the data buffer 63a.

63b is enabled. As a result, the output data of the data registers 31a and 31b is transferred to the data transfer gate 61.
a, 61b, memory cell arrays l a, l
Part of the write data is transferred to row b.

Note that at this time, the selection of the a side, the b side, or both of these is performed using the selection signals L r (S, D RS, T G S and the full serial buffer signal FSH), as in the case of read data transfer. This is done by

The above is the data transfer operation. Next, serial output, serial manual input, and high-speed copying will be explained with reference to FIG.

(1) Sorial output mode As shown in FIG. 5(a), serial output starts from data A on memory cell array Ib to data D on memory cell array Ib in the order of A→B-4C→D. This will be explained using an example. Note that data A starts from the start point SP A, and data D C')t'
The display controller 51 grasps the % completed address by counting the serial control clock SC.

(1) The Q-ready display controller 51 first sets the selection signal LRS to “0°”.
Then, side a is selected and data B is read and transferred from the memory cell array la to the data register 31a.

In this case, the start address of data B is not specified. That is, all pointers 35a are set to "0".

Next, the selection signal LR8 is set to "L" to select the b side, and read data A is transferred from the memory cell array Ib to the data register 31b. In this case, the start address of data A is address SP A. This start address is taken into the launch circuit 99 by the rise of the column address strobe signal CAS, and is set in the only pointer 35b-j via the decoder 70. At the same time, this signal CAS causes the write enable signal w E (in the present case of serial output to be “0”).
) is read into the D flip-flop block 85, and "O" is output from the Q output terminal of the 07 flip-flop knob 85.

(2) Start of serial output of data A In this state, when the display controller 51 sets the serial enable signal SEN to "1', the AND gate 87 outputs the serial output mode signal SOM, which is the enable terminal of the data buffers 67a and 67b. As a result, the outputs of the data registers 31a and 31b are supplied to the serial data gates 66a and 66b.Here, the 7 real data gates 66a and 66b are connected to the pointer 3.
Only one gate bit-addressed by 5a, 35b is turned on. In this case, from pointer 35b-j corresponding to start address SPA to data 1
``signal is output, the serial data gates 66b-j are turned on, and the output of the data registers 31b-j is supplied to the serial input/output cover couch 41 and output.

Here, when the display controller 51 outputs the serial control clock SC, this is output to the pointers 35a and 3.
5b is supplied to the Kurozoku end of pointer 35b-j.
1° signal is one higher level/\Soft.

As a result, the serial data gate 66b-j+1 is turned on, and the output of the data register 31b-j+1 is sent to the serial input/output buffer 4I and output. Similarly, the hint address of the pointer 35b is softened bit by bit by the clock SC, and the data register 31b is
The data A set in is sequentially read out and serially output from the serial input/output cover sofa 611.

When the serial output of the data A is completed, a "1" signal is output from the most significant pointer 35b-255, and is supplied to the least significant pointer 35a-0 and the OR gate 72. As a result, the lowest pointer: 35a-0 is “
1'' to start serial output of data B, a serial runout signal SRO is output from the OR gate 72 and sent to the display controller 51.

(3) Serial output of data B and transfer of data C The display controller 51 receives the serial runout signal SRO and combines the read data transfer of data C into 1b.

That is, while outputting the row address of data C,
Set the output enable signal OE to "1" (data transfer), set the write enable signal WE to "0" (read), raise the lobe signal RAs to the row address, and set the row address when transferring read data of data C. .

At this time, the selection signals LRS, DflS and +E transmission gate selection signal TGS are kept at "L", and the OR gate 90d
, "l" is outputted from the AND gate 90b intermittently,
Data transfer gate 61b is opened.

Also, a "1" signal is output from the OR gate 95b and supplied to the AND gate 94b. Further, a read data transfer control signal RDTC is output from the Q output end of the D flexible flop 91, and the data buffers 62a, 62
b is enabled.

In this state, when the display controller 551 raises the column address strobe signal CAS, a "1" signal is output from the anchor 9.1b after a delay time due to the delay 93, and the row data C of the memory cell array 1b is output. The data is taken into the data register 31b.

In this way, while data B is serially output from data register 31a, read data transfer of data C is performed to data register 31b.

(4) Serial output of data C and transfer of data D When the serial output of data B from the data register 31a is completed, the highest D flip-flop 35a of the pointer 35a
-127 outputs a "de" signal, which connects the lowest D flip-flop 35b-128 on the b side and the OR gate 72.
and will be supplied. As a result, the serial output of the data C stored in the data register 31b is started, and the serial runout signal SRO is output from the OR gate 72.
is output and supplied to the display controller 5I.

"The display controller 51 switches the selection signal LflS to "0" by the two-legged real runout signal SRO,
Data D is read and transferred from memory cell array Ia to data register 31a. This ret data transfer is performed in the same manner as the data C transfer.

(5) Stopping Similarly to the above 3, when all data D has been sent out, the display controller 51 sets the serial enable signal SEN to "0". As a result, Ant Gate 8
7 is closed and the serial output mote signal SOM becomes “0”.
”, the data buffers 67a and 67b close, and serial output stops.

Thus, in this embodiment, one data register 31a
(or 3fb), while the other data register 31b (or 31a) performs read data transfer, it is necessary to synchronize the output enable signal OE and the serial control clock SC. It can also be used for continuous serial output.

([) Serial input mode As shown in FIG. 5(b), starting from data A on memory cell array la, memory cell array! In this case, each data in the memory cell arrays Ia, lb is once stored in the data renostar 31a, After the read data is transferred to 31b, it is manually rewritten in serial, and the write data is transferred back to the original row of the memory cell arrays la and lbO. The reason for doing this is to save the parts that cannot be written well when part of the row data is rewritten.

Below, in order to distinguish the data after rewriting from the data after rewriting, the data before rewriting is
, and the data is expressed as Aa, Ba, Ca.

In addition, data A is from the start address SPA,
The data CD end address is determined by the display controller 51 by counting 7 real control clocks sc. In addition, three pairs of memory cell arrays (2a, 2b) ~
Exactly the same operation is performed in (・la, 4.b), and each data is ・serial human input for each pit.
, 5 rero.

(1) Kuwa'J: Book/jjikono[・[;-ra51ba, masu, selection signal,
Set feS to "I" and read data Ba from memory cell array lb to data register 31b. Next, the selection signal LR8 is set to "0" and read data Aa is transferred from the memory cell array 1a to the data register 31a. Here, the start address of data A1 is address SPA, which is preset in the corresponding D flip-flop 35a-i in pointer 35a by clear address strobe signal CAS.

When outputting the above signals C and A S, the display controller 5
1, set the write enable signal WE to “1” (serial manual input). As a result, the signal CAS rises and the D flip-flop 85 is set to "1".

Then, preparations are made for outputting the serial manual mode signal S[':vi from the AND gate 88.

(2) Start of serial manual power After the above-mentioned 9 bits are completed, the display controller 5I sets the serial enable signal SEN to "1" and outputs the serial manual mode signal S! from the ANDKATE 88. M ＼
It is output and the data bar I7A 653.65b is enabled. As a result, serial data gates 66a, 6
6b, and a data register 31a.

It is connected to 31b's human power pump. Here, serial data gates 66a and 66b are pointers 35a.

Only one gate will be on, addressed by the bit address signal from 35b.

In this case, it corresponds to the start address SPA of data A 4
A "1" signal is output from the pointers 35a-i,
Serial data gate 66a-i is turned on, and serial manual data from serial input/output cover sofa 41 is supplied to data register 31a-i.

Here, when the display controller 51 outputs the serial control clock SC, it is supplied to the AND gates 73a and 73b via the AND gate 96, and the pointer 3
From the AND gate 73a-i specified in 5a-i, “
I" signal is output. This "1" signal is supplied to the clock end of the data register 31a-i through the OR gate 74a-i, and serial manual data is taken into the data register 31a-i. Also, the serial control clock SC is supplied to the clock ends of pointers 35a, 35b, and the "l" outputs of pointers 35a-i are sequentially shifted to the second position. As a result, data A that has been manually input to the serial input/output cover sofa 41 is sequentially fetched into the data register 31a starting from the start address SPA.

In this way, the data l\a in the data register 31a is sequentially rewritten starting from the start address SPA, and the data A
When the serial input is finished, at this point pointer 35
from the topmost D flip-flop 35a-127 of a
" signal is output, and this signal is supplied to the lowest D flip-flop 35b-128 of the pointer 35b and the OR gate 72. As a result, when the serial input of data B starts, the serial input from the OR gate 72 A runout signal SRO is sent to the display controller 51.

(3) Write data transfer of data A and read data transfer of data C] (during data B real input) The display controller 51 that received the serial runout signal SRO transfers the serially inputted data 8 to the data register 31a.
Write data is transferred from the memory cell array 13 to the memory cell array 13.

That is, when the row address strobe signal RAS is raised with the write enable signal WE and the output enable signal OE set to "L", the D flip-flop 91 is set to "0", and the output from the Q output terminal is set to "0". A write data transfer control signal W D TC is output, and the data buffers 63a and 63b are opened.

Also, at this time, the selection signal RS is kept at "0")
Therefore, the transfer gate selection signal TGS and others are "0", and at the time when the data transfer control signal DTC is output,
A “1” signal is output from the AND gate 90a, the data transfer gates 61a are opened all at once, and the data register 31
The contents of a (i.e. data A) or memory cell array l
Write data is transferred to a.

Next, the controller 51 transfers read data from the data register Ca from the memory cell array la to the data register 31a in preparation for the next serial output.

During this time, data B was input serially, and data register 3
The data Ba in Ib is sequentially rewritten, and at the end of the manual operation, a "1" signal is output from the highest D flip-flop 35b-255 of the pointer 35b, and this is output from the lowest D flip-flop 35a-0 of the pointer 35a. and the OR gate 72. As a result, as soon as the data CD serial input is started, the OR gate 97 outputs a serial runout signal SR○, which is sent to the display controller 5I.

(lt) Write data transfer of data B and read data transfer of data D] (during data C serial manual input) When the display controller 51 receives the serial runout signal SRO, the register 31
Data B is transferred as write data to the array 1b using the B memory. Next, the data Da is sent as read data from the memory cell array 1b to the data nozzle 31b.

During this period, the serial input of data C continues in the data register 313.\, and the data C in the data register 31a continues.
a is rewritten.

(5) When detecting the manual termination of serial manual stop data C, the display controller 5
1 sets the serial enable signal S E N to "0" and instructs to stop the serial manual operation. As a result, the memory device 52 closes the AND gate 88, sets the serial manual mode signal SIM to "0", and stops serial input.

(6) Write data transfer of data C and data D Finally, data C manually input in serial and data Da transferred as read data are transferred as write data from data registers 31a and 31b to memory cell arrays la and lb. This will terminate the serial operation.

Thus, in this embodiment, one data register 31a
(or 31b) Since the read data transfer and write data transfer are performed using the other data register 31b (mafko 31a) while the data register is being manually operated,
Can be continuously serialized manually.

In addition, in the above operation, the reason why read data is transferred is to save the part that will not be rewritten when part of the row data is rewritten, as mentioned above.
When it is known in advance that the entire row data will be manually input serially, as in the case of data B, read data transfer is not necessary.

(III) High-speed copy mode 25 The operation of transferring data at row address A to row addresses B and C as shown in FIG. 25 (C) will be described.

(1) First, the display controller 51
Bull signal SEN is set to “0”, full serial buffer signal F
Set SB to "1". As a result, both the serial mode signals S[M and SOM become "0", the serial system operation is stopped, and the OR gates 90c, 90d, 9
An "I" signal is output from 5a and 95b, and learning of data transfer is performed on both the a side and the b side.

(2) The display controller 51 commands read data transfer using row address A. As a result, the data transfer control signal DTC is output, and the memory cell array la
, data at row address A of l b is stored in data register 3.
1a and 31b at once.

(3) Next, the display controller 51 transfers the contents of the data registers 31a and 31b to the memory cell array la.

Transfer write data to row address B of lb. After this transfer is completed, write data of the same contents of data registers 31a and 31b is transferred to row address C.

(4) The process ends when the write data has been transferred to all specified row addresses.

If this high-speed copy mode is used, it is possible to transfer data within the memory at high speed, which is particularly effective for processing such as screen scrolling.

In the above embodiment, the length 256 of one row of the memory cell array is divided into three equal parts, but the invention is not limited to this. For example, when the length of a row in a memory cell array is N, one side may be I and the other side may be NK (N is a positive integer of one color).

[2JI Channel of the Invention] As explained above, the present invention provides a pair of data registers, and while one of the pair performs serial input/output, the other performs data transfer with the memory cell array. Now that I have prepared the output,
You can increase the following effects.

(1) There is no need to synchronize the output enable signal that instructs data transfer with the serial control clock that advances serial input/output.

(2) It becomes possible to rewrite only part of the row data in the memory cell array and save the other part as is.

(3) Continuous serial labor becomes possible.

In particular, since a serial runout signal is output when the register that performs serial input/output is switched, the display controller can accurately grasp the change in serial input/output.

1 Brief Description of the Drawings FIG. 1 shows the overall structure of an image display device to which a memory device or an image display device according to an embodiment of the present invention is applied.

2 is a circuit diagram showing the configuration of the main parts of the memory device, FIG. 3 is a block diagram showing the configuration of the circuit that forms the main control signals of the memory device, and FIG. 4 is a data transfer operation. 5 is a conceptual diagram to explain the operation of serial output, serial manual input, and high-speed copy modes in the same memory device. FIG. 6 shows the configuration of a conventional dual port memory. The block diagram and FIG. 7 are timing charts for explaining the operation of the memory.

l a, l b... Memory cell array, 31
a, 31b...Data Reno Star, 35a, 35
b...Pointer, 61a, 61b...Data transfer gate (means for permitting data transfer), 66a, 6
6b...Serial data gate, SRO...
Serial runout signal.

Claims (2)

[Claims] (1) Separately transmitting and receiving data between a memory cell array of M rows and N columns, and data in columns K in the first half and columns NK in the latter half of any row of the memory cell array, and a pair of data registers that perform serial input/output alternately; an initializable pointer that indicates the serial input/output position in the data register; and a data register that does not perform serial input/output among the pair of data registers; 1. A memory device comprising: means for permitting data transfer to and from a memory cell array. (2) A serial runout signal is output from the pointer when the serial input/output position indicated by the pointer switches from one of the pair of data registers to the other. memory device.