JPS57186283A - Artificial speed-up system of low-speed memory - Google Patents

Artificial speed-up system of low-speed memory

Info

Publication number
JPS57186283A
JPS57186283A JP56070895A JP7089581A JPS57186283A JP S57186283 A JPS57186283 A JP S57186283A JP 56070895 A JP56070895 A JP 56070895A JP 7089581 A JP7089581 A JP 7089581A JP S57186283 A JPS57186283 A JP S57186283A
Authority
JP
Japan
Prior art keywords
speed
data
memory
low
processing section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56070895A
Other languages
Japanese (ja)
Inventor
Tsunetada Izumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP56070895A priority Critical patent/JPS57186283A/en
Publication of JPS57186283A publication Critical patent/JPS57186283A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Abstract

PURPOSE:To realize substantially high-speed data processings with relatively inexpensive low-speed memory elements, by installing registers which temporarily hold data between the data processing section and the memory section, etc. CONSTITUTION:Temporarily data holding registers 2 and 3 are installed between a data processing section (not shown in the diagram) and a memory section 5, and data processings are performed between the temporarily data holding registers 2, 3 and the data processing section or between the registers 2, 3 and the memory section 5. Therefore, substantially high-speed data processings can be performed with relatively inexpensive memory elements which are low in speed as compared with the operating time of the data processing section.
JP56070895A 1981-05-12 1981-05-12 Artificial speed-up system of low-speed memory Pending JPS57186283A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56070895A JPS57186283A (en) 1981-05-12 1981-05-12 Artificial speed-up system of low-speed memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56070895A JPS57186283A (en) 1981-05-12 1981-05-12 Artificial speed-up system of low-speed memory

Publications (1)

Publication Number Publication Date
JPS57186283A true JPS57186283A (en) 1982-11-16

Family

ID=13444716

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56070895A Pending JPS57186283A (en) 1981-05-12 1981-05-12 Artificial speed-up system of low-speed memory

Country Status (1)

Country Link
JP (1) JPS57186283A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62252590A (en) * 1986-04-24 1987-11-04 Ascii Corp Memory device
JPS62271291A (en) * 1986-05-20 1987-11-25 Ascii Corp Memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62252590A (en) * 1986-04-24 1987-11-04 Ascii Corp Memory device
JPS62271291A (en) * 1986-05-20 1987-11-25 Ascii Corp Memory device

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