JPH01144144A - Memory control system - Google Patents

Abstract

PURPOSE:To realize the effective application of a memory by using selectively a parity memory also as a data memory. CONSTITUTION:A latch means 8 holds data temporarily and a selector 7 selects the data on an address bus 12 or the means 8 to deliver it as an address to be given to a parity memory 2. When this memory 2 is used for parity, the data on the bus 12 is delivered from the selector 7. While the data on the latch 8 is delivered from the selector 7 when the memory 2 is used for data. For this purpose, the selector 7 is controlled each time. In such a way, a CMOS static RAM is used effectively.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 3) Problems to be solved by the invention Means for solving the problems (Figure 1) Working examples (Figure 1) (Figure 2) Effects of the invention [Summary] Regarding a memory control method for main memory and parity memory configured by CMOS static RAM, the purpose of the present invention is to enable the parity memory to be selectively used for parity or data. In a memory device equipped with a main memory and a parity memory constituted by a CMOS static RAM, a latch means for temporarily holding data is used to store either data on the address side or data on the latch means side as parity. When this parity memory is used as a parity memory, data on the address bus side is output from the selector, and when the parity memory is used as a data memory. is characterized in that the selector is controlled so as to output data on the latch means side from the selector.

[Industrial application field]

The present invention relates to a memory control system, and particularly to a system in which a parity memory can be selectively used as a normal memory when a CMOS static RAM is used in a memory system.

[Conventional technology]

In recent years, CMOS static RAM has become cheaper in price and is increasingly being used in place of DRAM.

When using a current CMOS static RAM, the mainstream is an 8-bit input/8-bit output memory, so the configuration of this CMOS static RAM will be explained with reference to FIG.

In FIG. 3, 31 is a main memory, 32 is a parity memory, 33 is a parity checker generator, 34 is a selector, 35 is a multiplexer, 36 is a bus gate, 37 is a JK-FF, and 38.39 is an AND gate. Gates 40 and 41 are exclusive OR (EOR) circuits.

Main memory 31 and parity memory 32 are CMOS
It is composed of static RAM.

When inputting data to the main memory 31, an address is input to the address bus 42, input data is input to the data bus 43, and R/W=rOJ is input. The input data is thereby written into the main memory 31. This input data is also transmitted to a parity checker generator 33 to create a parity PI. At this time, the parity po based on the previous input data output at the address is output from the parity memory 32, and is input to the EOR circuit 40 via the selector 34, and the parity po is outputted from the parity memory 32.
, compared to . For example, Pa-p.

= "1", the FOR circuit 40 outputs "0".

This rOJ is output from the multiplexer 35, but at this time, the EOR circuit 41 receives pOJ from the parity memory 32.
Since orlJ is applied, "1" is output from the FOR circuit 41, which is input to the bus 44 via the bus gate 36, and eventually the parity memory 32 has Po
The same "1" will be entered. In this way, the output P of the parity checker generator 33,
When the outputs of the parity memory 32 and
The same data as the output of checker generator 33 is entered.

Note that the output 8 of the parity memory 32 is connected to the selector 34.
An address signal for selecting one of the bits to be used for parity is applied to multiplexer 35, and an address signal for selecting one of its 8-bit outputs to be used for parity is applied to multiplexer 35. address signal is applied.

' Also, when reading data from the main memory 31, input the address to the address bus 42 and apply R/W="1", the data is read from the main memory 31,
Parity P0 is output from the parity memory 32.

At this time, since R/W=rlJ, the AND gate 38 is on, and the parity P0 is transmitted to the parity checker generator 33 via the selector 34 and the AND gate 38, and the output of the main memory 31 is It is compared with the parity P created from the data.

At this time, the parity checker generator 33 outputs rOJ when there is a mismatch.
*NMirOJ is output from the K-FF 37 to notify the CPU of the parity mismatch. As a result, the CPU is N
Perform Mi processing. After this, NMi can be cleared by WRITE to the NMi cancel register.

Of course, if this parity P, matches P, "1" is output from the AND gate 39, and the JK-FF 37 also *NMi
rlJ is output to notify the CPU of the parity value.

Note that the JK-FF37(7)('7) signal *R3T is output when the power is turned on or when the reset button is operated, and is used to reset the JK-FF37.

[Problem that the invention seeks to solve]

By the way, since CMOS static RAM can be banked up by power supply, it is used to hold important data, but it also has a parity memory for this purpose. However, CMOS static RAM has a lower probability of error occurrence than dynamic RAM, so when processing data that will be used in a short period of time,
Parity is especially necessary when there is no need to perform a parity check and the data is to be stored for a long period of time. Therefore, this 8
Since the parity memory for bit input and 8-bit output may be unnecessary in some cases, there is a problem that the amount of hardware increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory control method that allows the parity memory to be used as a normal memory when there is no need to perform a parity check, in order to overcome these problems.

(Means for solving the problem) In order to solve the above problem, in the present invention, as shown in FIG. 1, a selector 7 is provided on the address input side of the parity memory 2, and one input of the selector 7 is is the address bus 12, and the other input is the output of the latch 8 provided on the data bus 13 side.

Main memory 1 and parity memory 2 are CMOS
It is composed of static RAM.

When the parity memory 2 is used for parity as in the conventional case as in the case of FIG. 3, the control signal C8 is selected so that the output of the selector becomes the address signal input from the address bus 12. The behavior in this case is
Since this is the same as the case shown in FIG. 3, the explanation will be omitted. In FIG. 1, 3 is a parity checker generator, 4 is a selector, 5 is a multiplexer, 6 is a bus gate, 9 is an AND gate, and 10.11 is an EOR circuit.

Further, when the parity memory 2 is used as a normal memory, the control signal C3 is selected so that the output of the selector 7 becomes the one input from the latch 8. data bus 13
The values of each address and data register are output to.

When the address register is placed in the WRI, address data is output onto the data bus 13, and a launch signal C is applied to the latch 8 to latch the address data.

Next, when placing the data register in WRI, data bus 1
Data is output on the memory 2 for parity, and is applied to the parity memory 2 for writing processing.

When the data register is read, the data output from the parity memory 2 is output onto the data bus 13.

Note that an address signal for parity selection is applied to the selector 4 and the multiplexer 5 as in the case of FIG.

[Effect]

Since parity memory can be used not only as parity memory but also as normal memory, CMOS
Static RAM memory can be used efficiently.

〔Example〕

An embodiment of the present invention will be described based on FIG.

In Figure 2, the same symbols as in Figure 1 indicate the same parts.
In FIG. 2, 14 is a selector, 15 is a flip-flop (FF), 16 is a bus driver, and 17 is a JK-FF.
, 18 is an AND gate, and 20 is a data bus.

Next, the operation shown in FIG. 2 will be explained.

(1) When using parity memory for parity.

The control signal PCD output from the FF 15 is controlled to be "0". This PCD-rOJ turns off the bus driver 16, and the selector 7 turns off the address bus 1.
The address input from the 2 side is output, and the same address is transmitted to the parity memory 2 and the main memory 1.

When inputting data to main memory 1, R/W-rO
Enter J. Based on this, the input data on the data bus 13 is written into the main memory 1. This input data is transmitted to the parity checker generator 3 to create parity P1. At this time, the parity PO based on the previous input data outputted from the parity memory 2 at the address is outputted, inputted to the EOR circuit 10 via the selector 4, and compared with the parity P1. Then, the same data as the parity P0 is written into the parity memory 2 via the bus 20 in the same manner as described in FIG. Note that at this time, a control signal is output so that the bus gate 6 is turned on. That is, the bus gate 6 is controlled to be turned on when the parity memory 2 is used for parity. At this time, the bus driver 16 is controlled to be turned off.

Further, when reading data from the main memory 1, when an address is input to the address bus 12 and R/W-rlJ is applied, the data is read from the main memory 1 and the parity P is read from the parity memory 2. is output. At this time R
Since /W=rlJ, the AND gate 9 is on, and the parity P0 is transmitted to the parity checker generator 3 via the selector 4 and the AND gate 9. The parity checker generator 3 compares whether this parity P0 matches the parity P created from the output data of the main memory 1. Then, if they match, "1" is output, and if they do not match, "0" is output, so when there is a mismatch, *NMi "0" is output from JK-FF17.
" is output to notify the CPU of the parity mismatch. This is it.

The CPU performs NMi processing. Thereafter, MNi can be cleared by WRITE to the NMi cancellation register. Of course, if they match, "1" is output from the AND gate 18, and the JK-FF 17 also outputs *NMirlJ.
is output to notify the CPU of the parity match.

(2) When using parity memory as normal memory.

In this case, that is, when operating in the data mode in which data is written in the parity memory 2, "1" is written in a specific position of the mode register (not shown), and the address register, data・Address and data are written in each register.
- The CPU reads mode setting data from the mode register and outputs it onto the data bus 13.

As a result, "1" at the specific position is applied to the FF 15, and the FF 15 is set to "1" by the cent signal from the CPU. After setting to data mode in this way, C
The PU reads the address register and outputs it on the data bus 13. The data register is then read out and output onto the data bus 13.

As a result, the PCD output of the FF 15 becomes "1" so that the output of the latch 8 is input to the selector 7, the selector 7 outputs the address input from the latch 8 side, and the bus driver 16 is turned on. Further, the selector 14 outputs a selection control signal so that the latch 8 latches the data on the data bus 13. Parity memory 2
When used as a normal memory, as described above and shown in FIG. 1(B), address periods A and data periods alternately exist on the data bus 13, and addresses and data are output, respectively.

Therefore, when an address is output during the address period A, the selector 14 is controlled so that it outputs rlJ to the latch 8.

As a result, the latch 8 holds the address output to the data bus 13. When data is output in the next data period, the FF15 is controlled so that PCD=rl, so the selector 7 applies the data held in the latch 8 to the parity memory 2 as an address. I will do it. Moreover, the bus driver 16 is also turned on by this PCD=rlJ, and R/W=rOJ is applied, so that data is written in the parity memory 2.

Furthermore, if R/W = rlJ applied to the parity memory I72 during the data period, the data written in the parity memory 2 is read out, and the bus driver 1
6 and is output onto the data bus 13.

〔Effect of the invention〕

According to the present invention, the address is held in the latch 8, and the data on the address bus side is output to the selector 7, or
Since it is possible to selectively control whether data on the latch 8 side is output, the parity memory 2 can also be used as a data memory, and the parity memory can be used efficiently.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention. FIG. 3 is an explanatory diagram of a conventional example.

Claims (1)

[Claims] A memory device comprising a main memory (1) and a parity memory (2) constituted by a CMOS static RAM, which includes a latch means (8) for temporarily holding data, and an address bus (12). ) side or the data on the latch means (8) side as an address to the parity memory (2). When used as an address bus (12) from the selector (7) above.
When outputting data on the side and using the parity memory (2) as a data memory, the selector (7)
A memory control method characterized in that the selector (7) is controlled so as to output data on the latch means (8) side.