JP3737144B2 - Interrupt request circuit and interrupt request processing method - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to an interrupt request circuit used for a microcomputer or the like and an interrupt request processing method indicated by the interrupt request circuit.
[0002]
[Prior art]
An interrupt request circuit used for a microcomputer or the like receives an interrupt request signal from a peripheral circuit having a predetermined function (for example, a counter, an A / D conversion circuit, etc.), and outputs an interrupt request corresponding to the received interrupt request signal The signal is output to a central processing unit (hereinafter referred to as CPU). The interrupt request circuit has a plurality of flip-flops set in response to an interrupt request signal output from a corresponding peripheral circuit. When the state of the flip-flop changes from the reset state to the set state, the CPU receives the output of the flip-flop that has changed to the set state as an interrupt request output signal. Then, the CPU performs an interrupt process related to the peripheral circuit corresponding to the flip-flop changed to the set state. Thereafter, the CPU performs a clear operation for returning the flip-flop in the set state to the reset state. By this clear operation, the interrupt request circuit indicates that the interrupt process has been completed. Therefore, the CPU can determine whether or not there is an interrupt request in the peripheral circuit by detecting the state of the interrupt request circuit. If there is an interrupt request, the CPU performs the above-described clear operation after executing the corresponding interrupt process.
[0003]
[Problems to be solved by the invention]
However, a plurality of interrupt requests may occur asynchronously with the operation of the CPU. Therefore, if the next interrupt request is generated while the CPU executes processing for the first interrupt request, the next interrupt request may be cleared simultaneously by the clear operation for the first interrupt request. That is, in the above-described interrupt request circuit, an interrupt request to the CPU may be ignored.
[0004]
[Means for Solving the Problems]
In order to solve the above problem, an interrupt request circuit of the present invention includes a data holding circuit that holds first data indicating that an interrupt request is generated in response to an interrupt request signal, The bus line to which the third data is applied, and the first data held between the bus line and the data holding circuit and held by the data holding circuit in response to the first data and the second data. A logic circuit that outputs data to be maintained and outputs data that clears the first data held by the data holding circuit in response to the first data and the third data is provided.
[0005]
According to the interrupt request processing method of the present invention, an interrupt request signal is supplied to a predetermined data holding circuit and the first data is stored in the data holding circuit, and the data holding circuit storing the first data has a first step. And the step of giving the first data to all the data holding circuits except the data holding circuit.
[0006]
[Action]
According to the present invention, among the data holding circuits storing data indicating that there is an interrupt request, the first data is given only to the data holding circuit for which the interrupt request is accepted, and the other data holding circuits are supplied with the first data. As a result, the data of the data holding circuit in which the interrupt request is not accepted is maintained without being cleared.
[0007]
【Example】
FIG. 1 is a diagram showing an embodiment of an interrupt request circuit according to the present invention.
[0008]
The configuration of an embodiment of the interrupt request circuit according to the present invention will be described below.
[0009]
The interrupt request circuit of the present invention includes flip-flops 101, 103, 105, 107 and 109 corresponding to the interrupt request input terminals 137, 139, 141, 143 and 145, and AND gates 111, 113, 115, 117 and 119, respectively. And have.
[0010]
The interrupt request input terminals 137 to 145 are terminals that receive an interrupt request signal from a circuit having an interrupt factor. For example, the interrupt request input terminal 137 is connected to an analog / digital conversion circuit (hereinafter referred to as an A / D conversion circuit), and receives an interrupt request signal from the A / D conversion circuit. The interrupt request input terminal 139 is connected to an input / output circuit (hereinafter referred to as an I / O circuit) and receives an interrupt request signal from the I / O circuit. Thus, each interrupt request input terminal receives an interrupt request signal from a dedicated circuit corresponding to each interrupt request input terminal.
[0011]
Data input terminals 147, 149, 151, and 153 correspond to the flip-flops 101, 103, 105, 107, and 109, respectively. The data input terminals 147 to 153 correspond to the data output terminals 157, 159, 161, 163, and 165, respectively. These data input terminals 147 to 153 are connected to bidirectional data lines together with corresponding data output terminals 157 to 165. For example, the data input terminal 147 is connected to the first bidirectional data line (not shown) together with the data output terminal 157. The data input terminal 149 is connected to a second bidirectional data line (not shown) together with the data output terminal 159. In the present embodiment, description will be made on the assumption that the data bus is composed of eight data lines. Therefore, in this embodiment, description will be made assuming that there are eight flip-flops, eight data input terminals, and eight data output terminals. In addition, each configuration corresponding to the flip-flop, for example, AND gates 111 to 119 will be described as eight. (For ease of explanation, in the drawing, only five flip-flops and respective components corresponding to the flip-flops are illustrated.)
The flip-flop 101 includes a set terminal connected to the interrupt request input terminal 137, a data input terminal D connected to the output terminal of the AND gate 111, and a data output terminal Q connected to one input terminal of the AND gate 111. A reset terminal R connected to the reset terminal 167, and a gate terminal G connected to the output terminal of the AND gate 121. The data output terminal Q of the flip-flop 101 is further connected to the gate circuit 125 and the interrupt request signal output circuit 135. Similarly to the flip-flop 101, each of the other flip-flops 103 to 109 also has corresponding interrupt request input terminals 139 to 145, AND gates 113 to 119, a reset terminal 167, an AND gate 121, gate circuits 127 to 133, and interrupt requests. The signal output circuit 135 is connected. These flip-flops have a function of holding data applied to the data input terminal D. Therefore, these flip-flops function as 8-bit registers or latch circuits. (Hereinafter, when these eight flip-flops are considered as one unit, the eight flip-flops are referred to as interrupt request registers.)
The gate circuits 125 to 133 are connected to the input terminal connected to the data output terminal Q of each corresponding flip-flop, the output terminal connected to each corresponding interrupt request output terminal 157 to 165, and the output terminal of the AND gate 123. Connected control terminals.
[0012]
The AND gate 121 receives a write address signal output from the address decoder and a write permission signal WR output from a central processing unit (hereinafter referred to as CPU), and outputs a write signal to each flip-flop.
[0013]
The AND gate 123 receives the read address signal output from the address decoder and the read permission signal RD output from the CPU, and outputs a read signal to each of the gate circuits 125 to 133.
[0014]
The interrupt request signal output circuit 135 detects a change in data appearing at the data output terminal Q of each flip-flop, and outputs an interrupt request output signal to the CPU.
[0015]
The circuit shown in FIG. 1 described above is a part of the system shown in FIG.
[0016]
The positioning of the interrupt request circuit of the present invention in the system shown in FIG. 2 and the system configuration will be described below.
[0017]
The interrupt request circuit of the present invention shown in FIG. 1 is a portion to which reference numeral 201 or 203 is given in FIG. In addition, the same code | symbol as the code | symbol provided in FIG. 1 is provided to the structure same as FIG.
[0018]
The interrupt request circuit 201 is connected to an 8-bit data bus 217 via an 8-bit bidirectional data bus 221. The eight data lines constituting the bidirectional data bus 221 are connected to data input terminals 147 to 155 in FIG. Further, these eight data lines are also connected to data output terminals 157 to 165, respectively.
[0019]
The A / D conversion circuit 209 outputs an interrupt request signal to the interrupt request circuit 201 when an interrupt factor occurs inside. The interrupt request signal output from the A / D conversion circuit 209 is applied to the interrupt request input terminal 137 in FIG.
[0020]
The I / O circuit 211 outputs an interrupt request signal to the interrupt request circuit 201 when an interrupt factor occurs inside. The interrupt request signal output from the I / O circuit 211 is applied to the interrupt request input terminal 139 in FIG.
[0021]
The I / O circuit 213 outputs an interrupt request signal to the interrupt request circuit 201 when an interrupt factor occurs inside. The interrupt request signal output from the I / O circuit 213 is applied to the interrupt request input terminal 141 in FIG.
[0022]
The random access memory circuit 215 (hereinafter referred to as RAM) outputs an interrupt request signal to the interrupt request circuit 203 when an interrupt factor occurs inside. The interrupt request circuit 203 has the same configuration as the interrupt request circuit 201. Therefore, the interrupt request signal output from the RAM 215 is applied to one of interrupt request input terminals in the interrupt request circuit 203 (not shown).
[0023]
The CPU 205 outputs a write permission signal WR and a read permission signal RD. The CPU 205 outputs an address signal for selecting one of the interrupt request circuits 201 and 203 to the address bus 219. Further, the CPU 205 receives the interrupt request output signals output from the interrupt request circuits 201 and 203 via the interrupt request output line 224. Further, the CPU 205 generates data for clearing the interrupt request indicated by the interrupt request circuits 201 and 203, and provides this data to the interrupt request circuits 201 and 203 via the data bus 217.
[0024]
The address decoder 207 decodes the address signal output from the CPU 205 and outputs a selection signal for selecting the interrupt request circuit 201 to the AND gates 123 and 121, or a selection signal for selecting the interrupt request circuit 203 to the AND gates 223 and 225. Output.
[0025]
The AND gate 123 inputs the read permission signal RD output from the CPU 205 and the selection signal for selecting the interrupt request circuit 201 output from the address decoder 207, and outputs a read signal to the interrupt request circuit 201.
[0026]
The AND gate 121 receives the write permission signal WR and the selection signal for selecting the interrupt request circuit 201 output from the address decoder 207, and outputs a write signal to the interrupt request circuit 201.
[0027]
Write and read signal output to the interrupt request circuit 203 are performed via AND gates 223 and 225. The operations of writing to the interrupt request circuit 203 and outputting a read signal are the same as the operations related to the interrupt request circuit 201.
[0028]
Next, the operation of the interrupt request circuit of the present invention shown in FIGS. 1 and 2 will be described with reference to the time chart of FIG. In the time chart of FIG. 3, time elapses from the left to the right of the page. The upper part of FIG. 3 is a diagram showing the contents of data held in the interrupt request register (the above-described eight flip-flops), and the lower part is a figure showing the contents held by the registers in the CPU. Has been placed.
[0029]
(Interrupt factor A occurs)
First, it is assumed that an interrupt request register composed of flip-flops is initialized by a reset signal supplied to the reset terminal 167. That is, each flip-flop outputs data 0 from each data output terminal Q. (Data 0 is, for example, 0V, and data 1 is, for example, 5V.)
Next, the A / D conversion circuit 209 generates an interrupt factor A for converting analog data given from the outside into digital data, for example. This interrupt factor A is given to the interrupt request input terminal 137 in the interrupt request circuit 201 as an interrupt request signal. Since the interrupt request signal applied to the interrupt request input terminal 137 is applied to the set terminal S of the flip-flop 101, the data output from the data output terminal Q of the flip-flop 101 changes from 0 to 1. Since there are no interrupt factors in the other peripheral circuits, the flip-flops 103 to 109 are not set. Therefore, the data output from the data output terminal Q of the flip-flops 103 to 109 is zero. As shown in the upper part of FIG. 3, the content of the interrupt request register is (10000000) as a result.
[0030]
(Interrupt request output signal generation)
When the data output terminal Q of the flip-flop 101 changes from 0 to 1, the interrupt request signal output circuit 135 detects this change and outputs an interrupt request output signal to the CPU 205. The CPU 205 recognizes that an interrupt factor has occurred in any of the circuits by receiving this interrupt request output signal. Next, the CPU 205 identifies a circuit in which an interrupt factor has occurred, and determines whether or not to accept the interrupt factor and when to accept it.
[0031]
(Reading data from the interrupt request register)
First, the CPU 205 outputs a read permission signal RD and an address signal for selecting the interrupt request circuit 201 to the address bus 219 in order to read the contents of the interrupt request register in the interrupt request circuit 201. The address decoder 207 decodes the address signal output from the CPU and outputs a selection signal for selecting the interrupt request circuit 201. The AND gate 123 outputs a read signal in response to the selection signal and the read permission signal RD. On the other hand, the AND gate 121 does not output the write signal because the write permission signal WR is not output. Since the CPU 205 does not select the interrupt request circuit 203, the AND gates 223 and 225 are in a disabled state.
[0032]
The gate circuits 125 to 133 are turned on in response to the read signal output from the AND gate 123, and the data output terminals Q of the flip-flops 101 to 109 and the data corresponding to the flip-flops 101 to 109, respectively. Electrical connection is established between the output terminals 157 to 165. Since the data output terminal Q of the flip-flop 101 outputs data 1, data 1 is given to the data output terminal 157, and the data output terminals Q of the other flip-flops 103 to 109 output data 0. Data 0 is applied to the output terminals 159 to 165. Each data applied to the data output terminals 157 to 165 is applied to the data bus 217 via the bidirectional data bus 221. The CPU 205 reads the 8-bit data supplied to the data bus 217 into a register in the CPU 205. Since the data bus 217 is now (10000000), the CPU 205 recognizes that the content of the interrupt request register in the interrupt request circuit 201 is (10000000). That is, the CPU 205 recognizes that the interrupt factor A has occurred in the A / D conversion circuit 209.
[0033]
The CPU 205 determines whether or not the interrupt factor A has priority over the main process that the CPU 205 is currently executing. If the interrupt factor A has a higher priority than the currently executed process, the CPU 205 immediately enters the process flow for converting analog data to digital data immediately after finishing the current process. . That is, the CPU 205 interrupts the A / D conversion process during the main process flow. Here, since the timing of executing the interrupt processing varies depending on the program, it may be after other processing is performed after an interrupt request is made. Here, the CPU 205 enters a flow in which A / D conversion processing is performed immediately after ending the current processing. The A / D conversion circuit 209 converts analog data given from a peripheral circuit (not shown) into digital data in accordance with an A / D conversion flow controlled by the CPU 205. The converted digital data is transferred to, for example, the RAM 215 via the data bus 217 in accordance with an instruction from the CPU 205.
[0034]
(Clear interrupt request register (when interrupt factor B has not occurred))
After completing the interrupt processing, the CPU 205 starts an operation of clearing the output of the flip-flop 101 corresponding to the interrupt factor A. First, the CPU 205 generates data (01111111) and writes the data (01111111) to an 8-bit register in the CPU. That is, the CPU 205 creates clear data in which only the bit corresponding to the interrupt factor A is data 0 and the other bits are data 1, and stores the clear data in a register in the CPU 205. Subsequently, the CPU 205 outputs this clear data to the data bus 217. Clear data applied to the data bus 217 is applied to the data input terminals 147 to 155 of the interrupt request circuit 201 via the bidirectional data bus 221. Since the flip-flop 101 is outputting data 1 and the flip-flops 103 to 109 are outputting data 0, only the AND gate 111 is open. Therefore, the data 0 given to the data input terminal 147 passes through the AND gate 111 and is given to the data input terminal D of the flip-flop 101. Since the AND gates 113 to 119 are all closed, the data input terminals D of the flip-flops 103 to 109 are given data 0 regardless of the data given to the data input terminals 149 to 155. Note that clear data is similarly applied to the interrupt request circuit 203. However, as will be described later, since the CPU 205 does not select the interrupt request circuit 203, the clear data does not affect the operation of the interrupt request circuit 203 at all.
[0035]
Subsequently, the CPU 205 outputs a write permission signal WR and outputs an address signal for selecting the interrupt request circuit 201 to the address bus 219 in order to clear data corresponding to the interrupt factor A in the interrupt request register. The address decoder 207 decodes the address signal output from the CPU and outputs a selection signal for selecting the interrupt request circuit 201. The AND gate 121 outputs a write signal in response to the selection signal and the write permission signal WR. On the other hand, the AND gate 123 does not output the read signal because the read permission signal RD is not output. Since the CPU 205 does not select the interrupt request circuit 203, the AND gates 223 and 225 are in a disabled state.
[0036]
When the write signal is applied to the gate terminals G of the flip-flops 101 to 109, the flip-flops 101 to 109 capture the data applied to the data input terminal D and output the captured data to the data output terminal Q. Here, since data 0 is given to the data input terminal D of the flip-flop 101, the flip-flop 101 outputs data 0 in response to the write signal given to the gate terminal G. Similarly, the other flip-flops 103 to 109 output data 0 in response to a write signal applied to each gate terminal G. As described above, the output of the interrupt request register in the interrupt request circuit 201 changes from (10000000) to (00000000). That is, the data corresponding to the interrupt factor A in the interrupt request register is cleared. The operation in the case where another interrupt factor has not occurred before clearing the interrupt register has been described above, but the operation in the case where another interrupt factor has occurred will be described below.
[0037]
(Interrupt factor B occurs)
Assume that after the occurrence of the interrupt factor A and before the data in the interrupt request register corresponding to the interrupt factor A is cleared, the I / O circuit 213 generates an interrupt factor B indicating that there is an abnormality inside. This interrupt factor B is given as an interrupt request signal to the interrupt request input terminal 141 in the interrupt request circuit 201. Since the interrupt request signal applied to the interrupt request input terminal 141 is applied to the set terminal S of the flip-flop 105, the data output from the data output terminal Q of the flip-flop 105 changes from 0 to 1. Since only the flip-flop 101 outputs data 1 due to the interrupt factor A generated in the A / D conversion circuit 209, the content of the interrupt request register is (10100000) as a result.
[0038]
(Interrupt request output signal generation)
When the data output terminal Q of the flip-flop 105 changes from 0 to 1, the interrupt request signal output circuit 135 detects this change and outputs an interrupt request output signal to the CPU 205. The CPU 205 recognizes that an interrupt factor has occurred in any of the circuits by receiving this interrupt request output signal. Next, the CPU 205 identifies a circuit in which an interrupt factor has occurred, and determines whether or not to accept the interrupt factor and when to accept it. Since the CPU 205 is about to clear the data in the interrupt request register corresponding to the interrupt factor A, this determination is made after clearing the data in the interrupt request register.
[0039]
(Clear interrupt request register)
After completing the interrupt processing related to the interrupt factor A, the CPU 205 starts an operation of clearing the output of the flip-flop 101 corresponding to the interrupt factor A. First, the CPU 205 generates data (01111111) and writes the data (01111111) to an 8-bit register in the CPU. That is, the CPU 205 creates clear data in which only the bit corresponding to the interrupt factor A is data 0 and the other bits are data 1, and stores the clear data in a register in the CPU 205. Subsequently, the CPU 205 outputs this clear data to the data bus 217. Clear data applied to the data bus 217 is applied to the data input terminals 147 to 155 of the interrupt request circuit 201 via the bidirectional data bus 221. Since the flip-flops 101 and 105 output data 1 and the flip-flops 103 and 107 to 109 output data 0, only the AND gates 111 and 115 are open. Therefore, the data 0 given to the data input terminal 147 passes through the AND gate 111 and is given to the data input terminal D of the flip-flop 101. The data 1 applied to the data input terminal 151 passes through the AND gate 115 and is applied to the data input terminal D of the flip-flop 105. Since the AND gates 113 and 117 to 119 are closed, data 0 is supplied to the data input terminals D of the flip-flops 103 and 107 to 109 regardless of the data supplied to the data input terminals 149 and 153 to 155. Note that clear data is similarly applied to the interrupt request circuit 203. However, as will be described later, since the CPU 205 does not select the interrupt request circuit 203, the clear data does not affect the operation of the interrupt request circuit 203 at all.
[0040]
Subsequently, the CPU 205 outputs a write permission signal WR and outputs an address signal for selecting the interrupt request circuit 201 to the address bus 219 in order to clear data corresponding to the interrupt factor A in the interrupt request register. The address decoder 207 decodes the address signal output from the CPU and outputs a selection signal for selecting the interrupt request circuit 201. The AND gate 121 outputs a write signal in response to the selection signal and the write permission signal WR. On the other hand, the AND gate 123 does not output the read signal because the read permission signal RD is not output. Since the CPU 205 does not select the interrupt request circuit 203, the AND gates 223 and 225 are in a disabled state.
[0041]
When the write signal is applied to the gate terminals G of the flip-flops 101 to 109, the flip-flops 101 to 109 capture the data applied to the data input terminal D and output the captured data to the data output terminal Q. Here, since data 0 is given to the data input terminal D of the flip-flop 101, the flip-flop 101 outputs data 0 in response to the write signal given to the gate terminal G. Further, since data 1 is given to the data input terminal D of the flip-flop 105, the flip-flop 105 outputs data 1 in response to the write signal given to the gate terminal G. The flip-flops 103 and 107 to 109 output data 0 in response to a write signal given to each gate terminal G. As described above, the output of the interrupt request register in the interrupt request circuit 201 changes from (10100000) to (00100000). That is, only the data corresponding to the interrupt factor A is cleared without clearing the data corresponding to the interrupt factor B of the interrupt request register.
[0042]
(Reading data from the interrupt request register)
Next, the CPU 205 accesses the interrupt request circuit 201 in order to identify the circuit in which the interrupt factor has occurred based on the interrupt request output signal output from the interrupt request circuit 201 previously. Then, the CPU 205 determines whether or not to accept the interrupt factor and when to accept it.
[0043]
First, the CPU 205 outputs a read permission signal RD and an address signal for selecting the interrupt request circuit 201 to the address bus 219 in order to read the contents of the interrupt request register in the interrupt request circuit 201. The address decoder 207 decodes the address signal output from the CPU and outputs a selection signal for selecting the interrupt request circuit 201. The AND gate 123 outputs a read signal in response to the selection signal and the read permission signal RD. On the other hand, the AND gate 121 does not output the write signal because the write permission signal WR is not output. Since the CPU 205 does not select the interrupt request circuit 203, the AND gates 223 and 225 are in a disabled state.
[0044]
The gate circuits 125 to 133 are turned on in response to the read signal output from the AND gate 123, and the data output terminals Q of the flip-flops 101 to 109 and the data corresponding to the flip-flops 101 to 109, respectively. Electrical connection is established between the output terminals 157 to 165. Since data output terminal Q of flip-flop 105 outputs data 1, data 1 is applied to data output terminal 161, and data output terminals Q of flip-flops 101, 103 and 107-109 output data 0. Therefore, data 0 is given to the data output terminals 157, 159 and 163 to 165.
[0045]
Each data applied to the data output terminals 157 to 165 is applied to the data bus 217 via the bidirectional data bus 221. The CPU 205 reads the 8-bit data supplied to the data bus 217 into a register in the CPU 205. Since the data bus 217 is now (00100000), the CPU 205 recognizes that the content of the interrupt request register in the interrupt request circuit 201 is (00100000). That is, the CPU 205 recognizes that an interrupt factor B is newly generated in the I / O circuit 213. The CPU 205 determines whether or not this interrupt factor B has priority over the process that the CPU 205 is currently executing. If this interrupt factor B has a higher priority than the currently executed process, the CPU 205 immediately enters the processing flow for the interrupt factor B. That is, the CPU 205 interrupts the processing related to the interrupt factor B during the main processing flow. Here, the processing related to the interrupt factor B is immediately executed.
[0046]
The CPU 205 determines that the I / O circuit 213 cannot be used due to an abnormality due to the interrupt factor B. Then, when an instruction to use the I / O circuit 211 is subsequently given, the CPU 205 performs processing flow change processing so that the I / O circuit 211 is used.
[0047]
(Clear interrupt request register)
Subsequently, the CPU 205 starts an operation of clearing the output of the flip-flop 105 corresponding to the interrupt factor B. First, the CPU 205 generates data (11011111) and writes the data (11011111) to an 8-bit register in the CPU. That is, the CPU 205 creates clear data in which only the bit corresponding to the interrupt factor B is data 0, and the other bits are data 1, and stores the clear data in a register in the CPU 205. Subsequently, the CPU 205 outputs this clear data to the data bus 217. Clear data applied to the data bus 217 is applied to the data input terminals 147 to 155 of the interrupt request circuit 201 via the bidirectional data bus 221. Since the flip-flop 105 outputs data 1 and the flip-flops 101, 103 and 107 to 109 output data 0, only the AND gate 115 is open. However, since data supplied to the data input terminal 151 is 0, data 0 is supplied to the data input terminal D of the flip-flop 105. Since the AND gates 111, 113 and 117 to 119 are closed, the data input terminals D of the flip-flops 101, 103 and 107 to 109 are independent of the data given to the data input terminals 147, 149 and 153 to 155. Data 0 is given. Note that clear data is similarly applied to the interrupt request circuit 203. However, since the CPU 205 does not select the interrupt request circuit 203, this clear data does not affect the operation of the interrupt request circuit 203 at all.
[0048]
Subsequently, the CPU 205 outputs a write permission signal WR and outputs an address signal for selecting the interrupt request circuit 201 to the address bus 219 in order to clear data corresponding to the interrupt factor B in the interrupt request register. The address decoder 207 decodes the address signal output from the CPU and outputs a selection signal for selecting the interrupt request circuit 201. The AND gate 121 outputs a write signal in response to the selection signal and the write permission signal WR. On the other hand, the AND gate 123 does not output the read signal because the read permission signal RD is not output. Since the CPU 205 does not select the interrupt request circuit 203, the AND gates 223 and 225 are in a disabled state.
[0049]
When the write signal is applied to the gate terminals G of the flip-flops 101 to 109, the flip-flops 101 to 109 capture the data applied to the data input terminal D and output the captured data to the data output terminal Q. Here, since data 0 is given to the data input terminals D of all the flip-flops 101 to 109, each flip-flop 101 to 109 receives data 0 in response to a write signal given to each gate terminal G. Output.
[0050]
As described above, the output of the interrupt request register in the interrupt request circuit 201 changes from (00100000) to (00000000). That is, the data corresponding to the interrupt factor B in the interrupt request register is cleared.
[0051]
At this time, the outputs of the interrupt request registers all become 0, so the CPU 205 determines that there is no interrupt request from the peripheral circuit. Therefore, the CPU 205 returns to the interrupted main processing flow.
[0052]
According to the embodiment of the present invention described above, there are the following advantages.
[0053]
A plurality of interrupt requests to the CPU are generated asynchronously with the operation of the CPU. However, according to the present invention, even when the interrupt factor B is newly generated from another peripheral circuit while the CPU is performing the interrupt processing related to the interrupt factor A as described above, The corresponding flip-flop output is not cleared. Therefore, the CPU can recognize that the interrupt factor B is generated even after the clear operation related to the interrupt factor A is completed. Therefore, the interrupt process related to the interrupt factor B is executed without being ignored.
[0054]
In the clear data configuration according to the present invention, the first data given to the flip-flop corresponding to the interrupt factor to be cleared, the other flip-flop, that is, the flip-flop corresponding to the other interrupt factor and the interrupt factor are generated. The second data is uniformly given to the non-flip-flops. Therefore, the clear data generated by the CPU can be generated only by changing only one bit of the plurality of bits constituted by the second data to the first data. Therefore, the time required for generating the clear data is very short, and the operation speed of the CPU is not reduced by generating the clear data.
[0055]
According to the present invention, the clear operation of the interrupt request (output of the interrupt request register) indicated by the interrupt request circuit is executed by the data transferred to the data bus. That is, according to the present invention, a dedicated circuit such as an interrupt clear selector for selectively clearing only the flip-flop corresponding to the generated interrupt factor is not required. Therefore, interrupt processing can be executed reliably without increasing the circuit scale of the entire system.
[0056]
Next, the configuration of another embodiment of the interrupt request circuit of the present invention will be described.
[0057]
FIG. 4 is a diagram showing the configuration of another embodiment of the interrupt request circuit of the present invention. In FIG. 4, the same components as those in FIG.
[0058]
The difference between the interrupt request circuit shown in FIG. 4 and the interrupt request circuit shown in FIG. 1 is that the interrupt request input terminals 137 to 145 are connected to the reset terminals R of the flip-flops 101 to 109, respectively. Are connected to the set terminals S of the flip-flops 101 to 109, and OR gates 401 to 409 are connected to the data terminals D of the flip-flops 101 to 109, respectively. Other configurations are the same as those in FIG. Also, the positioning of the interrupt request circuit of FIG. 4 in the system of FIG. 2 is the same as the relationship between FIG. 1 and FIG.
[0059]
Next, the operation of the interrupt request circuit of the present invention shown in FIG. 4 will be described with reference to the time chart of FIG. The difference between the operation of the interrupt request circuit shown in FIG. 4 and the operation of the interrupt request circuit shown in FIG. 1 is that the data output terminal Q of the flip-flop outputs data 0 when an interrupt factor occurs in the peripheral circuit. .
[0060]
(Interrupt factor A occurs)
First, it is assumed that an interrupt request register composed of flip-flops is initialized by a reset signal supplied to the reset terminal 167. That is, each flip-flop outputs data 1 from each data output terminal Q. (Data 0 is, for example, 0V, and data 1 is, for example, 5V.)
Next, the A / D conversion circuit 209 generates an interrupt factor A for converting analog data given from the outside into digital data, for example. This interrupt factor A is given to the interrupt request input terminal 137 in the interrupt request circuit 201 as an interrupt request signal. Since the interrupt request signal applied to the interrupt request input terminal 137 is applied to the reset terminal R of the flip-flop 101, the data output from the data output terminal Q of the flip-flop 101 changes from 1 to 0. Since there are no interrupt factors in the other peripheral circuits, the flip-flops 103 to 109 are not reset. Therefore, the data output from the data output terminal Q of the flip-flops 103 to 109 remains at 1. As shown in the upper part of FIG. 5, the content of the interrupt request register is (01111111) as a result.
[0061]
(Interrupt request output signal generation)
When the data output terminal Q of the flip-flop 101 changes from 1 to 0, the interrupt request signal output circuit 135 detects this change and outputs an interrupt request output signal to the CPU 205. The CPU 205 recognizes that an interrupt factor has occurred in any of the circuits by receiving this interrupt request output signal. Next, the CPU 205 identifies a circuit in which an interrupt factor has occurred, and determines whether or not to accept the interrupt factor and when to accept it.
[0062]
(Reading data from the interrupt request register)
First, the CPU 205 outputs a read permission signal RD and an address signal for selecting the interrupt request circuit 201 to the address bus 219 in order to read the contents of the interrupt request register in the interrupt request circuit 201. The address decoder 207 decodes the address signal output from the CPU and outputs a selection signal for selecting the interrupt request circuit 201. The AND gate 123 outputs a read signal in response to the selection signal and the read permission signal RD. On the other hand, the AND gate 121 does not output the write signal because the write permission signal WR is not output. Since the CPU 205 does not select the interrupt request circuit 203, the AND gates 223 and 225 are in a disabled state.
[0063]
The gate circuits 125 to 133 are turned on in response to the read signal output from the AND gate 123, and the data output terminals Q of the flip-flops 101 to 109 and the data corresponding to the flip-flops 101 to 109, respectively. Electrical connection is established between the output terminals 157 to 165. Since the data output terminal Q of the flip-flop 101 outputs data 0, data 0 is given to the data output terminal 157, and the data output terminals Q of the other flip-flops 103 to 109 output data 1, so that data Data 1 is applied to the output terminals 159 to 165. Each data applied to the data output terminals 157 to 165 is applied to the data bus 217 via the bidirectional data bus 221. The CPU 205 reads the 8-bit data supplied to the data bus 217 into a register in the CPU 205. Since the data bus 217 is now (01111111), the CPU 205 recognizes that the content of the interrupt request register in the interrupt request circuit 201 is (01111111). That is, the CPU 205 recognizes that the interrupt factor A has occurred in the A / D conversion circuit 209.
[0064]
The CPU 205 determines whether or not the interrupt factor A has priority over the main process that the CPU 205 is currently executing. If the interrupt factor A has a higher priority than the currently executed process, the CPU 205 immediately enters the process flow for converting analog data to digital data immediately after finishing the current process. . That is, the CPU 205 interrupts the A / D conversion process during the main process flow. Here, since the timing of executing the interrupt processing varies depending on the program, it may be after other processing is performed after an interrupt request is made. Here, the CPU 205 enters a flow in which A / D conversion processing is performed immediately after ending the current processing. The A / D conversion circuit 209 converts analog data given from a peripheral circuit (not shown) into digital data in accordance with an A / D conversion flow controlled by the CPU 205. The converted digital data is transferred to, for example, the RAM 215 via the data bus 217 in accordance with an instruction from the CPU 205.
[0065]
(Clear interrupt request register (when interrupt factor B has not occurred))
After completing the interrupt processing, the CPU 205 starts an operation of clearing the output of the flip-flop 101 corresponding to the interrupt factor A. First, the CPU 205 generates data (10000000) and writes the data (10000000) to an 8-bit register in the CPU. That is, the CPU 205 creates clear data in which only the bit corresponding to the interrupt factor A is data 1 and the other bits are data 0, and stores the clear data in a register in the CPU 205. Subsequently, the CPU 205 outputs this clear data to the data bus 217. Clear data applied to the data bus 217 is applied to the data input terminals 147 to 155 of the interrupt request circuit 201 via the bidirectional data bus 221. Now, since the flip-flop 101 is outputting data 0, the data 1 given to the data input terminal 147 passes through the OR gate 401 and is given to the data input terminal D of the flip-flop 101. Since the flip-flops 103 to 109 output the data 1, the data 0 given to the data input terminals 149 to 155 passes through the OR gates 403 to 409 and is given to the data input terminals D of the flip-flops 103 to 109. It is done. Note that clear data is similarly applied to the interrupt request circuit 203. However, as will be described later, since the CPU 205 does not select the interrupt request circuit 203, the clear data does not affect the operation of the interrupt request circuit 203 at all.
[0066]
Subsequently, the CPU 205 outputs a write permission signal WR and outputs an address signal for selecting the interrupt request circuit 201 to the address bus 219 in order to clear data corresponding to the interrupt factor A in the interrupt request register. The address decoder 207 decodes the address signal output from the CPU and outputs a selection signal for selecting the interrupt request circuit 201. The AND gate 121 outputs a write signal in response to the selection signal and the write permission signal WR. On the other hand, the AND gate 123 does not output the read signal because the read permission signal RD is not output. Since the CPU 205 does not select the interrupt request circuit 203, the AND gates 223 and 225 are in a disabled state.
[0067]
When the write signal is applied to the gate terminals G of the flip-flops 101 to 109, the flip-flops 101 to 109 capture the data applied to the data input terminal D and output the captured data to the data output terminal Q. Here, since data 1 is given to the data input terminal D of the flip-flop 101, the flip-flop 101 outputs data 1 in response to the write signal given to the gate terminal G. Similarly, the other flip-flops 103 to 109 output data 1 in response to a write signal applied to each gate terminal G. As described above, the output of the interrupt request register in the interrupt request circuit 201 changes from (01111111) to (11111111). That is, the data corresponding to the interrupt factor A in the interrupt request register is cleared. The operation in the case where another interrupt factor has not occurred before clearing the interrupt register has been described above, but the operation in the case where another interrupt factor has occurred will be described below.
[0068]
(Interrupt factor B occurs)
Assume that after the occurrence of the interrupt factor A and before the data in the interrupt request register corresponding to the interrupt factor A is cleared, the I / O circuit 213 generates an interrupt factor B indicating that there is an abnormality inside. This interrupt factor B is given as an interrupt request signal to the interrupt request input terminal 141 in the interrupt request circuit 201. Since the interrupt request signal applied to the interrupt request input terminal 141 is applied to the reset terminal R of the flip-flop 105, the data output from the data output terminal Q of the flip-flop 105 changes from 1 to 0. Since only the flip-flop 101 outputs data 0 due to the interrupt factor A generated in the A / D conversion circuit 209, the content of the interrupt request register is (01011111) as a result.
[0069]
(Interrupt request output signal generation)
When the data output terminal Q of the flip-flop 105 changes from 1 to 0, the interrupt request signal output circuit 135 detects this change and outputs an interrupt request output signal to the CPU 205. The CPU 205 recognizes that an interrupt factor has occurred in any of the circuits by receiving this interrupt request output signal. Next, the CPU 205 identifies a circuit in which an interrupt factor has occurred, and determines whether or not to accept the interrupt factor and when to accept it. Since the CPU 205 is about to clear the data in the interrupt request register corresponding to the interrupt factor A, this determination is made after clearing the data in the interrupt request register.
[0070]
(Clear interrupt request register)
After completing the interrupt processing related to the interrupt factor A, the CPU 205 starts an operation of clearing the output of the flip-flop 101 corresponding to the interrupt factor A. First, the CPU 205 generates data (10000000) and writes the data (10000000) to an 8-bit register in the CPU. That is, the CPU 205 creates clear data in which only the bit corresponding to the interrupt factor A is data 1 and the other bits are data 0, and stores the clear data in a register in the CPU 205. Subsequently, the CPU 205 outputs this clear data to the data bus 217. Clear data applied to the data bus 217 is applied to the data input terminals 147 to 155 of the interrupt request circuit 201 via the bidirectional data bus 221. Since the flip-flop 101 is outputting data 0 now, data 1 is given to the data input terminal D of the flip-flop 101. Similarly, the flip-flop 105 outputs data 0, but since data 0 is given to the data input terminal 151, data 0 is given to the data input terminal D of the flip-flop 105. Since the flip-flops 103 and 107 to 109 output the data 1, the data input terminal D of the flip-flops 103 and 107 to 109 has the data 1 regardless of the data given to the data input terminals 149 and 153 to 155. Given. Note that clear data is similarly applied to the interrupt request circuit 203. However, as will be described later, since the CPU 205 does not select the interrupt request circuit 203, the clear data does not affect the operation of the interrupt request circuit 203 at all.
[0071]
Subsequently, the CPU 205 outputs a write permission signal WR and outputs an address signal for selecting the interrupt request circuit 201 to the address bus 219 in order to clear data corresponding to the interrupt factor A in the interrupt request register. The address decoder 207 decodes the address signal output from the CPU and outputs a selection signal for selecting the interrupt request circuit 201. The AND gate 121 outputs a write signal in response to the selection signal and the write permission signal WR. On the other hand, the AND gate 123 does not output the read signal because the read permission signal RD is not output. Since the CPU 205 does not select the interrupt request circuit 203, the AND gates 223 and 225 are in a disabled state.
[0072]
When the write signal is applied to the gate terminals G of the flip-flops 101 to 109, the flip-flops 101 to 109 capture the data applied to the data input terminal D and output the captured data to the data output terminal Q. Here, since data 1 is given to the data input terminal D of the flip-flop 101, the flip-flop 101 outputs data 1 in response to the write signal given to the gate terminal G. Since data 0 is applied to the data input terminal D of the flip-flop 105, the flip-flop 105 outputs data 0 in response to the write signal applied to the gate terminal G. The flip-flops 103 and 107 to 109 output data 1 in response to a write signal given to each gate terminal G. As described above, the output of the interrupt request register in the interrupt request circuit 201 changes from (0101111) to (11011111). That is, only the data corresponding to the interrupt factor A is cleared without clearing the data corresponding to the interrupt factor B of the interrupt request register.
[0073]
(Reading data from the interrupt request register)
Next, the CPU 205 accesses the interrupt request circuit 201 in order to identify the circuit in which the interrupt factor has occurred based on the interrupt request output signal output from the interrupt request circuit 201 previously. Then, the CPU 205 determines whether or not to accept the interrupt factor and when to accept it.
[0074]
First, the CPU 205 outputs a read permission signal RD and an address signal for selecting the interrupt request circuit 201 to the address bus 219 in order to read the contents of the interrupt request register in the interrupt request circuit 201. The address decoder 207 decodes the address signal output from the CPU and outputs a selection signal for selecting the interrupt request circuit 201. The AND gate 123 outputs a read signal in response to the selection signal and the read permission signal RD. On the other hand, the AND gate 121 does not output the write signal because the write permission signal WR is not output. Since the CPU 205 does not select the interrupt request circuit 203, the AND gates 223 and 225 are in a disabled state.
[0075]
The gate circuits 125 to 133 are turned on in response to the read signal output from the AND gate 123, and the data output terminals Q of the flip-flops 101 to 109 and the data corresponding to the flip-flops 101 to 109, respectively. Electrical connection is established between the output terminals 157 to 165. Since data output terminal Q of flip-flop 105 outputs data 0, data 0 is applied to data output terminal 161, and data output terminals Q of flip-flops 101, 103 and 107-109 output data 1. Therefore, data 1 is supplied to the data output terminals 157, 159 and 163 to 165.
[0076]
Each data applied to the data output terminals 157 to 165 is applied to the data bus 217 via the bidirectional data bus 221. The CPU 205 reads the 8-bit data supplied to the data bus 217 into a register in the CPU 205. Since the data bus 217 is now (11011111), the CPU 205 recognizes that the content of the interrupt request register in the interrupt request circuit 201 is (11011111). That is, the CPU 205 recognizes that an interrupt factor B is newly generated in the I / O circuit 213. The CPU 205 determines whether or not this interrupt factor B has priority over the process that the CPU 205 is currently executing. If this interrupt factor B has a higher priority than the currently executed process, the CPU 205 immediately enters the processing flow for the interrupt factor B. That is, the CPU 205 interrupts the processing related to the interrupt factor B during the main processing flow. Here, the processing related to the interrupt factor B is immediately executed.
[0077]
The CPU 205 determines that the I / O circuit 213 cannot be used due to an abnormality due to the interrupt factor B. Then, when an instruction to use the I / O circuit 211 is subsequently given, the CPU 205 performs processing flow change processing so that the I / O circuit 211 is used.
[0078]
(Clear interrupt request register)
Subsequently, the CPU 205 starts an operation of clearing the output of the flip-flop 105 corresponding to the interrupt factor B. First, the CPU 205 generates data (00100000) and writes the data (00100000) to an 8-bit register in the CPU. That is, the CPU 205 creates clear data in which only the bit corresponding to the interrupt factor B is data 1 and the other bits are data 0, and stores the clear data in a register in the CPU 205. Subsequently, the CPU 205 outputs this clear data to the data bus 217. Clear data applied to the data bus 217 is applied to the data input terminals 147 to 155 of the interrupt request circuit 201 via the bidirectional data bus 221. Now, since the flip-flop 105 is outputting data 0, data 1 is given to the data input terminal D of the flip-flop 101 via the OR gate 405. Since the flip-flops 101, 103, and 107 to 109 output data 1, the data input terminals 147, 149, and 153 to 155 are supplied to the data input terminal D of the flip-flops 101, 103, and 107 to 109, respectively. Regardless, data 1 is given. Note that clear data is similarly applied to the interrupt request circuit 203. However, as will be described later, since the CPU 205 does not select the interrupt request circuit 203, the clear data does not affect the operation of the interrupt request circuit 203 at all.
[0079]
Subsequently, the CPU 205 outputs a write permission signal WR and outputs an address signal for selecting the interrupt request circuit 201 to the address bus 219 in order to clear data corresponding to the interrupt factor B in the interrupt request register. The address decoder 207 decodes the address signal output from the CPU and outputs a selection signal for selecting the interrupt request circuit 201. The AND gate 121 outputs a write signal in response to the selection signal and the write permission signal WR. On the other hand, the AND gate 123 does not output the read signal because the read permission signal RD is not output. Since the CPU 205 does not select the interrupt request circuit 203, the AND gates 223 and 225 are in a disabled state.
[0080]
When the write signal is applied to the gate terminals G of the flip-flops 101 to 109, the flip-flops 101 to 109 capture the data applied to the data input terminal D and output the captured data to the data output terminal Q. Here, since data 1 is given to the data input terminals D of all flip-flops 101 to 109, each flip-flop 101 to 109 receives data 1 in response to a write signal given to each gate terminal G. Output.
[0081]
As described above, the output of the interrupt request register in the interrupt request circuit 201 changes from (11011111) to (11111111). That is, the data corresponding to the interrupt factor B in the interrupt request register is cleared.
[0082]
Since all outputs of the interrupt request register are 1 at this time, the CPU 205 determines that there is no interrupt request from the peripheral circuit. Therefore, the CPU 205 returns to the interrupted main processing flow.
[0083]
As described above, the interrupt request circuit using the OR gate shown in FIG. 4 is a circuit indicating that an interrupt request is generated when the data output from the data output terminal Q of each flip-flop is 0. On the other hand, the interrupt request circuit using an AND gate shown in FIG. 1 is a circuit indicating that an interrupt request has occurred when the data output from the data output terminal Q of each flip-flop is 1. Since the operations of these two interrupt request circuits are basically the same, the designer can select either one of them when developing a system (program) such as a microcomputer. That is, by providing two types of interrupt request circuits, it is possible to design in consideration of the characteristics of the entire system such as a microcomputer.
[0084]
Next, a modification of the interrupt request circuit shown in FIG. 1 will be described with reference to FIG.
[0085]
The circuit shown in FIG. 6 is a flip-flop that incorporates an AND gate. That is, the flip-flop shown in FIG. 6 is a circuit in which the AND gate connected to the preceding stage of each flip-flop shown in FIG. 1 is omitted.
[0086]
However, the write signal G shown in FIG. 1 uses a complementary signal in FIG. 6 (for example, the write signal G is generated by inverting the write signal G with an inverter) and applied to the data output terminal Q. The output signal also uses a complementary signal.
[0087]
Further, in FIG. 6, a reset terminal inversion R corresponding to the reset terminal R of each flip-flop shown in FIG. 1 is used.
[0088]
The flip-flop circuit of FIG. 6 includes transistors M1 and M2, and includes a transfer gate 601 that transfers data applied to a data input terminal D in response to a write signal G (write signal inversion G), and transistors M3 and M4. A transfer gate 603 configured to transfer data applied to the data output terminal Q in response to the write signal G (write signal inversion G); transistors M10 and M12 to which a reset signal applied to the reset terminal inversion R is applied; It has transistors M5 and M11 to which a set signal applied to the set terminal S is applied. Further, the flip-flop circuit includes transistors M13 and M14, an inverter 605 whose input terminal is connected to the data output terminal inversion Q, and whose output terminal is connected to the data output terminal Q, and the data supplied to the data output terminal Q. Transistors M7 and M8 and transistors M6 and M9 to which outputs of the transfer gate 601 and the transfer gate 603 are applied.
[0089]
Next, the operation of the flip-flop circuit shown in FIG. 6 will be described.
[0090]
(Reset operation)
When an “L” level reset signal is applied to the reset terminal inversion R, the transistor M10 is turned on, so that the power supply potential (“H” level) is applied to the data output terminal inversion Q. When the data output terminal inversion Q becomes “H” level, the output of the inverter 605 becomes “L” level. On the other hand, since the transistor M12 is turned off, the path between the ground potential (“L” level) and the data output terminal inversion Q is electrically cut off. In this way, the data output terminal Q becomes “L” level and the flip-flop circuit is reset.
[0091]
(Operation that receives an interrupt request)
Next, an operation for receiving an interrupt request, that is, a set operation will be described.
[0092]
When an “H” level interrupt request signal is applied to the set terminal S, the transistor M11 is turned on, so that the drain potential of the transistor M12 is applied to the data output terminal inversion Q. At this time, if the reset terminal inversion R is at the “H” level, that is, if the reset operation is not being performed, the transistor M12 is on, so the drain potential of the transistor M12 is at the “L” level. Therefore, the data output terminal inversion Q becomes “L” level. The inverter 605 inverts the “L” level given to the data output terminal inversion Q and sets the data output terminal Q to the “H” level.
[0093]
On the other hand, since the transistor M5 is turned off, the path between the power supply potential and the data output terminal inversion Q is electrically cut off. If the reset operation is not being performed, the transistor M10 is turned off, so that any path between the power supply potential and the data output terminal inversion Q is electrically cut off.
[0094]
In this way, the data output terminal Q becomes “H” level and the flip-flop circuit is set. Therefore, this flip-flop circuit indicates that an interrupt request is generated in the peripheral circuit connected to this flip-flop circuit.
[0095]
(Operation to clear interrupt request)
Next, an operation to clear the interrupt request (data write operation), that is, an operation to transmit the data given to the data terminal D to the data output terminal Q and the inversion Q or hold the data given to the data output terminal Q and the inversion Q The operation to be performed will be described.
[0096]
First, the data when the data output terminal Q and the data output terminal inversion Q are at the “L” level and “H” level, respectively, that is, when no interrupt request is generated in the peripheral circuit connected to the flip-flop circuit. A write operation will be described.
[0097]
When the data output terminal Q is at the “L” level, the transistor M7 is turned on and the transistor M8 is turned off. At this time, if the set terminal S is at the “L” level (not in the set operation) and the reset terminal inversion R is at the “H” level (not in the reset operation), the transistor M5 is turned on, so the data output terminal The inversion Q becomes “H” level. The transistors M10 and M11 are off and the transistor M12 is on. Therefore, the “H” level is not transmitted through the transistor M10. Further, since the transistors M8 and M11 are off, the path between the ground potential and the data output terminal inversion Q is cut off, and the “L” level is not transmitted to the data output terminal inversion Q.
[0098]
Here, if the write signal G is at “L” level (the write signal inversion G is at “H” level), the transfer gate 601 is turned off and the transfer gate 603 is turned on. The L ″ level is transferred to the gates of the transistors M6 and M9. Then, in addition to the transistor M7 that has been turned on, the transistor M6 is also turned on, and the power supply potential is applied to the data output terminal inversion Q through the transistor M6.
[0099]
Next, when the write signal G changes to “H” level (the write signal inversion G is “L” level), the transfer gate 601 is turned on and the transfer gate 603 is turned off, so that the data input terminal D is now turned on. The given data is transferred to the gates of the transistors M6 and M9. Here, assuming that the data applied to the data input terminal D is at “L” level, the transistors M6 and M9 are in the previous state, that is, the write signal G is at “L” level (the write signal inversion G is at “H” level). It is the same as when it was. Therefore, the state of the data output terminal Q and the inversion Q does not change. (The flip-flop that was originally in the reset state does not change even if data 0 is written.)
On the other hand, if the data applied to the data input terminal D is at “H” level, the transistor M6 is turned off and the transistor M9 is turned on. However, since the transistor M8 is off, the “L” level is not transmitted to the data output terminal inversion Q even if the ground potential is transmitted to the drain of the transistor M9. Therefore, the state of the data output terminal Q and the inversion Q does not change.
[0100]
As described above, in the flip-flop circuit, when the data applied to the data output terminal Q is 0 and the data applied to the data output terminal inversion Q is 1, the data output terminal Q and the data output terminal inversion Q This is a circuit in which the data given to is not changed by the data given to the data input terminal D. That is, this flip-flop circuit is a circuit to which data 1 given from the outside is not written.
[0101]
Next, when the state of the data output terminal Q and the data output terminal inversion Q is “H” level and “L” level, respectively, that is, when an interrupt request is generated in the peripheral circuit connected to the flip-flop circuit. A data write operation will be described.
[0102]
When the data output terminal Q is at “H” level, the transistor M7 is turned off and the transistor M8 is turned on. Here, if the write signal G is at “L” level (the write signal inversion G is at “H” level), the transfer gate 601 is turned off and the transfer gate 603 is turned on. The H ″ level is transferred to the gates of the transistors M6 and M9. Then, the transistor M6 is turned off and the transistor M9 is turned on. At this time, if the set terminal S is at the “L” level (not in the set operation) and the reset terminal inversion R is at the “H” level (not in the reset operation), the transistors M5 and M12 are turned on. M10 and M11 are turned off. Therefore, the “L” level is transmitted to the data output terminal inversion Q through the transistors M8, M9, and M12. The “L” level applied to the data output terminal inversion Q is inverted by the inverter 605 and applied to the data output terminal Q. That is, the flip-flop circuit holds data 1.
[0103]
Next, when the write signal G changes to “H” level (the write signal inversion G is “L” level), the transfer gate 601 is turned on and the transfer gate 603 is turned off, so that the data input terminal D is now turned on. The given data is transferred to the gates of the transistors M6 and M9. Here, when the data applied to the data input terminal D is at “L” level, the transistor M6 changes from OFF to ON, and the transistor M9 changes from ON to OFF. Therefore, the power supply potential is transmitted to the data output terminal inversion Q through the transistors M5 and M6. The inverter 605 inverts the level of the data output terminal inversion Q and sets the data output terminal Q to the “L” level. Since the transistor M9 is turned off, the path between the ground potential and the data output terminal inversion Q is electrically cut off.
[0104]
On the other hand, if the data applied to the data input terminal D is at “H” level, the transistor M6 is turned off and the transistor M9 is turned on. That is, the states of the transistors M6 and M9 are the same as when the write signal G is at the “L” level (the write signal inversion G is at the “H” level). Therefore, the state of the data output terminal Q and the inversion Q does not change. (The flip-flop that was originally in the set state does not change even if data 1 is written.)
In this way, this flip-flop circuit is only provided by giving 0 to the data input terminal D when the data given to the data output terminal Q is 1 and the data given to the data output terminal inversion Q is 0. The circuit can change the state of the data output terminal Q.
[0105]
Based on the above write operation, data 0 is written only to the flip-flop circuit to be cleared, and data 1 is written to the flip-flop circuit that is not to be cleared, thereby clearing the interrupt request for only the flip-flop circuit to be cleared. The action can be performed.
[0106]
The flip-flop circuit shown in FIG. 6 can realize the same operation as the circuit composed of the flip-flop and the AND gate shown in FIG. 1 by adding the transistors M7 and M8. Specifically, the flip-flop circuit shown in FIG. 6 can reduce the number of MOS transistors by four compared with the circuit of FIG. 1 in order to realize the same operation as the circuit of FIG. Therefore, an interrupt request circuit having a small circuit area can be provided when integrated into an IC.
[0107]
Next, a modification of the interrupt request circuit shown in FIG. 4 will be described with reference to FIG.
[0108]
The circuit shown in FIG. 7 is a flip-flop in which an OR gate is incorporated. That is, the flip-flop shown in FIG. 7 is a circuit in which the OR gate connected to the preceding stage of each flip-flop shown in FIG. 4 is omitted.
[0109]
However, the write signal G shown in FIG. 4 uses a complementary signal in FIG. 7 (for example, the write signal G is inverted by inverting the write signal G with an inverter), and is applied to the data output terminal Q. The output signal also uses a complementary signal.
[0110]
In FIG. 7, the reset terminal inversion R corresponding to the reset terminal R of each flip-flop shown in FIG. 4 is used.
[0111]
The difference in configuration between the flip-flop circuit shown in FIG. 7 and the flip-flop circuit shown in FIG. 6 is only the connection relationship between the transistors M7 and M8. In the flip-flop circuit shown in FIG. 6, the transistor M6 and the transistor M7 are connected in parallel, whereas in the flip-flop circuit shown in FIG. 7, they are connected in series. In the flip-flop circuit shown in FIG. 6, the transistors M8 and M9 are connected in series, whereas in the flip-flop circuit shown in FIG. 7, they are connected in parallel.
[0112]
Next, the operation of the flip-flop circuit shown in FIG. 7 will be described.
[0113]
The reset operation and set operation of this flip-flop circuit are the same as those of the flip-flop circuit shown in FIG.
[0114]
(Operation to clear interrupt request)
Next, an operation to clear the interrupt request (data write operation), that is, an operation to transmit the data given to the data terminal D to the data output terminal Q and the inversion Q or hold the data given to the data output terminal Q and the inversion Q The operation to be performed will be described.
[0115]
First, data when the data output terminal Q and the data output terminal inversion Q are at the “L” level and “H” level, respectively, that is, when an interrupt request is generated in the peripheral circuit connected to the flip-flop circuit. A write operation will be described.
[0116]
When the data output terminal Q is at the “L” level, the transistor M7 is turned on and the transistor M8 is turned off. Here, if the write signal G is at “L” level (the write signal inversion G is at “H” level), the transfer gate 601 is turned off and the transfer gate 603 is turned on. The L ″ level is transferred to the gates of the transistors M6 and M9, the transistor M6 is turned on, and the transistor M9 is turned off. At this time, if the set terminal S is at the “L” level (not in the set operation) and the reset terminal inversion R is in the “H” level (not in the reset operation), the transistor M5 is turned on. Therefore, the data output terminal inversion Q becomes “H” level through the transistors M5, M6, and M7. This “H” level applied to the data output terminal inversion Q is inverted by the inverter 605 and applied to the data output terminal Q. The transistors M10 and M11 are off and the transistor M12 is on. Accordingly, the “H” level is not transmitted to the data output terminal inversion Q through the transistor M10. Further, since the transistors M8 and M11 are off, the path between the ground potential and the data output terminal inversion Q is cut off, and the “L” level is not transmitted to the data output terminal inversion Q.
[0117]
Next, when the write signal G changes to “H” level (the write signal inversion G is “L” level), the transfer gate 601 is turned on and the transfer gate 603 is turned off, so that the data input terminal D is now turned on. The given data is transferred to the gates of the transistors M6 and M9. Here, assuming that the data applied to the data input terminal D is at “L” level, the transistors M6 and M9 are in the previous state, that is, the write signal G is at “L” level (the write signal inversion G is at “H” level). It is the same as when it was. Therefore, the state of the data output terminal Q and the inversion Q does not change.
[0118]
On the other hand, if the data applied to the data input terminal D is at “H” level, the transistor M6 is turned off and the transistor M9 is turned on. Accordingly, the “L” level is transmitted to the data output terminal inversion Q through the transistors M9 and M12. The inverter 605 inverts the “L” level given to the data output terminal inversion Q and sets the data output terminal Q to the “H” level.
[0119]
Next, when the data output terminal Q and the data output terminal inversion Q are at the “H” level and “L” level, respectively, that is, when an interrupt request is not generated in the peripheral circuit connected to the flip-flop circuit. A data write operation will be described.
[0120]
When the data output terminal Q is at “H” level, the transistor M7 is turned off and the transistor M8 is turned on. Here, if the write signal G is at “L” level (the write signal inversion G is at “H” level), the transfer gate 601 is turned off and the transfer gate 603 is turned on. The H ″ level is transferred to the gates of the transistors M6 and M9, the transistor M6 is turned off, and the transistor M9 is turned on. At this time, if the set terminal S is at the “L” level (not in the set operation) and the reset terminal inversion R is at the “H” level (not in the reset operation), the transistor M12 is turned on. Therefore, the data output terminal inversion Q becomes “L” level through the transistors M8, M9 and M12. The inverter 605 inverts the “L” level given to the data output terminal inversion Q and sets the data output terminal Q to the “H” level. Transistors M10 and M11 are off. Accordingly, the “H” level is not transmitted to the data output terminal inversion Q through the transistor M10.
[0121]
Next, when the write signal G changes to “H” level (the write signal inversion G is “L” level), the transfer gate 601 is turned on and the transfer gate 603 is turned off, so that the data input terminal D is now turned on. The given data is transferred to the gates of the transistors M6 and M9. Here, when the data applied to the data input terminal D is at “L” level, the transistor M6 changes from OFF to ON, and the transistor M9 changes from ON to OFF. However, since the transistor M7 is off, the “H” level is not transmitted to the data output terminal inversion Q.
[0122]
On the other hand, if the data applied to the data input terminal D is at “H” level, the transistors M6 and M9 are in the previous state, that is, the write signal G is at “L” level (the write signal inversion G is “H”). The level is the same as when it was). Therefore, the state of the data output terminal Q and the inversion Q does not change.
[0123]
In this way, this flip-flop circuit is only provided by giving 1 to the data input terminal D when the data given to the data output terminal Q is 0 and the data given to the data output terminal inversion Q is 1. The circuit can change the state of the data output terminal Q.
[0124]
Based on the above write operation, data 1 is written only to the flip-flop circuit to be cleared, and data 0 is written to the flip-flop circuit that is not to be cleared, thereby clearing the interrupt request for only the flip-flop circuit to be cleared. The action can be performed.
[0125]
The flip-flop circuit shown in FIG. 7 can realize the same operation as the circuit composed of the flip-flop and the OR gate shown in FIG. 4 by adding the transistors M7 and M8. Specifically, the flip-flop circuit shown in FIG. 7 can reduce the number of MOS transistors by four compared to the circuit of FIG. 4 in order to realize the same operation as the circuit of FIG. Therefore, an interrupt request circuit having a small circuit area can be provided when integrated into an IC.
[0126]
【The invention's effect】
As described in detail above, the interrupt request processing method according to the present invention provides the first data to the first input terminal and maintains the interrupt request output given to the output terminal corresponding to the first input terminal. Since the second data is given to the first input terminal and the interrupt request output given to the output terminal corresponding to the first input terminal is cleared, the interrupt request to the CPU Even if multiple occurrences occur asynchronously, it is possible to reliably execute processing related to an interrupt request that occurs later.
[0127]
The interrupt request circuit according to the present invention corresponds to each of a plurality of bus lines for transferring data, a plurality of first input terminals for receiving data transferred to the bus lines, Since there are a plurality of second input terminals to which an interrupt request signal is applied corresponding to each of the bus lines and a plurality of output terminals corresponding to each of the second input terminals, the interrupt request circuit indicated by the interrupt request circuit The clear operation can be executed by data transferred to the data bus. That is, according to the present invention, since a dedicated circuit such as an interrupt clear selector is not required, interrupt processing can be reliably executed without increasing the circuit scale of the entire system.
[Brief description of the drawings]
FIG. 1 is a diagram showing an embodiment of an interrupt request circuit according to the present invention.
FIG. 2 is a diagram showing an embodiment of a system incorporating an interrupt request circuit according to the present invention.
FIG. 3 is a time chart for explaining the operation of the interrupt request circuit of the present invention shown in FIGS. 1 and 2;
FIG. 4 is a diagram showing another embodiment of the interrupt request circuit according to the present invention.
5 is a time chart for explaining the operation of the interrupt request circuit of the present invention shown in FIGS. 2 and 4. FIG.
FIG. 6 is a diagram showing a modification of the flip-flop of the interrupt request circuit according to the present invention.
FIG. 7 is a diagram showing a modification of the flip-flop of the interrupt request circuit according to the present invention.
[Explanation of symbols]
101, 103, 105, 107, 109 flip-flop
111, 113, 115, 117, 119 Andgate
137, 139, 141, 143, 145 Interrupt request input terminals
147, 149, 151, 153, 155 Data input terminals
157, 159, 161, 163, 165 Data output terminal

Claims (6)

In response to the interrupt request signal, the first data indicating that there is an interrupt request is held, and the held first data is output to the interrupt request output circuit. Circuit,
A bus line to which a plurality of bit data including second and third data having different logics are provided ;
A plurality of logic circuits to which the first data output from the data holding circuit and the second or third data given to the bus line are input;
The logic circuit outputs data for maintaining the first data held by the data holding circuit in response to the first data and the second data to the data holding circuit,
And an interrupt request circuit for outputting data for clearing the first data held by the data holding circuit to the data holding circuit in response to the first data and the third data. .   2. The interrupt request circuit according to claim 1, wherein the logic level of the first data and the second data is 1, and the logic level of the third data is 0.   3. The interrupt request circuit according to claim 1, wherein the logic circuit is an AND gate. In response to the interrupt request signal, the first data indicating that there is an interrupt request is held, and the held first data is output to the interrupt request output circuit. Circuit,
A bus line to which a plurality of bit data including second and third data having different logics are provided ;
An interrupt request circuit having a plurality of logic circuits to which the first data output from the data holding circuit and the second or third data given to the bus line are input is used. In the interrupt request processing method
A first step of giving an interrupt request signal to the predetermined data holding circuit and storing the first data in the data holding circuit;
The logic circuit outputs data for maintaining the first data held by the data holding circuit in response to the first data and the second data to the data holding circuit, and And a second step of outputting data for clearing the first data held by the data holding circuit to the data holding circuit in response to the first data and the third data. How to handle interrupt requests. In an interrupt request circuit comprising a plurality of data holding circuits for holding first data indicating that an interrupt request is generated in response to an interrupt request signal and outputting the data to a central processing unit ,
A bus line to which a plurality of bit data including second and third data having different logics output from the central processing unit is provided ;
A plurality of logic circuits to which the first data output from the data holding circuit and the second or third data given to the bus line are input;
The central processing unit stores third data in the logic circuit corresponding to the data holding circuit for which the interrupt processing related to the held first data has been completed, and all the data except the data holding circuit. The logic circuit corresponding to the data holding circuit outputs bit data that gives second data, and
The logic circuit outputs, to the data holding circuit, data that maintains the first data held by the data holding circuit in response to the first data and the second data, An interrupt request circuit that outputs data for clearing the first data held by the data holding circuit to the data holding circuit in response to data and the third data.   6. The first data held in the data holding circuit is cleared according to an output of the logic circuit when a write signal output from a central processing unit is given. The interrupt request circuit described.

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