JP3584566B2 - Data error correction device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a data error correction device for performing error detection and correction of data read from a recording medium, and particularly has a feature in memory access of data read from a CD-ROM.
[0002]
[Prior art]
In recent years, CD-ROMs of high-density, high-quality digital storage devices have rapidly spread, and CD-ROM devices have been required to operate at higher speeds. Hereinafter, a conventional CD-ROM signal processing device will be described.
FIG. 6 shows a conventional CD-ROM signal processing device. In FIG. 6, reference numeral 61 denotes a cross-interleave read-solomon code (CIRC) -IC for performing error correction processing on CD-ROM data. 62 is a control microcomputer, 63 is a host computer, 64 is a memory, 65 is a CD-ROM signal processing device, 651 is a CIRC interface block that captures CD-ROM data and an erasure flag output from the CIRC-IC 61, and 652 is a CIRC An error correction block for correcting and detecting errors in CD-ROM data that could not be corrected by the IC 61; 653, a host interface block for transferring data subjected to predetermined digital signal processing to a host computer; 654, CD-ROM signal processing It is configured by a memory interface block that controls a memory 64 connected to the device 65.
[0003]
The operation of the CD-ROM signal processing device configured as described above will be described below. First, the CIRC interface block 651 detects synchronization of CD-ROM data at an interface with the CIRC-IC 61, performs predetermined digital processing (descrambling of CD-ROM data), and then performs CD-ROM data Then, the erasure flag is written into a predetermined memory space of the memory 64 via the memory interface block 654 in a predetermined format.
[0004]
The error correction block 652 reads the CD-ROM data written in the memory 64 in the above-described processing through the memory interface block 654 a preset number of times, performs error correction on the data, and performs error correction. Error detection is performed on the data of. The host interface block 653 reads out the data written in the memory 64 by performing the above-described processing through the memory interface block 654 and transfers the data to the host computer 63 or transfers the data input from the host computer 63 to the memory interface block 654. Write to memory via
[0005]
[Problems to be solved by the invention]
However, in the above-described conventional configuration, access to the memory is becoming overcrowded as the speed of the CD-ROM device increases. For this reason, data to be sent to the host computer cannot be read at a sufficiently high speed, and it is difficult to maintain the data transfer speed.
[0006]
The present invention is intended to solve the above-mentioned conventional problems, and realizes more efficient signal processing by performing control to automatically change the number of error corrections according to the presence or absence of a data error in a block unit. It is an object of the present invention to provide a data error correction device capable of performing such operations.
[0007]
[Means for Solving the Problems]
In order to achieve this object, a data error correction device of the present invention sequentially writes reconstructed data into a memory for each predetermined unit block, and simultaneously executes an error included in the reconstructed data in parallel with the writing operation. Detecting the presence or absence of an error in each unit block of the reconstructed data using a detection code, and if there is no error in the unit block of the reconstructed data , reduce the number of corrections less than a preset number of corrections. When there is an error in a block, a configuration in which error correction of a data signal read out again from the memory is performed by a correction frequency control unit that controls an error correction unit to perform error correction by the preset correction frequency. have.
[0008]
[Action]
With this configuration, error detection of each block of CD-ROM data is performed in parallel with writing of the CD-ROM data to the memory, and the number of times of error correction of the CD-ROM data is set according to the detection result. The memory access time for the correction operation can be reduced.
[0009]
【Example】
An embodiment in which the error correction device of the present invention is applied to a CD-ROM signal processing system will be described below with reference to the drawings. In FIG. 1, reference numeral 11 denotes a CIRC-IC, 12 denotes a control microcomputer, 13 denotes a host computer, 14 denotes a memory, 15 denotes a CD-ROM signal processing device, 151 denotes a CIRC interface block, and 152 denotes real-time when CD-ROM data is fetched. An error detection block 153 for detecting an error and storing a detection result, 153 is an error correction block for performing error correction and error detection of CD-ROM data written in the memory, and 154 is a host for exchanging data with a host computer. An interface block 155 is a memory interface block for the CD-ROM signal processing device 15 to exchange data with the memory 12.
[0010]
FIG. 2 is a block diagram showing how the CD-ROM data output from the CIRC-IC 11 is processed by the error detection block 152. Reference numeral 211 denotes a serial-to-parallel conversion circuit for CD-ROM data. Is a descramble circuit for CD-ROM data, 213 is a FIFO memory for writing CD-ROM data to the memory 14, 214 is a synchronization detection circuit for detecting a synchronization pattern of CD-ROM data, 221 is an error detection circuit, Reference numeral 222 denotes an error detection result storage register for storing an error detection result.
[0011]
FIG. 3 is a diagram showing the error detection block 152 and the error correction block 153 in detail. Reference numeral 311 denotes an error correction circuit. Reference numeral 312 denotes an error correction circuit based on the value of a register 222 storing the error detection result in the error detection block 152. A correction number control circuit 313 for controlling 311 is an error detection circuit for checking whether or not the data after error correction has an error.
[0012]
The operation of the CD-ROM signal processing device configured as described above will be described with reference to FIGS. First, the CD-ROM data is data of 2352 bytes in one block which is serially output from the CIRC-IC 11 and has a format shown in FIG. 4, and data other than the synchronization pattern of 12 bytes is scrambled. . The CIRC interface block 151 takes in the CD-ROM data output from the CIRC-IC 11 into the serial / parallel conversion circuit 211, converts the data into 16-bit parallel data, and outputs it to the descramble circuit 212 and the synchronization detection circuit 214. The descrambling circuit 212 descrambles the CD-ROM data output from the serial / parallel conversion circuit 211 in units of 16 bits and outputs the data to the FIFO 213 and the error detection circuit 221.
[0013]
The synchronization detection circuit 214 detects the 12-byte synchronization pattern shown in FIG. 4 and generates a synchronization signal for a data block of 2352 bytes of CD-ROM data. This synchronization signal is output to the error detection circuit 221 and the error detection result. Output to the storage register 222. The FIFO 213 writes the data output from the descrambling circuit 212 into the memory 14 via the memory interface block 155 in 8-bit units. The error detection circuit 221 processes the data output from the descrambling circuit 212 in units of 16 bits, and outputs the result of error detection to the error detection result storage register 222 in units of one block of CD-ROM data.
[0014]
Further, since the data format of the CD-ROM data differs depending on the mode and form as shown in FIGS. 4A and 4B, the error detection circuit 221 detects the mode and form of the CD-ROM data, and Is configured to perform error detection according to the above. The FIFO memory 213 and the error detection circuit 221 operate in parallel, and the result of the error detection for one block of CD-ROM data indicates that the writing of the CD-ROM data of that block from the CIRC-IC 11 to the memory is completed. The data is written to the error detection result storage register 222, and the value of this register is decoded by the error correction block 153.
[0015]
The error correction circuit 311 capable of controlling the number of corrections by the number-of-corrections control circuit 312 writes the CD-ROM data output from the CIRC-IC 11 into the memory 14 via the CIRC interface block 151 and the memory interface 155. The CD-ROM data is read, and the syndrome calculation of P and Q is performed to calculate the error position and error pattern of the erroneous data. If there is no error in the data as a result of the syndrome calculation, the error correction processing ends. If there is an error, the erroneous data is read from the memory 14 via the memory interface block 155, the data is corrected, and the corrected data is overwritten on the address having the erroneous data via the memory interface block 155. I do.
[0016]
The number-of-corrections control circuit 312 reads the value of the error detection result storage register 222 and corrects the data determined to be error-free so that the number of times of error correction processing is smaller than the number of corrections set by the control microcomputer 12. An instruction is issued to the correction circuit 311 to reduce the memory access of the error correction circuit 311. The value of the error detection result storage register 222 is read, and for the data determined to have an error, the error correction circuit 221 is instructed to perform the error correction processing by the number of corrections set by the control microcomputer 12. put out.
[0017]
FIG. 5 shows the error detection result register and the number-of-corrections control circuit described above. In FIG. 5, the detection result output from the error detection circuit 221 in the error detection block 152 is latched by the latch circuit 511 in the error detection result storage register 222 with the synchronization signal of the CD-ROM data output from the synchronization detection circuit 214. I do. A signal output from the latch circuit 511 and a signal “PQ1X2” for setting the number of corrections by the microcomputer are input to the OR gate 513. If the output signal of the OR gate 513 is “1”, error correction is performed once and “0” is output. ", Error correction is performed twice. The NOR gate 512 is inserted to select whether to perform error correction for the number of times set by the microcomputer regardless of the result of the error detection circuit 221 or to control the number of corrections based on the result of the error detection circuit 221. If the signal "ECCADD" set by the microcomputer is "1", error correction is performed the number of times set by the microcomputer, and if "0", a signal for controlling the number of error corrections is output based on the result of the error detection circuit 221. . The error detection circuit 313 reads, via the memory interface block 155, the data on which the above-described error correction processing has been completed, and checks whether or not the data after the error correction processing has an error.
[0018]
Since the host interface block 154 can reduce the memory access of the error correction block 153 by the above-described error correction processing, the memory access for data transfer to the host computer can be increased.
[0019]
【The invention's effect】
As described above, the present invention reduces the number of error corrections when the number of errors in data in a unit block is small by controlling the number of corrections of an error correction block based on the result of error detection in parallel with data capture. When there are many errors, by increasing the number of error corrections, the memory access time can be reduced as a whole, and the memory access time for data transfer to a host computer or the like can be increased. In a system, an excellent data error correction device capable of high-speed transfer can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment in which an error correction device of the present invention is applied to a CD-ROM signal processing system. FIG. 2 is a detailed block diagram of a CIRC interface block and an error detection block in the embodiment. FIG. 3 is a detailed block diagram of an error detection block and an error correction block in the embodiment. FIG. 4 is a diagram showing a data format of a data block in the embodiment. Peripheral block diagram [FIG. 6] A block diagram in a case where a conventional error correction device is applied to a CD-ROM signal processing system.
11, 61 CIRC-IC
15, 65 CD-ROM signal processing system 14, 64 memory 13, 63 host computer 151, 651 CIRC interface block 152 error detection block 153, 652 error correction block 155, 654 memory interface block 222 error detection result storage register 311 error correction circuit 312 Error correction frequency control circuit

Claims (1)

The digital data signal to be corrected read from the recording medium is subjected to predetermined digital signal processing and reconstructed data is sequentially written into a memory for each predetermined unit block, and in parallel with the write operation, the reconstructed data is rewritten. The presence or absence of an error in each unit block of the reconstructed data is detected using an error detection code included in the data , and if there is no error in the unit block of the reconstructed data , the number of corrections is set based on a preset number of corrections. If there is an error in the unit block, the correction number control means for controlling the error correction means so as to perform error correction by the preset number of corrections, the correction of the data signal read from the memory again. A data error correction device for a digital signal, which performs error correction.

Images