JP2814980B2 - Cell buffer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell buffer control system, and more particularly to an ATM (Asynchronous T).
The present invention relates to a cell buffer control method used for performing ATM cell multiplexing / demultiplexing, speed conversion, and signal format conversion in a transfer mode (asynchronous transfer mode) communication device.

[0002]

2. Description of the Related Art Conventionally, a cell buffer control circuit used for performing ATM cell multiplexing / demultiplexing, speed conversion, and signal format conversion in an ATM communication apparatus simply includes a FIFO (First In First Out) memory. The buffer writing and reading control is performed using a FULL flag signal of a FIFO indicating that the memory is full and an EMPTY flag signal indicating that the memory is empty.

FIG. 2 is a block diagram showing an example of a conventional cell buffer control circuit.

As shown in FIG. 2, a conventional cell buffer control circuit includes a plurality (N) of FIFO memories 101 for storing ATM cell data and a write control for controlling writing of cell data to the FIFO memory 101. It comprises a control circuit 102 and a read control circuit 103 for performing read control.

When writing cell data to the FIFO memory 101, the write control circuit 102 checks whether there is an empty memory space in the FIFO memory 101 or not.
Upon receiving the FULL flag output signal which is the control terminal of the O memory 101 and collating it, if it is found that there is free memory space, the data word is given to the data input IN of the FIFO memory 101 and the write enable signal WREN is generated.
Data writing to the FIFO memory 101 is continued until there is no free memory space.

When reading cell data from the FIFO memory 101, the read control circuit 103 checks the EMPTY flag output signal of the FIFO memory 101 before reading, and if the existence of data in the memory is confirmed, the read control circuit 103 reads
The control is performed such that the read permission signal RDEN is generated until the data in the IFO memory 101 becomes empty, and the cell data is continuously read.

[0007]

Since the ATM cell has a fixed length, write and read control of the FIFO memory is performed in units of cell data. When a failure such as a dropout occurs, a portion of the cell data may drop out and be written to the FIFO memory, or extra data may be written to the FIFO memory between a certain cell and the next cell. At this time, the cell is not read out from the head of the cell.

In the conventional method, when this state occurs, even if the device recovers normally, there is a problem in that the data shifted once at the time of writing or reading is not recovered, and the shifted cell data continues to be output. there were.

The reason is that the cell buffer control circuit of the ATM cell does not have means for detecting whether or not the reading process is normally performed from the cell head position and restoring to the normal state.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a cell buffer for detecting an abnormal state in which there is some abnormality in a device and which continues to be output with a shift, and recovers to a state in which the cell is normally read from the head. It is intended to provide a control method.

[0011]

According to the present invention, in order to achieve the above object, a cell buffer control circuit for an ATM cell stores a signal (cell pulse signal) indicating the head of the ATM cell together with cell data. One bit is added to perform writing / reading of a cell pulse signal, and write / read control of the buffer is performed by using an up / down counter for managing ATM cells in the buffer. A means for resetting the FIFO memory and the up / down counter when a signal is not read is provided.

When an error occurs in the device due to a missing clock or the like during the write / read control of the FIFO memory in the cell buffer control circuit of the ATM cell, the head position of the cell data deviates from the main signal cell data. In some cases, writing / reading cannot be performed in cell units from the head of the cell. To detect this abnormal state, F
When reading control of the FIFO memory is performed, the presence or absence of a cell pulse signal indicating the head position of the cell data is determined first after reading is started, and the FIFO memory is reset based on the determination result. As a result, it is possible to prevent output of cell data that is shifted from the head of the cell even after recovery from the failure of the device, and to restore data to a state in which data is read from the head of the cell in cell units after recovery from the failure. Can be.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment to which a cell buffer control system according to the present invention is applied.

According to the present invention, as shown in FIG. 1, a plurality (N) of FIFO memories 1 for storing ATM cell data,
Has a write enable signal generation circuit 21 and a FIFO for cell data
A write control circuit 2 for performing write control on the memory 1, a read control circuit 3 having a leading phase determination circuit 31 and a read permission signal generation circuit 32, and performing read control of cell data from the FIFO memory 1; And a cell counter 4 for managing the number of cells in the memory 1.

The write control circuit 2 includes a write enable signal generation circuit 2
The write enable signal generation circuit 21 receives a cell pulse signal indicating the beginning of cell data, and writes a 1-bit cell pulse signal to a plurality of FIFO memories 1 together with one cell of ATM cell data. And determine
The write enable signal WREN is generated and output to the FIFO memory 1. When the writing of data for one cell is completed, a one-cell write completion signal CWEP for counting up the cell counter 4 that manages the number of cells in the FIFO memory 1 is transmitted to the cell counter 4.

The read control circuit 3 comprises a read permission signal generation circuit 32 and a leading phase determination circuit 31.

The read permission signal generating circuit 32 receives a counter value indicating the number of cells stored in the FIFO memory 1 output from the cell counter 4 and determines that one or more cell data has been stored in the FIFO memory 1. FIF when recognized
A read permission signal RDEN is sent to the O memory 1 and 1
The 1-bit cell pulse signal written in the memory is read together with the ATM cell data for the cells. FIFO
When data reading for one cell in the memory 1 is completed, a one-cell reading completion signal CREP for counting down the cell counter 4 is sent to the cell counter 4.
Further, the read permission signal generation circuit 32 generates a reference phase signal serving as a timing of cell data head read when transmitting the read permission signal RDEN to the FIFO memory 1, and outputs the reference phase signal to the head phase determination circuit 31.

The leading phase judging circuit 31 comprises a leading phase comparing circuit 33 and a reset signal generating circuit 34.

In the leading phase comparison circuit 33, a plurality of FIFs
A phase comparison is made between the cell pulse signal read from the O memory 1 and the reference phase signal indicating the read start position received from the read permission signal generation circuit 32, and whether the phase of the cell pulse signal and the phase of the reference phase signal are all the same. A comparison is made to determine whether or not the determination is affirmative, and the determination result is output to the reset signal generation circuit 34.

The reset signal generation circuit 34 performs a reset process of the FIFO memory 1 based on the determination result received from the leading phase comparison circuit 33. The phase of the reference phase signal and F
If any one of the phases of the cell pulse signal read from the IFO memory 1 does not match, it means that the ATM cell has not been correctly read from the head position, and it is detected that an abnormal state has occurred. In this case, A
A reset signal RST for resetting the FIFO memory 1 storing the TM cell data is generated and output.

The EMPTY flag of the FIFO memory 1 is connected to the reset terminal of the cell counter 4,
When the cell data stored in the FIFO memory 1 becomes empty by the reset processing of the O memory 1 and the EMPTY flag of the FIFO memory 1 becomes active,
The cell counter 4 is reset, and the counter value is initialized to “0”.

By this reset processing, the write control or the read control to the FIFO memory 1 is restored from the abnormal state to the normal state, and the data read after the ATM cell is normally written from the head position is shifted to the head phase. It is possible to restore a state in which normal data is read from the head position of the cell in a unit of cell, instead of the data that remains shifted.

The cell counter 4 has a function of managing the number of cells in the FIFO memory 1, and is composed of an up / down counter. The cell counter 4 counts up by a one-cell write completion signal CWEP input from the write control circuit 2 and counts down by a one-cell read completion signal CREP input from the read control circuit 3 to thereby store data in the FIFO memory 1. Is managed on a cell-by-cell basis. Further, the counter value is sent to the read control circuit 3 as the number of storage cells in the FIFO memory 1, and when the counter value is “0”, the read control circuit 3
Is prohibited, and when the counter value is "1" or more, F
A read permission signal RDEN for the FIFO memory 1 is output to the FIFO memory 1. The cell counter 4 receives the EMPTY flag signal from the FIFO memory 1, and resets the cell counter when the FIFO memory 1 becomes empty,
It has a function of initializing the counter value to “0”.

In the above-described embodiment, the phase of the cell pulse signal read from the plurality of FIFO memories 1 and the reference phase signal received from the read permission signal generation circuit 32 and indicating the read start position are read by the leading phase comparison circuit 33. Make a comparison,
Although it is determined whether or not the phase of the cell pulse signal and the phase of the reference phase signal are all the same, the present invention is not limited to this, and when reading the ATM cell from the FIFO memory 1, the reading is performed. When the cell pulse signal is not read first after the start, it may be detected that the reading of the ATM cell from the FIFO memory 1 is shifted from the cell head.

[0026]

As described above, according to the cell buffer control method of the present invention, in the cell buffer control method of writing ATM cells from the beginning of the cell and reading from the beginning of the cell, when a failure such as a clock drop occurs. In this state, the data whose cell data start position is shifted does not continue to be output after the recovery from the failure, and the data is read from the head position of the cell normally in cell units after the recovery from the failure. There is an effect that it can be restored.

The reason is that a bit for storing a cell pulse signal indicating the head position of the cell together with the main signal cell data is added by one bit, and an up / down counter for counting the number of ATM cells in the FIFO memory is provided.
The number of ATM cells stored in the O memory is managed, and write / read control of the FIFO memory is performed on a cell basis.
This is because a means for resetting the FIFO memory and the up / down counter when the cell pulse signal read from the memory is not read first is provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment to which a cell buffer control system according to the present invention is applied.

FIG. 2 is a block diagram of an example of a conventional cell buffer control circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 FIFO memory 2 write control circuit 3 read control circuit 4 cell counter 21 write enable signal generation circuit 31 start phase determination circuit 32 read enable signal generation circuit 33 start phase comparison circuit 34 reset signal generation circuit

Claims (8)

(57) [Claims] 1. A cell buffer control method for writing an ATM cell to a FIFO memory once, reading the ATM cell in a cell unit, and then outputting the read cell unit, wherein when writing the ATM cell to the FIFO memory, a cell pulse signal indicating a cell head position is output. When the ATM cell is stored in the FIFO memory and the ATM cell is read from the FIFO memory, the ATM cell from the FIFO memory is read when there is a phase shift between the reference phase signal, which is the read start timing, and the read timing of the cell pulse signal. A cell buffer control method for detecting that a cell read is shifted from the head of the cell. 2. A cell buffer control method in which an ATM cell is once written in a FIFO memory, read out in a cell unit, and then output. When writing an ATM cell in the FIFO memory, a cell pulse signal indicating a cell head position is supplied to the FIFO memory. When reading the ATM cell from the FIFO memory and reading the ATM cell from the FIFO memory, if the cell pulse signal is not read first after reading is started, the reading of the ATM cell from the FIFO memory is shifted from the cell head. A cell buffer control method characterized by detecting the presence of a cell buffer. 3. The method according to claim 1, wherein when the reading of the ATM cell from the FIFO memory is detected as being shifted from the head of the cell, the FIFO memory is reset to clear the contents of the FIFO memory. Item 3. The cell buffer control method according to item 1 or 2. 4. A cell counter for counting the number of ATM cells in the FIFO memory is reset when the reading of the ATM cells from the FIFO memory is detected as being shifted from the head of the cell. 4. The buffer control method according to claim 3, wherein the buffer is cleared to zero. 5. A cell buffer control circuit for temporarily writing an ATM cell to a FIFO memory, reading the ATM cell in a cell unit, and outputting the read out cell, wherein the FIFO memory is provided with a region for storing a cell pulse signal indicating a cell head position. Together with the cell pulse signal from the FIFO
Writing means for writing to a memory;
Reading means for reading from the memory; reference phase signal generating means for generating a reference phase signal at a timing of starting reading by the reading means; phase of the reference phase signal from the reference phase signal generating means;
Phase comparing means for comparing the phase of the read timing of the cell pulse signal with the reading means; and, if the phase is shifted as a result of the comparison by the phase comparing means, reading of the ATM cell from the FIFO memory is started at the cell top. A cell buffer control circuit, comprising: abnormality detection means for detecting an abnormality when the state is shifted from the state. 6. A cell buffer control circuit for temporarily writing an ATM cell to a FIFO memory, reading the ATM cell in units of cells, and outputting the readout cell, wherein the FIFO memory is provided with a region for storing a cell pulse signal indicating a cell head position. Together with the cell pulse signal from the FIFO
Writing means for writing to a memory;
Reading means for reading from a memory; and when reading by the reading means, if the cell pulse signal is not read first after reading is started,
A cell buffer control circuit comprising: abnormality detection means for detecting an abnormality when the reading of the ATM cell from the FO memory is shifted from the head of the cell. 7. The FIFO memory is reset to clear the contents of the FIFO memory when the abnormality detection means detects an abnormality that the reading of the ATM cell from the FIFO memory is shifted from the head of the cell. FI
7. The cell buffer control circuit according to claim 5, further comprising FO memory reset means. 8. A cell counter for counting the number of ATM cells in said FIFO memory, and said abnormality detecting means detecting an abnormality when reading of said ATM cells from said FIFO memory is out of the cell head. 8. The buffer control circuit according to claim 7, further comprising cell counter reset means for resetting the cell counter to clear the counter value to zero.