JP3011162B2 - Self-recovery method for address destruction and self-recovery device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-recovery method for address destruction , particularly in an ATM switch, and a self-recovery method thereof.
Belongs to the return device .

[0002]

2. Description of the Related Art A new transmission technology for realizing an ultra-high-speed network B-ISDN that handles various information media is called A.
There is a TM (Asynchronous Transfer Mode). This ATM divides information into fixed-length ATM cells and transmits the ATM cells.
It is composed of an M header and a 48-byte payload storing information.

The ATM switch has a function of allocating an ATM cell to a destination by looking at the header of the ATM cell. AT
The M switches are classified into an input buffer type ATM switch, an output buffer type ATM switch, and a shared buffer type ATM switch according to the achievement method. Here, a shared buffer type ATM switch will be described.

The transfer of data in such an ATM switch will be described with reference to the drawings.

The ATM switch includes a shared memory in which the memory is stored, a cell caller and a cell writer, a busy address storage and a read address determiner. The data structure between the cell caller and the cell writer is a write queue in which empty cells are stored. The data structure between the in-use address storage device and the read address determiner is a read queue in which cells storing data are stored.

In the exchange of data at the ATM switch, all information is decomposed into fixed-length cells (1 to N) and packed into a 48-byte information field. Each cell has a 5-byte header (label) indicating control information such as an address.

[0007]

However, in the above-described shared buffer type ATM switch, in the ring counter system in which an initially set address is transferred via a queue, an address being transferred may have a bit error. The address may be destructed by changing to a different address.

In such address destruction, when two specific addresses exist, another cell is erroneously read or a cell is lost. When the specific address no longer exists, a failure occurs in which the capacity of the shared address is reduced.

This fault does not recover until the operator returns to the initial value by pressing the reset button or the like.

Further, address destruction will be specifically described with reference to FIG. 1 to N in FIG.
(TM cell). In FIG. 3, data is stored in cells 2, 4, and 7 (cells with address numbers 2, 4, and 7) stored in shared memory 20. No data is stored in cells other than 2, 4, and 7 among cells 1 to N. The cells 2, 4, and 7 are stored in the read queue 24, and the other cells are stored in the write queue 23.

When cell 2 is read by read address determiner 26, cell 2 becomes empty due to a bit error or the like.
Is read incorrectly and stored in the shared memory 20, there are two cells 1. That is,
The empty cell 1 exists in the read queue 23, and the cell 1 to which data is written coexists in the read queue 24. In addition, the cell 2 that has been written exists in the shared memory 20, and the empty cell 2 also exists in the write queue 23. This is address destruction, and is conceptually indicated by reference numeral 30.

This state is not restored until the operator returns to the initial value by pressing the reset button or the like as described above. That is, the use is continued without resetting, and the address is destroyed until the reset.

The present invention has been made in view of the above problems, and has as its object to detect whether or not there is a failure as described above and, if a failure has occurred, to perform self-recovery. Address recovery method and address recovery
And a self-recovery device therefor.

[0014]

The invention according to claim 1 is a self-restoring method for address destruction in an ATM switch, wherein addresses 1 to N of cells stored in a shared memory are stored in the shared memory. By taking advantage of the fact that there is only one for each of the address of the cell in the connected write queue and the address of the cell in the read queue, the read queue and the write queue for transferring cells to and from the shared memory are used. Is compared with the number of cell addresses that can be stored in the shared memory, and if different, the ATM switch is initialized. The invention according to claim 2 is a method for
A self-restoring device for address destruction in a TM switch, comprising: an address generator for generating the same number of cells as can be stored in a shared memory; and an address FIFO for transferring cells to and from the shared memory. Address FIFO
And a match determiner that compares the number of cells within the address generator with the number generated from the address generator, and when they do not match, determines that the address is destructed and outputs an address destruction detection signal. Features. The invention according to claim 3 is
A self-recovery device for address destruction in an ATM switch, comprising: an address generator, a plurality of match determiners, a stop determiner, and a match number determiner, wherein the address generator is capable of storing cells in a shared memory. Produces the same number as the number,
Each of the coincidence determiners has an address FIFO for exchanging cells with the shared memory.
The number of cells in the address FIFO is compared with the number generated from the address generator, and when the addresses match, a match signal is output, and the number of cells in the address FIFO and the number generated from the address generator are output. When the numbers match, a comparison end signal is transmitted, and the stop determiner outputs the stop instruction upon receiving all the comparison end signals from a plurality of match determiners, and the match number determiner Between the stop instruction from the stop determiner and the immediately preceding stop instruction, the number of match signals from the plurality of match determiners is counted, and if the number is not 1, it is output as an address destruction detection signal. It is characterized by. The coincidence determiner determines whether or not the address from the address generator is present in the monitored address FIFO during a specific time. Address FIF for sending and receiving
O, an accumulation counter, a down counter, and an address comparator, wherein the address FIFO has a write address queue and a read queue, and the storage amount counter stores the monitored address FIFO. The down counter monitors the number of addresses that are present, and upon receiving a stop instruction from the stop determiner, loads the value of the accumulation counter at that time, adds -1 each time a cell is read, and stops when the value reaches 0. Output a comparison end signal to the decision unit,
The address comparator, while the down counter is not 0, each time a cell is read from the address FIFO, the address from the address generator and the address FI
The addresses existing in the FOs are compared, and if they match, a match signal is output to the match number determiner. An address destruction detection signal output from the address destruction detection device in the ATM switch is an AT destruction detection signal.
It can be a reset signal for the M switch.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described.
Will be explained. FIG. 1 shows the self-recovery of address destruction of the present invention.
Shared buffer type ATM switch according to an embodiment of the present invention
FIG. As shown in FIG. 1, an address generator 1, a stop determiner 3, a plurality of match determiners 4 and a match number determiner 2 are provided.

There are as many coincidence determiners 4 as the total number of read queues 23 and write queues 24 shown in FIG.
Each of them comprises an address FIFO 7, an accumulation counter 5, a down counter 6, and an address comparator 8.

The address FIFO 7 stores the read queue 2
3 and each FIFO of the plurality of write queues 24.

The address generator 1 is a shared memory 20 shown in FIG.
The counter arbitrarily generates the same number as the number N of addresses that can be stored, and counts up as 1 to N, for example.
The address generator 1 holds the same value K (1 to N) until the stop judging unit 3 gives a stop instruction. When the stop instruction is received, the value is changed to the next value. This address makes one round (1 to N), and detection of all address destruction is completed.

The stop judging unit 3 outputs a stop instruction when all the comparison end signal signals from the plurality of coincidence judging units 4 are received.

The coincidence number judging device 2 counts the number of coincidence signals from the plurality of coincidence judging devices 4 between the stop instruction from the stop judging device 3 and the immediately preceding stop instruction. , As an address destruction detection signal 9 to the reset means. .

The coincidence determiner 4 determines whether or not the address K (1 to N) from the address generator 1 exists in the monitored address FIFO 7 at a certain moment. 5 and down counter 6
And an address comparator 8.

The storage amount counter 5 constantly monitors the number of addresses (cells) stored in the monitored address FIFO 7. The down counter 6 loads the value of the accumulation counter 5 at the time of receiving the stop instruction of the stop judging device 3, adds −1 to the value every time the cell is read, and outputs a comparison end signal to the stop judging device 3 when it becomes 0. Output.

While the down counter 6 is not 0, the address comparator 8 stores the address from the address generator 1 and the address F each time a cell is read from the address FIFO 7.
The addresses from the IFOs 7 are compared, and if they are the same, a match signal is output to the match number determiner 2. If they do not match, no match signal is output.

Self recovery from address destruction according to the present embodiment
2 is that only one of the addresses 1 to N used by the supply buffer in FIG. 2 exists in the address (cell address) in the write queue 23 or the address in the read queue 24 (for example, the write queue 23). Address destruction is detected by utilizing the fact that 1 to K in 23 and K to N in the read queue 24).

In such a self-recovery method of address destruction,
With respect to the number N of addresses that can be stored in the shared memory 20 in FIG. 2, it is confirmed that the address 1 exists only in the addresses in the write queue 23, and then the address 2, address 3,... In this way, address destruction is detected.

Further, the self-recovery from the failure is performed by returning the shared buffer type ATM switch itself to the initial state based on the detection result.

FIG. 4 shows a flow of a method of detecting address destruction.

The address destruction is as described in the problem to be solved by the present invention.

In this embodiment, the present invention is applied to a shared memory type ATM switch. However, the present invention is not limited to this, and can be applied to a switch suitable for applying the present invention.

The number, position, shape, and the like of the above components are not limited to the above-described embodiment, but may be any number, position, shape, and the like suitable for carrying out the present invention.

In the drawings, the same components are denoted by the same reference numerals.

[0032]

Since the present invention is configured as described above, the following effects can be obtained. In the present invention, cells having the same address in the shared memory detect whether there is address destruction by utilizing that only one exists in either the write queue or the read queue,
Further, when address destruction occurs, self-recovery can be performed.

[Brief description of the drawings]

FIG. 1 shows a shared buffer type AT according to an embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an M switch.

FIG. 2 is a conceptual diagram showing data transfer in the shared buffer type ATM switch shown in FIG.

FIG. 3 is a conceptual diagram showing address destruction.

FIG. 4 is a flowchart illustrating a method for detecting address destruction.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Address generator 2 Matching number judging device 3 Stop judging device 4 Matching judging device 5 Accumulation amount counter 6 Down counter 7 Address queue 8 Address comparator 9 Judgment result 20 Shared memory 21 Input cell 22 Output cell 23 Write queue 24 Read queue 25 Cell writer 26 Address memory in use 27 Cell reader 28 Read address determiner 30 Address destruction

Claims (5)

(57) [Claims] 1. A self-restoring method for address destruction in an ATM switch, wherein addresses 1 to N of cells stored in a shared memory are read from an address of a cell in a write queue connected to the shared memory. Utilizing the fact that there is only one of each of the addresses in the queue, the number of addresses of the cells in the read queue and the write queue for exchanging cells with the shared memory; A self-recovery method for address destruction, characterized in that the number of cell addresses that can be stored is compared with the number of cells that can be stored, and if the numbers are different, the ATM switch is initialized. 2. An address destruction in an ATM switch.
A self-resetting device, address FI performing an address generator for generating the same number as the number of cells that can be stored in the shared memory, the cell exchange between the shared memory
FO, and compares the number of cells in the address FIFO with the number generated from the address generator. If they do not match, it is determined that the address is destructed and a match detection signal for outputting an address destruction is output. Self-recovery of address destruction in an ATM switch, characterized by comprising a judgment device.
apparatus. 3. The address destruction in an ATM switch.
A self-recovery device , comprising: an address generator, a plurality of match determiners, a stop determiner, and a match number determiner, wherein the address generator generates the same number as the number of cells that can be stored in the shared memory. Each of the coincidence determiners has an address FIFO for exchanging cells with the shared memory.
The number of cells in the address FIFO is compared with the number generated from the address generator, and when the addresses match, a match signal is output, and the number of cells in the address FIFO and the number generated from the address generator are output. When the numbers match, a comparison end signal is transmitted, and the stop determiner outputs the stop instruction when all the comparison end signals are received from the plurality of match determiners. The number of coincidence signals from the plurality of coincidence determiners is counted between the stop instruction from the stop determiner and the immediately preceding stop instruction, and if the number is not 1, it is output as a detection signal of address destruction. Characterized by the fact that
Self-recovery device for address destruction in ATM switch . 4. The coincidence judging device judges whether or not an address from the address generator exists in an address FIFO monitored during a specific time, and determines whether or not the address from the shared memory is present. , An address FIF for exchanging cells
O, an accumulation counter, a down counter, and an address comparator. The address FIFO has a write address queue and a read queue. The accumulation amount counter monitors the address FI being monitored.
The down counter monitors the number of addresses stored in the FO, and upon receiving a stop instruction from the stop determiner, loads the value of the storage counter at that time and adds -1 each time the cell is read. When it becomes 0, it outputs a comparison end signal to a stop judging device. The address comparator outputs an address from the address generator and an address FI each time a cell is read from the address FIFO while the down counter is not 0.
Comparing an address present in the FO, the case matching signal match and outputs the coincidence number determiner 請
The address destruction in the ATM switch according to claim 3
Self-recovery device. 5. The address destruction detection signal output from the address destruction detection device in the ATM switch according to any one of claims 2, 3 and 4 , is a reset signal of the ATM switch. , Address broken
Break self-recovery device.