JP2757904B2 - ATM cell format converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method in which an ATM cell (hereinafter, referred to as "cell") is inserted only into a payload portion of an SDH frame, and an ATM cell is inserted into a header portion and a payload portion of the SDH frame. AT to state
The present invention relates to an ATM cell format converter for converting the insertion state of M cells.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional ATM cell format conversion apparatus of this type includes a host device (not shown).
Input data 1 consisting of SDH frames sent from
And a write timing control circuit 3 for controlling the timing of writing cells in the buffer 2
A read timing control circuit 4 for controlling the timing of reading cells of the buffer 2;
And a buffer reset control circuit 5 for controlling the resetting.

The buffer 2 is supplied with input data 1 consisting of an SDH frame in which cells are inserted only in the payload portion, and shifts from a state in which cells are inserted only in the payload portion of the SDH frame to a header portion of the SDH frame. This is for converting the inserted state of the cell into a state where the cell is inserted in the payload portion. The writing of the input data 1 is controlled by a write timing control circuit 3. This write timing control circuit 3
Upon receiving the overhead display signal 6 of the SDH frame, the write cell head position display signal 7 of the SDH frame, and the reset signal 8 from the buffer reset control circuit 5, the write timing signal 9 is supplied to the buffer 2 when the input data 1 is written. .

The buffer reset control circuit 5 receives the initial reset signal 10 from the host device, generates a reset signal 8, and supplies the reset signal 8 to the buffer 2, the write timing control circuit 3, and the read timing control circuit 4.

The read timing control circuit 4 receives a read cell head position display signal 11 from a lower-level device (not shown), generates a read timing signal 12, and supplies the read timing signal 12 to the buffer 2. The buffer 2 outputs output data 13 when receiving the read timing signal 12.

Conventionally, this type of ATM cell format conversion apparatus resets a cell format conversion buffer 2 at the time of initial reset, and uses a head position display signal 7 of a first write cell on a cell writing side to store a buffer. Write the first bit of the cell to address 0 of address 2
Thereafter, the cell read side reads the data at the address 0 in the buffer 2 in accordance with the head position display signal 11 of the read cell, thereby performing the bit phase adjustment of the cell.

[0007]

However, in this type of conventional ATM cell format converter, when a malfunction occurs or a pseudo pulse is generated due to the mixing of noise, the cell is written or read. In this case, there is a problem that a bit shift occurs and excess data remains in the buffer.In addition, due to the residual data, a phase shift occurs between the write side and the read side data. There is a problem that self-reliance cannot be restored.

An object of the present invention is to provide an ATM cell format converter capable of autonomously recovering from a data interruption state when a bit shift occurs during writing or reading of a cell.

[0009]

According to the present invention, in order to solve the above-mentioned problems, an ATM cell is inserted into a header portion and a payload portion of an SDH frame from a state in which an ATM cell is inserted only into a payload portion of the SDH frame. In an ATM cell format converter for converting an inserted state of an ATM cell into an inserted state, a cell format conversion buffer for temporarily buffering an ATM cell, cell writing means for writing a cell to the buffer, A cell reading means for reading a cell from the buffer, wherein the cell writing means comprises: a vacant cell detection circuit for detecting a vacant cell having no data; and a cell monitor for detecting when the vacant cell detection circuit detects a vacant cell. A monitoring cell generating circuit for generating a monitoring cell having a monitoring pattern of A monitoring cell insertion circuit that inserts a monitoring cell from the monitoring cell generation circuit into the empty cell when a cell is detected; and a buffer reset control circuit that resets the buffer. A monitoring cell detection circuit for detecting the monitoring cell from output data read from the buffer; and a predetermined reference monitoring pattern in which a detection monitoring pattern of the detection monitoring cell detected by the monitoring cell detection circuit is generated by the monitoring cell generation circuit. And a monitoring pattern determining circuit that generates a bit shift signal when it does not match and determines that the bit shift signal does not match, and the buffer reset control circuit outputs a bit shift signal from the monitoring pattern determining circuit. The buffer is reset when received.

[0010]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The embodiment shown in FIG. 1 differs from the conventional ATM cell format converter shown in FIG.
4, a monitoring cell generation circuit 15, and a monitoring cell insertion circuit 16
, Monitoring cell detection circuit 17 and monitoring pattern determination circuit 1
8 is added.

The vacant cell detection circuit 14 detects a vacant cell having no data (user information) from the input data 1, generates a vacant cell presence signal 19, and supplies it to the monitor cell generation circuit 15. The monitoring cell generation circuit 15 receives the empty cell presence signal 19, generates a monitoring cell 20 having a monitoring monitoring pattern, and provides the monitoring cell 20 to the monitoring cell insertion circuit 16. The monitoring cell insertion circuit 16 receives the monitoring cell 20 and inserts the monitoring cell 20 into a vacant cell detected by the vacant cell detection circuit 14 to input the monitoring data with monitoring cell 21.
Is generated and given to the buffer 2.

The monitoring cell detection circuit 17 includes a buffer 2
The monitor cell is detected from the output data 13 read out from the memory cell, and a monitor cell presence signal 22 is generated and supplied to the monitor pattern determination circuit 18. This monitoring pattern determination circuit 18
Determines whether the detection monitoring pattern of the detection monitoring cell detected by the monitoring cell detection circuit 17 when receiving the monitoring cell presence signal 22 matches a predetermined reference monitoring pattern generated by the monitoring cell generation circuit 15. I do. The monitoring pattern determination circuit 18 generates a bit shift signal 23 when the detection monitoring pattern does not match the reference monitoring pattern, and supplies the bit shift signal 23 to the buffer reset control circuit 5.

The buffer reset control circuit 5 generates a reset signal 8 when receiving the bit shift signal 23 and supplies the reset signal 8 to the buffer 2, the write timing control circuit 3, and the read timing control circuit 4. When the monitoring pattern determination circuit 18 generates the bit shift signal 23, it means that a bit shift has occurred at the time of writing or reading the cell. In this case, the buffer reset control circuit 5 resets the buffer 2 At the same time, the reset signal 8 is given to the write timing control circuit 3 and the read timing control circuit 4.

[0015]

According to the ATM cell format converter of the present invention, when a bit shift occurs at the time of writing or reading a cell, the ATM cell format converter can recover from the data interruption state autonomously.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional ATM cell format converter.

[Explanation of symbols]

 Reference Signs List 1 input data 2 cell format conversion buffer 3 write timing control circuit 4 read timing control circuit 5 buffer reset control circuit 13 output data 14 empty cell detection circuit 15 monitoring cell generation circuit 16 monitoring cell insertion circuit 17 monitoring cell detection circuit 18 monitoring Pattern judgment circuit

Claims (2)

(57) [Claims] 1. An AH is provided only in a payload portion of an SDH frame.
Temporarily buffering ATM cells in an ATM cell format converter that converts the inserted state of ATM cells from a state in which TM cells are inserted to a state in which ATM cells are inserted in a header portion and a payload portion of an SDH frame. A cell format conversion buffer, a cell writing means for writing cells to the buffer, and a cell reading means for reading cells from the buffer, wherein the cell writing means detects an empty cell having no data. A vacant cell detection circuit, a monitoring cell generation circuit that generates a monitoring cell having a monitoring pattern for monitoring when the vacant cell detection circuit detects a vacant cell, and a vacant cell detected by the vacant cell detection circuit. A monitoring cell insertion circuit for inserting a monitoring cell from the monitoring cell generation circuit into the empty cell; A buffer reset control circuit for resetting a buffer, wherein the cell read means includes a monitor cell detection circuit for detecting the monitor cell from output data read from the buffer, and a detection monitor for the monitor cell detected by the monitor cell detection circuit. A monitoring pattern determination circuit that determines whether a cell detection monitoring pattern matches a predetermined reference monitoring pattern generated by the monitoring cell generation circuit and generates a bit shift signal when the detection monitoring pattern does not match. And the buffer reset control circuit resets the buffer when receiving a bit shift signal from the monitoring pattern determination circuit.
Cell format converter. 2. The cell writing means has a write timing control circuit for controlling a timing of writing an ATM cell into the cell format conversion buffer, and the cell reading means is configured to read a cell from the cell format conversion buffer. 2. The ATM cell format conversion apparatus according to claim 1, further comprising a read timing control circuit for reading timing of the ATM cell.