JPH0732381B2 - Plesiochronous buffer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The synchronizing circuit according to the present invention relates to a pre-geochronous synchronizing circuit for overcoming data synchronized with two different clocks.

[Prior Art] Conventionally, a circuit of this type generally slips data assuming only a frame synchronization bit.

Further, although data slip has been performed assuming a multi-frame synchronization bit, most circuits cannot support when the multi-frame synchronization bit is inserted in other than a specific time slot.

[Problems to be Solved by the Invention] The conventional technique has the following two drawbacks.

1) If only the frame synchronization bit is slipped, multiframe synchronization is lost.

2) Slip of data including multi-frame synchronization requires all of the PCM data and multi-frame synchronization bits that make up a multi-frame, which increases RAM capacity and data delay time, resulting in large data discontinuity.

[Means for Solving the Problems] According to the present invention, in a pre-geochronous buffer device for inputting a PCM signal 1 including frame synchronization bit information and multi-frame synchronization bit information, a RAM 100 for storing the PCM signal 1 is provided. A frame synchronization circuit 101 which receives the PCM signal 1 and outputs a frame synchronization signal 10, a clock extraction circuit 102 which receives the PCM signal 1 and outputs a clock signal 11, a frame synchronization signal 10 and the clock signal 11 RAM write side means including a RAM write counter 200 which outputs a RAM write address signal 12 as a frame counter, which is controlled by the frame synchronization signal 10 and which advances in response to the clock signal 11. A clock generator 400 for generating a clock signal 23 and a read address signal of the RAM 100 for receiving the read side clock signal 23. RAM read-out counter 202 outputs a 20
And the RAM 100 based on the read address signal 20.
Receiving the output PCM signal read by the above, the read address signal 20 and the read side clock signal 23,
RAM read side means including a multi-frame synchronization circuit 500 for outputting a multi-frame synchronization signal, the RAM write address signal 12 and the RAM read address signal 20, and the input two address signals 12, 20 is phase-compared with each other, and when the RAM write address signal 12 advances from the read address signal 20, the read counter delay signal 22 is output to the RAM read counter 202, and the read of the RAM address signal 12 is performed. If it is delayed from the read address signal 20, the read counter advance signal 21
To the RAM reading counter 202 for outputting the phase comparator 30
When the RAM read counter 202 receives the read counter delay signal 22, the RAM read counter 202 advances the counter for one frame and receives the read counter advance signal 21. In this case, a pre-geochronous buffer device is obtained in which the counter for one frame is stopped and the output PCM signal is slipped.

That is, the pregeochronous buffer circuit according to the present invention is
In a pre-geochronous synchronization circuit for PCM data composed of frames having both frame synchronization bit information and multi-frame synchronization bit information, a write counter for controlling RAM and RAM write, a clock extraction circuit, and frame synchronization It has a circuit, a read clock generator, a RAM read counter and a multi-frame synchronization circuit, and a phase comparison circuit for comparing the phases of the RAM write counter and RAM read counter.
The output of the phase comparison circuit is input to a read counter, and the read counter of the RAM is input to a multi-frame synchronization circuit.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment according to the present invention.

In the pre-diochronous circuit shown in FIG. 1, a PCM signal having a frame sync bit and a multi-frame sync bit is input to the input terminal 1. This PCM signal is simultaneously input to the RAM 100, the frame synchronization circuit 101, and the clock extraction circuit 102.

The frame synchronization circuit 101 acquires the frame synchronization from the input PCM signal and outputs the frame synchronization signal 10 to the first address counter.
Supply to 200. The clock extraction circuit 102 extracts a bit clock from the input PCM signal and supplies the clock 11 to the first address counter 200. First address counter 200
Is a counter that advances in accordance with the clock 11 and operates as a frame counter controlled by the frame synchronization signal 10. The output 12 of the first address counter 200 is RAM1
It is used as a write address of 00, and input PCM data is written to RAM according to this address.

The above is the description of the writing side of the RAM 100.

Next, the circuit on the RAM reading side will be described.

The clock generator 400 is a generation source of the read-side clock 23, and supplies the clock R23 to the second address counter 202 and the multi-frame synchronization circuit 500.

The second address counter 202 is RAM1 according to the clock R23.
A read address of 00 is generated. RAM data is read out according to the read-out address 20, and is given to the output terminal 2 and the multi-frame synchronizing circuit 500.

The multi-frame synchronization circuit 500 uses the RAM read address 2
0 and the clock R23 are given, the multi-frame bit is detected from the PCM signal output from the RAM 100, and the multi-frame synchronizing signal is output from the multi-frame terminal 3.

Next, the slip control circuit will be described.

The phase comparator 300 consists of the write address 12 of RAM100 and RAM100.
The read address of 20 and is input. Phase comparator 300
Performs phase comparison on the two input addresses.

At this time, in general, in this type of phase detection, when the clock of the clock generator 400 is used as a reference, the clock extracted from the input PCM signal may be advanced or delayed due to the difference in clock stability. Occurs.

Therefore, the phase comparator 300 uses the read address 20 of the RAM100.
When the phase difference between the write address 12 and the write address 12 exceeds the specified value, and the write address 12 of the RAM100 advances from the read address 20 of the RAM100, the second address counter advance signal 21 is output and the write of the RAM100 is performed. If the address 12 is delayed from the read address 20 of the RAM 100, the second address counter delay signal 22
Is output. The second address counter advance signal 21 and the second address counter delay signal 22 are
Given to 2. When the second address counter 202 receives the second address counter advance signal 21, the second address counter 202 stops the address counter 2 for one frame and slips the PCM data.
When the second address counter delay signal 22 is received, the second address counter 202 advances the counter for one frame and slips the PCM data.

The above is the slip control.

The pregeochronous buffer circuit according to the present invention is characterized by the following points.

When only the above-mentioned control circuit is used, multi-frame is not taken into consideration, so that multi-frame synchronization is always lost when slip occurs.

Therefore, the multi-frame synchronization circuit 500 is configured to constantly monitor the read address 20 of the RAM 100 output by the second address counter 202.

When a slip occurs, the read address of RAM100 is 20
Is limited to the event that the address for one frame advances or is delayed, the multi-frame synchronization circuit 500 can detect the occurrence of slip.

Therefore, the operation of the multi-frame detection circuit 500 is RA
The multi-frame sync bit is skipped when the read address 20 of the M100 advances by one frame, and the multi-frame sync bit is repeatedly used when the read address 20 of the RAM100 is stopped for one frame.

By using such a multi-frame synchronization circuit, it is possible to configure a circuit that does not lose multi-frame synchronization even if a frame slip occurs.

[Effects of the Invention] As described above, according to the present invention, a pre-geochronous circuit capable of preventing multi-frame slip can be realized only by the buffer capacity capable of frame synchronization protection, and the effect of minimizing the delay time of the PCM line is provided. is there.

[Brief description of drawings]

FIG. 1 is a block diagram according to an embodiment of the present invention. 1 …… input terminal, 2 …… output terminal, 3 …… multi-frame terminal, 10 …… frame synchronization signal, 11 …… clock, 12 …… RAM
100 write address, 20 …… RAM100 read address, 2
1 …… Address counter 2 advance signal, 22 …… Address counter 2 delay signal, 23 …… Clock R, 100 …… RAM, 101 ……
Frame synchronization circuit, 102 ... Clock extraction circuit, 200 ... First address counter 1,202 ... Second address counter, 30
0 …… Phase comparator, 400 …… Clock generator, 500 …… Multi-frame synchronization circuit.

Claims (1)

[Claims] 1. A pre-geochronous buffer device for inputting a PCM signal (1) containing frame synchronization bit information and multi-frame synchronization bit information, comprising: a RAM (100) for storing the PCM signal (1); A frame synchronization circuit (101) which receives the signal (1) and outputs a frame synchronization signal (10); a clock extraction circuit (102) which receives the PCM signal (1) and outputs a clock signal (11); Frame sync signal (10) and the clock signal (11)
In response to the clock signal (11),
A RAM writing side means including a RAM writing counter (200) which outputs a RAM writing address signal (12) as a frame counter and is controlled by the frame synchronization signal (10), and a reading side clock signal (23) is generated. A clock generator (400) and the read side clock signal (23) are received, and the RAM (1
00), which outputs a read address signal (20), and a RAM (1) based on the read address signal (20).
00), the read address signal (20), and the read side clock signal (2)
3) and a RAM reading side means including a multi-frame synchronizing circuit (500) for outputting a multi-frame synchronizing signal, the RAM write address signal (12) and the RAM reading address signal (20). When the received two address signals (12, 20) are phase-compared with each other and the RAM write address signal (12) advances from the read address signal (20), the read counter delay signal ( 22) is output to the RAM read counter (202), and when the RAM address signal (12) is delayed from the read address signal (20), a read counter advance signal (21) is output to the RAM read counter. And a slip control means including a phase comparator (300) for outputting to the (202), and the RAM read counter (202) receives one frame when the read counter delay signal (22) is received. Advancing between counter, when receiving the readout counter advance signal (21) is stopped between 1 frame counter, Purejio black eggplant buffer device, characterized in that to slip the output PCM signal.