JPH03120923A - Method and circuit for frame synchronization - Google Patents

Abstract

PURPOSE:To use one memory in common for a multi-point monitor memory, a delay element memory for slip control and a memory for data arrangement conversion by varying write/readout control of the memory depending on the state of synchronization and of out of synchronism. CONSTITUTION:An address of a memory 2 used for frame pattern detection of a pattern detection section 8 is controlled by sequential readout/write for the detection of the frame pattern at the time of appearing out of synchronism. On the other hand, the sequential write/random read control is applied at synchronization state and the readout address is used as an address having data arrangement conversion and data delay information. Thus, the multi-point monitor memory is used in common as a delay element for slip control and a memory for data arrangement conversion.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a frame synchronization circuit using a multi-point monitoring frame synchronization method, and particularly to a frame synchronization circuit having functions of slip control and data arrangement conversion by delay insertion/removal of data. Regarding circuits.

[Conventional technology]

The interface section of the primary group (1,544 Mb/a) transmission line has three functions: frame synchronization using a multi-point monitoring method, slip control using a delay insertion/extraction method, and centralized/distributed arrangement conversion of input data. The synchronization circuit of the conventional multi-point monitoring frame synchronization method is NTT Facility 981, 'l1.
0L55. No. 11. 100 pages.

As described in FIG. 24, memory is required to implement the function. Slip control by delayed insertion/removal is the same as 1.
As shown in FIG. 29, page 02, a delay element is required, and a memory is normally used as the delay element. Also,
A memory such as TsI shown in FIG. 18 on page 97 is required for centralized/distributed layout conversion.

[Problem to be solved by the invention]

In the above conventional technology, in order to realize the three functions of the interface section (7-frame pattern detection function, slip control function by delay insertion/extraction of data, and input data centralization/distribution layout conversion function), separate memories are used for each. Due to necessity, when configured with a highly integrated circuit such as the interface section t-LsI,
The hardware scale became larger, and there were problems in terms of implementation and cost.

An object of the present invention is to provide a frame synchronization method and circuit using a multi-point monitoring system, which has a slip control function and a data arrangement conversion function, is small in hardware scale, and is advantageous for high integration.

[Means to solve the problem]

In order to achieve the above purpose, a multi-point monitoring frame r
In the first method, the address control of the memory used when detecting the frame pattern was controlled by sequential read/write in order to detect the frame pattern when out of synchronization.

On the other hand, in the synchronous state, sequential write/random read control is performed, and the read address is set to an address value having data arrangement conversion and data delay information, so that the multi-point monitoring memory can also be used as a delay element for slip control. It is shared and controlled as a memory for data layout conversion.

Furthermore, the purpose of the first half is to search for a frame pattern that exists in a specific phase when synchronization is lost, control and output the write and read address signals input to the memory so that the input data is shifted one bit at a time, and This is accomplished by providing the frame synchronization circuit with a memory control circuit that controls and outputs the address signal having data delay information in accordance with data arrangement conversion and the data delay insertion/extraction signal when synchronization is established.

[Effect]

During the out-of-synchronization state (hunting period), in order to detect a frame pattern of n points that exists every frame bit period (m bits), input data is sequentially written to or read from n words at the same address every m bits. The frame pattern is detected by comparing the n pieces of data with the frame pattern, and the synchronization is restored. However, during the out-of-synchronization state (synchronization establishment, forward protection, backward protection period), m
It is not necessary to write all Xn bit data to memory, and D
Since it is sufficient to monitor one frame bit input every Im bit at n points, no memory is required. Therefore, in the out-of-synchronization state, the memory is used as a delay element for slip control and a memory for data arrangement conversion. This is achieved by setting the read address of the memory to an address value having data delay and data arrangement conversion information corresponding to the write address.

By the method described above, it is possible to realize a frame synchronization circuit equipped with slip control and data arrangement conversion functions with a smaller scale than the conventional circuit.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an (n+1) multi-point monitoring frame synchronization circuit according to an embodiment of the present invention. At input terminal 1, concentrated arrangement data having a frame bit period of m bits is input, and the input data is written to the D1 word of memory 2. In the memory 2, by controlling the write/read addresses from the RAM control circuit 5, frame pattern hunting operation when synchronization is lost, input data concentration/distribution rearrangement conversion operation, and slip control operation by delay insertion/extraction of data are realized. . A detailed diagram of the memory 2 and RAM control circuit 5 is shown in FIG. Further, a timing chart diagram of the circuit shown in FIG. 2 is shown in FIG.

The RAM control circuit 5 sequentially counts at the same speed as the input data, as shown in FIG.

It has a counter of 211L including an address generation counter 4 and an address generation counter 5 which counts with a delay of the address color/relay bit by the data delay bit. The counter value 6 of the address generation counter 4 is outputted to the address of the memory 2 by the selection circuit 7 as a write/read address in the frame pattern hunting operation when synchronization is lost. The operation of the memory 2 at this time is shown in FIG. 3 and FIG. As shown in FIG. 3, when synchronization is lost, a read operation is performed in the first half of the same address, and a write operation is performed in the second half. At this time, the input/output data D of the memory 2
, ~Dn is controlled by reading the data as shown in FIG. 4(1) when the address value is 1 in the case of 4-point monitoring consisting of A-D frames as shown in FIG. 4(1), and checking the latest data. d.

The 4 bits including t- are output to the pattern detection section 8 in FIG. And when writing, there is a lot of pressure. -D2 data is shifted to ~D and written to the same address. Next, when the address value is 2, a similar operation is performed for input data d. By performing such an operation for (mx4) bits, the pattern detection section 8 can hunt a frame pattern in the input data series.

The pattern detection unit 8 detects whether the pattern matches the 7-frame pattern or
The mismatch information is output to the frame synchronization protection section 9, and the frame synchronization preservation section 9 performs synchronization protection and outputs synchronization loss/synchronization establishment information to the RAM control section 3. Here, when synchronization is established, it is not necessary to compare data at (n+1.) points at once, and one frame bit bit input every m bits is loaded into the pattern detection unit 8, and mX
It is sufficient to monitor the frame pattern every (n+1) bits. Here, when the synchronization i starts, by changing the address control of the memory 2 from the control described above, the input data centralization/distribution arrangement conversion operation and the slip control operation by delay insertion/extraction of data are performed. Fig. 5 shows the principle diagram. As shown in FIG. 5, writing/reading operations are performed corresponding to each frame of input data. If there is no request for data delay, input data 2 is stored in double buffer format.
Sequential reading and random reading are performed corresponding to each frame. Next, when a data delay request is made, sequential writing and random reading are performed corresponding to each of the five frames of input data in a triple buffer format. At this time, data delay is realized by delaying the timing of writing and reading from the memory for the same frame by the amount of data delay.

A configuration diagram of the RAM control section 3 based on this principle is shown in FIG. The write address uses the counter value 6 of the address generation counter 4. Next, as the read address, the address value 12 output from the distributed read address generation section is used.

The distributed placement read address generation unit 10 generates a distributed placement address corresponding to the counter value 15 that is varied by the selection circuit 11. The counter value 15 is the counter value 6 from the address generation counter 4 when there is no data delay request, and the counter value 14 from the address generation counter 5 when there is a delay request. 1
1 is selected and used. Depending on the control method like this)
, data from the D1 word of the memory 2 controlled by the address from the RAM control unit 3 can be converted in the amount of dispersion and can be inserted and removed with delay. The data is output to the phase matching section 15 in FIG. The phase matching section 15 is 1B(
The phase matching is realized by controlling the glance/readout signal. Further, this signal is monitored by the phase monitoring section 16, and if there is a risk of slipping, a data delay insertion/extraction request signal is output to the RAM control section 3.

As described above, according to this embodiment, by sharing the memory for (n+1) point monitoring as the memory for the delay element of slip control and the memory for concentrated/distributed layout conversion, economical
This is advantageous for high integration.

In addition, input data is multiplexed data of multiple highways, and random readout control makes it possible to share the memory with line setting memory.

〔Effect of the invention〕

According to the present invention, in a frame synchronization circuit using a multi-point monitoring method, by changing the read/write control of the memory depending on the synchronized state and the out-of-synchronization state, multi-point monitoring can be performed using one memory. Since the memory for delay elements for slip control and the memory for data arrangement conversion can be shared, it is advantageous for economicalization and high integration of LSIs and the like.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of an (n+1) multi-point monitoring frame synchronization circuit according to an embodiment of the present invention, FIG. 2 is a detailed diagram of the memory section and RAM control section in FIG. 1, and FIG. 5 is a memory FIG. 4 is a diagram illustrating a RAM control method in an out-of-synchronization state, and FIG. 5 is a diagram illustrating a RAM control method in a synchronization established state. 1...Data input terminal, 2...Memory (RAM), 5...RAM control unit,
4...Address generation counter, 5...
...Address generation counter (for data delay), 8
. . . Pattern detection section, 10 . . . Distributed address generation section, 16 . . . Phase monitoring section. Figure 5 RAMλ Figure 4

Claims (1)

[Claims] 1. In a frame synchronization method that uses memory to detect frame patterns when synchronization is out of synchronization, perform slip control by delay insertion/removal of data, and centralize/distribute layout/conversion of input data, a single memory can be synchronized. A frame synchronization method characterized in that when the frame pattern is out of synchronization, the frame pattern is detected, and when synchronization is established, the frame synchronization method is used for slip control by delay insertion/removal of the data and centralized/distributed arrangement conversion of input data. 2. When out of synchronization, frame pattern detection
The memory address is controlled by sequential read/sequential write, and when synchronization is established, the memory read address is set to an address value that includes data layout conversion information and data delay information corresponding to the write address, and the memory address is controlled by sequential write/random read. A frame synchronization method characterized by performing address control. 3. A memory that inputs input data and outputs n pieces of data for each frame bit synchronization while shifting 1 bit at a time, and compares the n pieces of data output from the memory with the frame pattern to determine whether it matches or does not match. the pattern detection circuit that outputs the results of the above to the frame synchronization protection circuit; the frame synchronization protection circuit that outputs out-of-synchronization information based on the match/mismatch results; and the phase matching circuit that performs phase matching of the input data; A phase monitoring circuit that monitors the phase matching and outputs a data delay insertion/removal signal when there is a risk of slipping, and a phase monitoring circuit that outputs a data delay insertion/removal signal when there is a risk of slipping; controlling and outputting write and read address signals input to the memory so that the input data is shifted one bit at a time in order to search for a frame pattern existing in the memory;
On the other hand, a frame synchronization circuit characterized in that it has a memory control circuit that controls and outputs the address signal having data delay information by changing the arrangement of data and the data delay insertion/extraction signal when synchronization is established.