JPH05227141A - Phase difference correction circuit - Google Patents

Abstract

PURPOSE:To provide a phase difference correction circuit in a transmission line switching circuit in which phase correction in bit unit can be performed on a short distance transmission line, and also, circuit configuration can be simplified. CONSTITUTION:Delay control circuits 100, 200 which output delay frame pulses S0 with in-phase before and after switching are provided at the transmission lines of data memory M1 M2 for system in current use and spare system, respectively, and the readout addresses of the data memory M1, M2 are formed by the delay frame pulse S0. The delay control circuits 100, 200 are comprised of delay frame pulse forming means 10 which delay a frame pulse S1 for system in current use based on prescribed preset delay quantity D1, and means 20 which fetch delay quantity from the spare frame pulse S2 of the delay frame pulse S0 as preset delay quantity D2 synchronizing with the delay frame pulse S0 from the delay control circuit 100 for system in current use when a system is switched to a spare system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase difference correction circuit, and more particularly to a phase difference correction circuit in a digital transmission line switching device.

[0002]

2. Description of the Related Art A data transmission line, whether wired or wireless, is provided with a backup transmission line in consideration of maintenance of the active system or failure of the active system. At the same time, it is provided with a switching circuit for switching between the active and standby transmission paths.

Since there should be no overlap or skip between the data obtained from the active system and the data obtained from the standby system when switching the transmission lines, it is possible to correct the phase difference between the active system and the standby system. A transmission line switching circuit has been developed.

For example, in Japanese Unexamined Patent Publication No. 1-264427, the same signal is simultaneously transmitted in parallel to the active transmission path and the standby transmission path to detect the phase difference between the two frames.
A transmission path switching system that performs correction based on the phase difference is disclosed.

Further, Japanese Patent Laid-Open No. 3-160835 discloses the following phase correction circuit. That is, FIG.
As shown in FIG.
Inputting the working and spare frame signals to 0 and 600, and shifting the write signal indicating a predetermined number of addresses for writing the working and spare signal data into the working and spare memories 400 and 500 by 1 bit. Output at a fixed cycle.

Next, according to this address, the working and protection signal data are transferred to the working and protection memories 400 and 500.
And read by the read signal output from the read signal generation circuit 900. The read signal generation circuit 900 outputs a read signal in response to a control signal output from the phase comparison control circuit 800. The phase comparison control circuit 800 outputs the first address of the output of the read signal generation circuit. And a write signal indicating the first address of the output of the current or spare write signal generation circuit are input and compared, and the read signal is positioned in the middle of a fixed cycle of the write signal. The control signal is output under control.

[0007]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The transmission line switching method disclosed in Japanese Patent No. 427 is applied to a long-distance transmission line, and its purpose is to correct a phase shift in frame units.

As described above, in order to detect the phase shift of both signals on a frame-by-frame basis, first, it is necessary to provide a frame synchronization circuit for synchronizing the frame signals of both systems. Further, there is a drawback that the circuit configuration becomes very complicated, such as the need to provide means for detecting the phase difference between the frames of both systems.

Further, according to the phase correction circuit described in Japanese Patent Laid-Open No. 1-264427, the read signal generating circuit 900 common to the active system and the standby system is used, and when a failure occurs in this part, the active signal is used. Neither the system nor the standby system can be used.

In addition, the active and standby memories 400, 5
In order to write data to 00, a write signal indicating a predetermined number of addresses is shifted bit by bit so as to be output at a constant cycle, and a read signal has the same configuration.

Therefore, the write signal generating circuits 300, 6
00 and the memories 400 and 500, and the number of signal lines between the read signal generation circuit 200 and the memories 400 and 500 are large, which makes the circuit configuration complicated.

The present invention has been proposed in view of the above-mentioned conventional circumstances, and provides a phase difference correction circuit in a transmission path switching circuit which can perform phase correction in bit units on a short-distance transmission path and has a simple circuit configuration. It is intended to be provided.

[0013]

The present invention employs the following means in order to achieve the above object. That is, in a transmission path switching circuit that includes an active system data memory M1 and a standby system data memory M2, and when switching the transmission path from the active system to the standby system, in-phase data in both systems is read from the data memories M1 and M2. As shown in FIG. 1, delay control circuits 100 and 200 for outputting in-phase delayed frame pulses S0 before and after switching are provided to the transmission path of the active data memory M1 and the transmission path of the standby data memory M2, respectively. In advance, the delay frame pulse S0 is used to form the read addresses of the data memories M1 and M2, and the delay control circuits 100 and 20 are provided.
0 is a delayed frame pulse forming means 1 for delaying the active frame pulse S ₁ based on a predetermined set delay amount D 1.
0, and when the active system is switched to the standby system, the delay amount of the delayed frame pulse S0 from the standby frame pulse S2 is set in synchronization with the delayed frame pulse S0 output from the active system delay control circuit 100. Delay amount D
_The delay amount fetching means 20 fetched as ₂ .

The delay frame pulse forming means 10 is
As shown in FIG. 2, a storage means 1 in which a delay amount for delaying the active frame pulse S1 is set, and a counter 2 which is reset in synchronization with the active frame pulse S1.
And a comparator 3 which outputs a delayed frame pulse S1 when the output of the counter 2 and the output of the storage means 1 match.
And is equipped with.

Further, the set value fetching means 20 stores the count value of the counter 2 to which the standby system frame pulse S2 is input at the timing synchronized with the delayed frame pulse S0 when the active system is switched to the standby system. The configuration is taken into the means 1.

[0016]

[Action] the delayed frame pulse forming means predetermined amount of delay from the working frame pulse in 10 D ₁ delayed delayed frame pulse S0 are formed.

When the active system is switched to the standby system, the frame pulse S of the standby system of the delayed frame pulse S0
If the delay amount D ₂ from 2 is known, its value by replacing a predetermined delay amount D ₁ of the said active system to a predetermined delay amount D ₂ of the standby system, the active system based on the frame pulse S2 of the protection system In-phase delayed frame pulse S0 can be formed.

Therefore, when switching from the active system to the standby system, the frame pulse S of the standby system of the delayed frame pulse S0 obtained from the delay control circuit 100 of the active system is used.
The delay from 1 is detected and used as a new delay amount D ₂ .

As a result, a delayed frame pulse S0 having a fixed phase can be obtained in both the active system and the standby system, and if the read address is formed based on this delayed frame pulse S0, the active system can be used as the standby system. There is no skip or duplication in the read signal when switching to.

[0020]

FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a timing chart of FIG.

Data memories M1 and M2 are provided in the active system and the standby system, respectively. In order to alternately perform writing and reading, the respective data memories M1 and M2 are composed of two unit memories M1a, M1b and M2a, M2b. Is becoming

Further, delay control circuits 100 and 200 for delaying the frame pulses S1 and S2 by a predetermined amount corresponding to the active system and the standby system to form a delayed frame pulse S0 having the same phase in the active system and the standby system are provided. The delayed frame pulse S0 forms the read address of the two memories M1 and M2.

Since the active system and the standby system have exactly the same configuration, only the active system will be described below. First, the delay control circuit 100 (200) is as follows.

That is, the register 1r as a storage means
A delay amount D ₁ (D ₁ = 5 in FIG. 4) which is a predetermined amount (3 in FIG. 4) which is equal to or more than the phase difference between the frame pulse S 1 for the active system and the frame pulse S 2 for the standby system is set. On the other hand, the counter 2 is reset by the active system frame pulse S1 and then counted up at the same cycle as the access (writing, reading) cycle of the memory M1 as shown in FIG.

The contents of the register 1r and the counter 2 are inputted to the comparator 3, and when the output of the counter 2 matches the contents of the register 1r, the coincidence pulse P ₀ is inputted to the selector 5.

The selector 5 is normally set to "main", that is, the working system by the master-slave setting signal S ₁₀ , and outputs the coincidence pulse P ₀ output from the comparator 3. Matching pulse P that passed 5
₀ indicates the delayed frame pulse S0 as shown in FIG.
And is input to the register 1r as a reset signal of the register 1r.

The output of the register 1r and the output of the counter 2 are input to the selector 4 provided in the preceding stage of the register 1r. Normally, the input from the register 1r is output by the master-slave setting signal S ₁₀ . ing.

When the delayed frame pulse S0 is input to the register 1r as described above, the previous set value D of the register 1r input via the selector 4 as described above.
Set _{1 as it} is as the next set value (Fig. 4
(B)).

With the above configuration, the master-slave setting signal S
When ₁₀ is "main", the frame pulse S1 is to be output as a delayed frame pulse S0 which is delayed by D ₁ which is set in the register 1r.

Next, consider a case where the transmission path is switched and the standby system frame pulse S2 is input to the counter 2 of the standby delay control circuit 200. In this case, the master-slave setting signal S ₁₀ input to the selector 4 and the selector 5
Is set to “subordinate”. Further, the active-system delay control circuit 100 operating as described above is also temporarily moving in parallel, and the delay pulse S0 obtained by the active-system delay circuit 100 is input to the selector 5, and the selector 5 Is input as a reset signal to the register 1r via.

On the other hand, the counter 2 is reset and counts up each time the standby system frame pulse S2 is input as shown in FIGS. 4 (e) and 4 (g), whereby the active system delay control is performed. At the timing when the delayed frame pulse S0 is input from the circuit 100, the register 1r fetches the count value (3 in FIG. 4) output from the counter 2 into the register 1r via the selector 4 (FIG. 4 (f)). ).

After that, when the master-slave setting signal S ₁₀ is returned to "main" again, this system operates as the active system and operates exactly the same as the delay control circuit 100.
Next, the memory M1 is accessed as follows.

The frame pulse S1 of the working system is input to the write address counter 9 of the working system memory M1, and the write address counter 9 of the working system memory M1 (the counter 2 shown in FIGS. 4 (c) and 4 (g)) is thereby supplied. The same as the output) is formed and the data is written.

On the other hand, delayed frame pulse S0 which is formed as described above is input to the read address counter 15 in the memory M1, by the set delay amount D ₁ with respect to the write address as shown in FIG. 4 (i) The read address Ar is formed with a delay. This output data Dout of the memory M1 will be read out is delayed by the delay amount D ₁ with respect to the input data Din.

Even if the active system is switched to the standby system, since the phase of the delay pulse S0 is the same as described above, the phases of the data read by the active system and the standby system do not shift.

The memory M of each of the active system and the standby system
1 and M2 are two memories M1a and M1b and M2a and M2b.
It is possible to write and read alternately. That is, in the working system, the frame pulse S1 is input to the write signal forming circuit 8
A write signal S ₂₀ that becomes “1” or “0” is formed for each frame, and thus the memories M1a and M1b are written for each frame.

On the other hand, as described above, the set delay amount D
_{According to 1} (D ₂ ), the read address is formed by the read address counter 15 according to the delayed frame pulse S 0 delayed from the frame pulse S 1, and the delayed frame pulse S 0 is also sent to the select signal forming circuit 11 as described above. A select signal S ₃₀ that is input and repeats “1” and “0” for each frame is formed. As a result, the selector 12 controlled by the select signal S ₃₀ advances by the delay amount D ₁ ,
The data read from the memory M1a (M1b) on the writing side is output.

[0038]

As described above, according to the present invention, the delay control circuit provided in the active system and the standby system can form the delayed frame pulse in phase before and after the switching from the active system to the standby system. Since the read address of the memory is formed based on the frame pulse, data duplication or skip does not occur before and after the switching.

Moreover, the active delay control circuit and the standby delay control circuit are independent of each other, and when one of them fails, the replacement becomes easy.

[Brief description of drawings]

FIG. 1 is a principle view of the present invention.

FIG. 2 is a principle diagram of a delay control circuit.

FIG. 3 is a block diagram of an embodiment of the present invention.

FIG. 4 is a timing diagram of FIG.

FIG. 5 is a block diagram of a conventional example.

[Explanation of symbols]

1 Storage Means 2 Counter 3 Comparator 10 Delay Frame Pulse Forming Means 20 Delay Amount Intake Means 100, 200 Delay Control Circuits D ₁ , D ₂ Delay Amount M1 Working Data Memory M2 Standby Data Memory S0 Delay Frame Pulse S1 Working System Frame Pulse S2 Preliminary frame pulse

Claims (3)

[Claims] 1. An active system data memory (M1) and a standby system data memory (M2) are provided, and when switching the transmission line from the active system to the standby system, data in phase in both systems is stored in the data memory (M1).
1), In the transmission line switching circuit that reads from (M2), the transmission line of the active data memory (M1) and the backup data memory
Delay control circuit that outputs in-phase delayed frame pulse (S0) before and after switching to each of the (M2) transmission lines
(100) and (200) are provided, and the delayed frame pulse (S
(0) is configured to form the read address of the data memory (M1), (M2), and each delay control circuit (100), (200)
The active system frame pulse based on the preset delay amount (D ₁ )
Delay frame pulse forming means (10) for delaying (S1),
Delayed frame pulse output from the active delay control circuit (100) when switching from the active system to the standby system
Backup system the set delay amount the delay amount from the frame pulse (S2) (D ₂₎ delay capture means (20) and become more phase difference correction circuit for taking as the (S0). 2. The storage means (1) in which the delay frame pulse forming means (10) sets a delay amount for delaying the active frame pulse (S1) and the active frame pulse (S1) in synchronization with each other. A comparator that outputs a delayed frame pulse (S0) when the counter (2) to be reset matches the output of the counter (2) and the output of the storage means (1).
(3) The phase difference correction circuit according to claim 1, comprising: 3. The count value of the counter (2) to which the standby system frame pulse (S2) is input when the delay amount capturing means (20) is switched from the active system to the standby system, The phase difference correction circuit according to claim 2, wherein the phase difference correction circuit is configured to be stored in the storage means (1) at a timing synchronized with S0).