JP2575542B2 - Packet information counter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a local area network (LAN) which connects a plurality of communication stations by a transmission line and performs packet communication between these stations, and which is required for quality control of packets transmitted. The present invention relates to a packet information counter used when collecting packet information.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a configuration example of a conventional packet information counter. In this figure, reference numeral 1 denotes a multi-port repeater / packet information detector, and each of segments 0 to N of a network (not shown). Are connected to correct the timing and reproduce the waveform of the signal transmitted through the network, and detect various types of packet information necessary for quality control of the transmitted packet when the packet passes through the multiport repeater. Reference numeral 2 denotes a packet information controller, which converts the parallel signal packet information PI output from the multiport repeater / packet information detector 1 into serial signal packet information data PID, and an address signal ADS synchronized with the packet information data PID. Generate Reference numeral 3 denotes an adder, and reference numeral 4 denotes a dual-port RAM, the storage area of which is divided by the type of packet information and the segment number, and the count value of the packet information is stored in each of them. Reference numeral 5 denotes a CPU (central processing unit) that controls each unit of the apparatus.

In such a configuration, the multi-port repeater / packet information detector 1 corrects the timing and reproduces the waveform of the signal transmitted from each of the segments 0 to N of the network (not shown), When passing through a repeater, various packet information is detected. Next, the packet information controller 2 converts the parallel signal packet information PI output from the multi-port repeater / packet information detector 1 into serial signal packet information data PID,
An address signal ADS synchronized with D is generated.

Thus, the packet information controller 2
Is written to the dual port RAM 4 via the adder 3 in accordance with the address ADS output from the packet information controller 2. Next, the packet information controller 2 outputs a prohibition signal CONS to the CPU 5 at the same time as the end of the packet transmission / reception to prohibit the CPU 5 from reading and writing.
, The count value is once read up by the adder 3, and then the dual port RAM 4 is read again.
To the same storage area. The various types of statistical information written in the dual port RAM 4 in this manner are read by the CPU 5.

[0005]

In the conventional packet information counter described above, the count value of a certain area of the dual port RAM 4 is counted up.
Since the CPU 5 reads out the count value from the same area, the packet information controller 2 outputs the inhibition signal CON when counting up (when a packet is absent).
It was necessary to prohibit reading and writing of CPU 5 by S. Therefore, there is a disadvantage that the degree of freedom of reading and writing of the CPU 5 is limited.

Also, if the count-up of the packet information is performed during access by the CPU 5, there is a danger that the packet information will be lost. Furthermore, if the packet information is read while the packet is absent, there is a possibility that the synchronization of the packet information may be lost. Therefore, there is a problem in that a measure must be taken to invalidate the packet information each time.

In order to solve the above-mentioned problems by hardware, there is a disadvantage that the circuit size becomes large, so that it is necessary to rely on software. SUMMARY OF THE INVENTION The present invention has been made under such a background, and it is assured with a small circuit scale that it is possible to avoid contention between count-up of packet information and CPU access and to prevent loss or de-synchronization of packet information. It is an object of the present invention to provide a packet information counter which can be used for a packet.

[0008]

SUMMARY OF THE INVENTION A packet information counter according to the present invention is used in a local area network in which a plurality of communication stations are connected by a transmission line to perform packet communication between these stations, in a first and second storage areas. Storage means for storing various types of packet information necessary for quality control of packets transmitted through the network, and any one of the first and second storage areas of the storage means. First selecting means for selecting, and inputting the packet information to generate an address, outputting the address to the first selecting means, and selecting one of the first and second storage areas Packet information control means for selecting and storing the packet information in a selected storage area;
Control means for transferring an access signal to the first selecting means to select the first or second storage area in a standby state in order to access the storage means; and controlling the first or second storage area in a standby state After selecting the second storage area, the first or second storage area different from the first or second storage area selected by the first selection means based on a control signal output from the first selection means. And a second selecting means for transferring an access enable signal to the control means after selecting the second storage area.

[0009]

According to the above arrangement, first, the packet information selecting means receives the packet information transmitted through the network, generates an address, outputs the address to the first selecting means, and outputs the first and second packet information. Is selected, and the packet information is stored in the selected storage area.
Then, the control unit accesses the storage unit by using the first
When the access signal is transferred to the selection means, the first selection means selects the first or second storage area in the standby state and then outputs the control signal.

With this, the second selection means selects the first or second storage area different from the first or second storage area selected by the first selection means based on the control signal. , An access enable signal to the control means. Therefore, the control means can freely read and write to the storage means after receiving the access enable signal.

[0011]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a packet information counter according to an embodiment of the present invention. In this figure, parts corresponding to the respective parts in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. However, the storage area (memory map) of the dual port RAM 4 is divided into a bank 4a selected by the MSB "0" of the address ADS and a bank 4b selected by the MSB "1" of the address ADS. I have. The packet information is normally counted up using one bank 4a or 4b, and the other bank 4a or 4b is cleared and is in a standby state. In FIG. 1, bank selectors 6 and 7 for setting the MSB of the address ADS to “0” or “1” are newly provided.

In such a configuration, first, the multi-port repeater / packet information detector 1 corrects the timing and reproduces the waveform of the signal transmitted from each of the segments 0 to N of the network (not shown), and When passing through a multi-port repeater, various packet information is detected. Next, the packet information controller 2 converts the parallel signal packet information PI output from the multi-port repeater / packet information detector 1 into a serial signal packet information data PID and an address signal synchronized with the packet information data PID. Generate ADS.

Thus, the packet information controller 2
Is output from the packet information controller 2 and passed through the adder 3 to the dual port RAM according to the address ADS passed through the bank selector 6.
The data is written to the four banks 4a or 4b. Next, the packet information controller 2 reads the count value from the dual port RAM 4 at the same time as the end of the packet transmission and reception, increments the count value by 1 in the adder 3, and writes the count value into the same storage area of the dual port RAM 4 again.

The CPU 5 has a dual port RAM.
When the access signal AC is transferred to the bank selector 6 in order to access 4, the bank selector 6 selects a bank 4a or 4b in a standby state in anticipation of the absence of a packet. On the other hand, the bank selector 7 receives the control signal CTL output from the bank selector 6 and inputs the control signal CTL.
After selecting another bank 4a or 4b other than b, CP
The access enable signal ACE is transferred to U5.

Thus, the CPU 5 can freely read and write to the dual port RAM 4 only after receiving the access enable signal ACE. As described above, the storage area of the dual port RAM 4 is
a and 4b, and by controlling the banks 4a and 4b by the two bank selectors 6 and 7, it is possible to avoid competition between the addition of the statistical information and the access of the CPU 5, and to process the packet information smoothly. be able to.

[0016]

As described above, according to the present invention, the storage area of the storage means is divided into a plurality of areas, and the storage areas are switched by the plurality of selection means. Access conflict can be avoided, and the control means has a high degree of freedom in reading and writing. Further, there is an effect that loss of packet information can be avoided structurally. Further, there is an effect that the synchronization of the packet information is always maintained. In addition, there is an effect that even if the circuit scale is small, it hardly depends on a program.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a packet information counter according to one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a conventional packet information counter.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Multiport repeater packet information detector 2 Packet information controller (packet information control means) 3 Adder 4 Dual port RAM (storage means) 4a, 4b Bank (storage area) 5 CPU (control means) 6, 7 Bank selector ( Selection means)

Claims (1)

(57) [Claims] 1. A local area network in which a plurality of communication stations are connected by a transmission line to perform packet communication between these stations, the local area network having first and second storage areas,
Storage means for storing various types of packet information necessary for quality control of packets transmitted to the network, and a first means for selecting one of the first and second storage areas of the storage means Selecting means for generating an address by inputting the packet information, outputting the address to the first selecting means, and selecting one of the first and second storage areas, Packet information control means for storing packet information in a selected storage area; and an access signal transferred to the first selection means for accessing the storage means, the first or second storage being in a standby state. Control means for selecting an area; and the first selection based on a control signal output from the first selection means after selecting the first or second storage area in a standby state. Second selecting means for transferring an access enable signal to the control means after selecting the first or second storage area different from the first or second storage area selected by the stage. A packet information counter, characterized in that: