JPH04310161A - Data readout circuit - Google Patents

Abstract

PURPOSE:To prevent the erroneous reading of data written by a CPU from one port of a dual port memory due to the change of the processing time of a CPU of the data readout circuit where the multiplex processing part of a PCM terminal equipment reads out data from the other port at regular intervals. CONSTITUTION:The circuit is provided with a dual port memory 42 one port of which is connected to a CPU 41, a control circuit 43 connected to the other port of the dual port memory 42, and a temporary storage memory connected to the CPU 41 and the dual port memory 42. The highest order address of the dual port memory 42 is connected to be reverse logic in the right and left ports, connected to a synchronizing signal line feeding a synchronizing signal to the CPU 41 from the circuit 43, the output data of the CPU 41 is temporarily stored in the temporary storage memory 11, synchronized with the synchronizing signal to be transferred from a temporary storage memory 11 to the dual port memory 42.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexing processing section for performing signal processing in a PCM terminal station, and more particularly to a data reading circuit for reading out signal processing results written in a dual port memory from the dual port memory.

0002

2. Description of the Related Art A data reading circuit of a multiplexing processing unit that performs signal processing in a conventional PCM terminal equipment is as shown in FIG.
A dual port memory 42 has a microcomputer (hereinafter referred to as CPU) 41 connected to one port via an address bus and a data bus, and a microcomputer (hereinafter referred to as CPU) 41 is connected to the other port of the dual port memory 42 via an address bus and a data bus. It has a data read control circuit (hereinafter simply referred to as a control circuit) 43.

[0003] Here, the dual port memory 42 is a C
If the PU 41 and the control circuit 43 access the same address at the same time, access by either one will not be accepted. Therefore, if the CPU 41 attempts to write to an address that has been read by the control circuit 43, there is a possibility that the processing results of the CPU 41 will be lost. Therefore, the highest address line 44 of the address bus on the control circuit 43 side is connected to the NOT circuit 45,
Generally, the output of the NOT circuit 45 is connected to the highest address of the port on the CPU side. In this way, N
By connecting the most significant address to reverse logic using the OT circuit 45, the memory space can be divided into halves as shown in FIG. That is, when the control circuit 43 is accessing the lower half address (hereinafter referred to as A side), the CPU 41 accesses the upper half address (hereinafter referred to as B side).

[0004] Furthermore, the control circuit 43 and the CPU 41 are connected by a synchronization signal line 46.

Next, the operation will be explained with reference to FIG. The CPU 41 reads data from a predetermined address in the dual port memory 42 and processes it in synchronization with the fall of the synchronization signal from the control circuit 43. This data processing is performed alternately on the A side and the B side, and the processing time differs for each process. The processing results are written to the dual port memory 42 again. In addition, in FIG. 6, the CPU 41
Only the least significant bit (bit 0) of the processing result data is shown.

On the other hand, the control circuit 43 reads data from a predetermined address in the dual port memory 42 in synchronization with the rise of the read pulse, and outputs it to the output terminal 47. Here too, reading is performed alternately on the A side and the B side. Note that the repetition period of the read pulse matches the repetition period of the synchronization signal.

[0007]

[Problem to be solved by the invention] In the conventional system, the CP
This is an effective means if U41 can reliably produce a processing result within the time specified by the synchronization signal, that is, within the time specified in the specifications of the PCM terminal device. However, CPU41
If the processing becomes complicated and the processing is not completed within the time set for the device, the processing result data of the CPU 41 and the read result data of the control circuit 43 may match, as shown in FIG. The problem is that it doesn't.

An object of the present invention is to provide a data reading circuit that allows the control device 43 to always read correct data without being affected by the processing time of the CPU 41.

[0009]

[Means for Solving the Problems] According to the present invention, there is provided a dual port memory having two ports capable of writing/reading from each port and having a microcomputer connected to one port, and the other port of the dual port memory. a data read control circuit that is connected to a port of the dual port memory and reads data from the dual port memory at predetermined time intervals, and the microcomputer processes data in synchronization with a synchronization signal from the data read control circuit. In a data reading circuit for writing processed data into a port memory, a temporary storage memory different from the dual port memory is connected to the CPU and the dual port memory, and the microcomputer writes the processed data each time data processing is completed. The data reading circuit is characterized in that the data written in the temporary storage memory is read out and written in the dual port memory in synchronization with the synchronization signal.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of a data read circuit according to an embodiment of the present invention. Components that are the same as the conventional ones are given the same numbers.

The left port of the dual port memory 42 is connected to the CPU 41 via an address bus and a data bus.
and temporary storage memory 11 are connected. A data read control circuit 43 whose output terminal 47 is connected to a signal processing circuit of a PCM terminal device is also connected to the right port via an address bus and a data bus. In this embodiment, it is assumed that an address bus having 16 signal lines and a data bus having 8 signal lines are used. Also, lead wires, write wires, power wires, etc. are omitted.

As in the past, the top line 44 of the address bus on the control circuit 43 side is connected to invert the logic by passing a NOT circuit 45 between the right port and the left port of the dual port memory 42. There is. Thereby, as shown in FIG. 2, it can be divided into a lower address half (A side) and an upper address half (B side).

Furthermore, the control circuit 43 and the CPU 41 are connected through a synchronization signal line.

The operation will be explained below. The control circuit 43 is
CPU41 at regular intervals determined by the PCM terminal equipment specifications.
Send a synchronization signal to. This synchronization signal causes the CPU to
2 stores the processing completion result data temporarily stored in the temporary storage memory 11 in the dual port memory 42, for example.
Transfer to side A. Then, start regular processing of the data,
The processing results are written to temporary storage memory 11 for temporary storage. Typically, this process completes before the next synchronization signal is issued.

While the CPU 41 is transferring and writing data to the A side of the dual port memory 42, the control circuit 43 accesses the B side of the dual port memory 42, that is, reads data. In addition, while the CPU 41 is transferring and writing data to the B side of the dual port memory 42, the control circuit 4
3 accesses side A of the dual port memory 42, that is, reads data. This allows normal access without address collision.

[0016] Here, the operation when the number of processing items of the CPU increases temporarily and the processing is not completed within the time specified by the PCM terminal device specifications will be explained. For example, when the processing time for side B increases and the time period when side A should normally be accessed has entered, a timer within the CPU 41 detects this. Then, while continuing the data processing, the previously processed data, that is, the same data as the data already written on the B side, is retrieved from the temporary storage memory 11 for temporary storage and written on the A side. When the data processing is completed, the CPU 41 writes the result into the temporary storage memory 11 for temporary storage. Thereafter, the above operation is repeated.

In this way, even if the data processing time of the CPU 41 changes, the processing result data of the CPU 41 and
No error occurs during read result data of the control circuit 43. Note that the data shown in FIG. 3 is only the 0 bit, which is the least significant bit of the 8-bit data bus.

[0018]

As explained above, according to the present invention, a temporary memory is provided in the data reading circuit, data processed by a microcomputer is temporarily written to the temporary memory, and the data written to the temporary memory is read. By reading and writing to the dual port memory in synchronization with the synchronization signal, even if the CPU processing time is longer than the time specified in the PCM terminal equipment specifications, the latest CPU processing completion result data can be transferred to the dual port memory. Since data can be written into memory, changing points in CPU processing result data can be read without error.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a memory map of dual port memory 42.

FIG. 3 is a signal waveform diagram in the data read circuit of FIG. 1;

FIG. 4 is a block diagram of a conventional data read circuit.

FIG. 5 is a memory map of the dual port memory 42.

FIG. 6 is a signal waveform diagram in the data read circuit of FIG. 4;

[Explanation of symbols]

11 Temporary storage memory 41 CPU 42 Dual port memory 43 Control circuit 44 Control circuit side highest address 45 N
OT circuit 46 synchronous signal line 47 output terminal

Claims (1)

[Claims] [Claim 1] A dual port memory comprising two ports capable of writing/reading from each port, with a microcomputer connected to one port, and a microcomputer connected to the other port of the dual port memory at predetermined time intervals. a data read control circuit that reads data from the dual port memory, the microcomputer processes data in synchronization with a synchronization signal from the data read control circuit, and writes the processed data to the dual port memory. In the read circuit, a temporary storage memory different from the dual port memory is connected to the CPU and the dual port memory, and the microcomputer writes processed data to the temporary storage memory each time data processing is completed; A data reading circuit characterized in that data written in the temporary storage memory is read out and written in the dual port memory in synchronization with the synchronization signal.