JPS60151770A - Data transferring system - Google Patents

Abstract

PURPOSE:To minimize queuing time of both sides by providing memories of exclusive use in the CPU side and each terminal side, and absorbing the difference of transfer data processing speed between the CPU and each terminal by making individuals to oprate at timing of their own. CONSTITUTION:Transferred data from the CPU are stored temporarily in a memory 2 for CPU writing, and then inputted successively to a parallel data series conversion circuit 3 according to data transfer sequence mentioned later through a data line (a), and parallel-series converted. Memories 4-1, 4-2...4-n for terminal reading store serial data output of the parallel data series conversion circuit 3 as it is, and transfer transfer data stored in memories 4-1, 4-2...4-n synchronizing them with clock of terminal side complying request from terminal side.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a data transfer circuit, and sometimes relates to a data transfer method using a memory, which is suitable as a data transfer means for a control device having a large number of terminals. It is something.

[Background of the invention]

Conventionally, in a data transfer system between a CPU (central processing unit) and a large number of terminals, each terminal has an individual data parallel-to-serial conversion circuit, and serial transfer is mainly performed. However, this method has the disadvantage that when transferring CPU data to a large number of terminals, the same number of parallel data-serial conversion circuits as the number of terminals are required, leading to an increase in the scale of the device. To resolve this,
A method has been devised to convert data sent to multiple terminals from parallel to serial in a time-sharing manner. However, when using this method, data is transferred by assigning a time slot to each terminal, so the CPU must output data in accordance with the time slot of each terminal.
There will be some restrictions depending on the data output operation of U or the state of the external terminal. Also, considering the terminal, data is transferred from the CPU in a time-division manner, so if the terminal processes the transferred data at a sufficiently fast speed, the data will be transferred until the next data is transferred. There are disadvantages such as the terminal being placed in a waiting state.

[Purpose of the invention]

The present invention attempts to eliminate such drawbacks of the prior art, and its purpose is to use a simple hardware configuration,
It is an object of the present invention to provide a data transfer circuit that absorbs the difference in transfer data processing speed between a CPU and each terminal and minimizes the waiting time of both.

[Summary of the invention]

In order to achieve this objective, the present invention has a system in which the CPU and /4r terminals operate asynchronously, and the data transfer between the CPU and each terminal Also, in order to prevent the operation timings of each terminal from interfering with each other, dedicated memories are provided on the CPU side and each terminal side, respectively, and each terminal 161 operates at its own timing.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 6.

FIG. 1 is a simplified overall configuration diagram of an embodiment of this data transfer method. In the figure, there are x6, 1 is the data input line from CPLT, 2 is CPU write memory,
6 is a parallel data serial conversion circuit, 4-1, 4-2, ・
..., 4-n is a memo for unread end +7.5-1
5-2. ..., 5-n are data output lines to each terminal. Transfer data from the CPU first passes through the data input line 1 and is input to the CPU memory 2. As long as this time memory 2 has the necessary and sufficient memory capacity, the CPU always uses the CPU according to its own data transfer sequence, regardless of the circumstances of the other party to which the data is transferred.
It is important for U to output data at the best timing, and this means that if the CPU sees the terminal, it is the same as the terminal receiving data at a sufficiently fast speed. Transfer data from the CPU is temporarily stored in the CPU write memory 2, and then sequentially input to the parallel data serial conversion circuit f45 through the data line α according to the data transfer sequence described later, where it is converted from parallel to serial. .

The serial data after conversion is stored in an end unread memory 411 corresponding to each data address as necessary.
4-z+..., 4-n are input through data line b. End unread memory 4-1, 4-
2, .
, 4-2, . . . , 4-n is transferred while being synchronized with the clock on the terminal side. Therefore, according to the present invention, there is no time slot restriction as seen in time-division data transfer systems, and each terminal uses CP according to its individual data transfer processing speed.
It is possible to receive transferred data regardless of the timing with the U or other terminals, and if you look at the CPU side from the terminal side, the transferred data is the same as being transferred in synchronization with its own clock. As a result, unnecessary waiting time caused by timing factors is eliminated.

FIG. 2 is an overall diagram of a data transfer sequence control circuit in one embodiment of the present invention. In the figure, 6 is an address decoder, 7 is a data selector control circuit, 8 and 9
is a data selector, and 10 is a counter. The CPU transfers data.

It passes through the data input line 1 and is input to the CPU ii' memory 2 according to the address decoded by the address C, read/write signal, and clock E. Further, the data select control circuit 7 issues an address for identifying data within the transfer circuit, and inputs it to the data selector 8 through the control signal line L together with a data write command to the CPU write memory 2. .

This signal passes through the data selector 8, the control signal line J, and is input to the memory as a CPU write memory 20 control signal together with the address signal H of the address decoder 6. On the other hand, the CPU adjusts the state of the CPU write memory 2 using the FULL code N to prevent data from being destroyed in an overflow state. The memory overflow is caused by the data transfer rate of the CPU,
This is determined by the relative relationship between the transfer data processing speeds of each terminal, and this can be easily avoided by changing the memory capacity settings. Further, the data selection control circuit 7
By signal M, memory dedicated to each terminal at all times, 4-1.4-
2. . . . 4-n is monitored, and if the memory is not in the FULL state, data corresponding to each terminal is sequentially read out from the CPU write memory 2 as well. In order to read data corresponding to each terminal from the CPU if reading memory 2, the data selector control side 1 circuit 7 issues a data identification address and a reading command within the data transfer circuit, and sends a control signal. The data is input to the data selector 8 through the line ■. The data selector 8 passes the same command through the control line J,
Transfer data input to the CPU programming memory 2 and output from the memory 2 is transferred via data lines a and K.
The parallel data is input to the serial conversion circuit 6. After the transfer data is converted into serial data by the same circuit 6, it passes through the serial data line L according to the address given from the data selector control circuit 7, and is sent to a dedicated terminal for each terminal corresponding to the address of each data via the data selector 9. Terminal reading memory 4-1.4-2. . . . is input to 4-n. Terminal reading memory 4-1, 4-2,...
. . , 4-n stores the input serial data as it is, and outputs the serial data to the output data line 5-1 in synchronization with the terminal clock according to each terminal's request. .5'-42+..., 5-
Output to n. In addition, the terminal read memo IJ 4-
1.4-2. . . . , 4-n is composed of, for example, a shift register. Terminal reading memo I7
4-1.4-2. ..., 4-n has four lines on the terminal side, respectively: output data line 5, EMPTY signal line P, clock signal line Q, and READ signal line R, and outputs serial data according to the terminal's request. Perform the transfer. The operation timing of the data transfer circuit will be explained below with reference to FIG.

FIG. 3 is an operation time chart of the terminal read memory. (a) is clock Q, C port) is EMPTY number P, (c) is 1 (mount signal R, (d) is data 5, (e) is FULLG, number M, (f) is memory 4- 1, 4-
2, -==, 4-n (7) Wl (ITE No. 1. In the same figure, (a) is the start-up operation of the terminal for normal transfer data. klF, tm 1m No. (c) teeth,
After detecting that EMPTY No. 1g is not always at the 11i level, a transfer data read command is issued and EMPTY No. 16 (c) is set to Hi level. data) is synchronized with the terminal side clock (a) and based on EMPTY No. 18 (b).
Start enclosing with A Hals. While data transfer is being performed, FULL is set to i level so that only data is written on data line b. When the series of data transfer is completed, IIIJEAD
No. 1a goes to LO level at the rising edge of the next pulse of EMPTY 1@ No. (b), and at the same time, FULL information (e) also goes to LO level, and the concave memories 4-1 and 4-2.

..., data writing to 4-n is permitted. Figure (1)) shows a case where the contents of the terminal read memory become empty immediately after reading data, and at this time F
A4PTY No. 18 maintains the IJi level and cancels READ No. 1 Bi→ from the terminal. The same figure (C1 is the terminal reading memo IJ 4-1.4-2...
. , 4-n is the writing timing of the transfer data. The data selector control circuit 7 is connected to the memory 4-1.4-
2.・・・・・・FULL M from 4-n is Lo
level, and control data selector 9 (
WRITE 1 = No. (to) Kaoru human power through M No. 0. IM (ITE fi number (to) is Hi level and No I
Then, the EMPTY signal (b) is output from data 1 after the rising edge of the pulse after that.
(Keep the IIi level until it reaches the LO level and cancel the Fu! AD signal (c) from the terminal. Memo for terminal reading +74-1.4-2.
・.

When data can be input to 4-n, CPU 1@IJ
Since the clock cycle of Leave it floating.

〔Effect of the invention〕

As explained above, the data transfer method of the present invention allows the CPU to communicate with a large number of terminals using a relatively simple circuit configuration.
The key is to minimize the waiting time for both the CPU and the terminal when transferring data. This reduces the time the CPU spends on data transfer, so the CPU
U can perform more processing than before in a unit time, and is extremely effective in speeding up the processing of a CPU that handles many terminals.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of an embodiment of the data transfer method of the present invention, FIG. 2 is an overall diagram of a data transfer sequence control circuit, and FIG. 6 is an operation time chart of a terminal read memory. . 1...Data input line, 2...Memory for CPU writing, 6...Parallel data 1-to-string conversion circuit, 4-1, 4-2,..., 4-n...Memory for terminal reading , 5-1 , 5-2 , ......, 5-
n...Data output line, 6...Address coater\7...Delta selector control circuit, 8...Data selector, 9...Data selector, agent patent attorney High
Akio Hashi

Claims (1)

[Claims] 1. In a data transfer circuit of a system consisting of a central processing unit and many terminals attached to it, a memory for writing by the central processing unit and a memory for end unreading are provided for each terminal individually, and the data transfer circuit is configured to read data according to the data read speed of each terminal. A circuit that selects and reads data corresponding to each terminal from among the data group inputted in advance into the central processing unit write memory, and a circuit that converts the read data into parallel and serial data, and after conversion, a circuit dedicated to each terminal. A data transfer method characterized by having a circuit for inputting data to an unread memory at the end.