JPS6232505B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to an instruction control device constituting a central processing unit of an information processing device, and particularly to instruction control in high-speed computers for science and technology that require high-speed processing. Regarding the control method of the device.

(b) Background of technology In the field of high-speed computers for science and technology, there is a strong demand for high-speed data processing, and speeding up is achieved by dividing parts of a series of processing that can be processed independently and processing them simultaneously in parallel. is being measured. For this reason, a plurality of instructions and a plurality of data to be processed by the instructions are stored, and depending on the state of the instruction processing device, a subsequent instruction in the program may be processed before a preceding instruction. In other words, it is an overtaking of commands. Therefore, it is necessary to hold a plurality of commands and data and control the order in which commands are issued and the order in which data processed by the commands are transmitted, and a countermeasure for this is desired.

(c) Purpose of the Invention Based on the above-mentioned request, the purpose of the present invention is to correctly transmit the data processed by the command when a certain command is issued, and to store the data in the memory circuit where the transmitted data was stored. It is an object of the present invention to provide a control method for an instruction control device that causes a unit to take in new data, and when each storage unit of the memory circuit becomes full, prevents the taking in of new instructions and data.

(d) Structure of the Invention The structure of the present invention is that a command control device constituting an information processing device includes a command transmission circuit that holds a plurality of commands, selects one of the commands, and transmits the selected command to the command processing device. , a storage circuit that holds data processed by each of the plurality of instructions, and a flag indicating that valid data is held for one or more storage units for each data unit of the storage circuit. , a flag control circuit that specifies a storage unit address for storing input data, and a preprocessing circuit that attaches the input specification to the data storage unit address specified by the flag control circuit and supplies it to the instruction issuing circuit. When the command transmission circuit transmits a command, the command transmission circuit sends the address back to the flag control circuit, and the flag control circuit transmits the address to the storage circuit and turns off the flag corresponding to the address. The system allows new data to be taken into the memory unit of the memory circuit corresponding to the flag, and when all flags are turned on, the new command and the data processed by the command are prohibited from being taken in. be.

(e) Embodiment of the Invention FIG. 1 is a block diagram of a circuit showing an embodiment of the invention. Figure 2 shows the flag control circuit 2 in Figure 1.
FIG. 2 is a detailed diagram of No. 2. This embodiment shows a case where two pieces of data are input for every command. Buffer 11 from an external device such as an external storage device via terminal A
Information is entered and held in the order of instructions, first data, and second data. Information is extracted from the buffer 11 in the order of instructions, first data, and second data, and the clock
CLo, CL _DF , and CL _DS are turned on in sequence, and the instruction is set in the register 12. When the clock CLo turns on, the flag control circuit 22 is set in the register 13.
The data address sent out via the signal line 26 is then set. Buffer 11, register 12, and register 13 constitute a preprocessing circuit. 1st
Data is set in register 23 at the address indicated by register 13 when clock _{CL_DF} is turned on, and second data is set in register 24 at the address indicated by register 13 when clock _{CL_DS} is turned on. At this time, the flag control circuit 22 sets in the register 13 one of the addresses whose flags in the registers 23 and 24 are turned off. In this embodiment, the number of registers for setting instructions is 4, so 2 registers are used to store data.
The number of storage units for 3 and 24 is 4, respectively, and there are 4 types of addresses: 0, 1, 2, and 3. It is also assumed that all data input for each instruction can be set in one storage unit. Therefore, register 13 is the clock
When CL _DF and CL _DS are turned on, registers 23 and 2
4 write address is specified.

Registers 14, 15, 16, 17, 18, 19
and selectors 20 and 21 constitute a command transmission circuit,
If any of registers 14, 16, and 18 is reset, for example, register 18 is reset, clock _CL3 is turned on, takes in the instruction in register 12, and reads register 19.
takes in the address of register 13. register 1
When the clock CL1 is reset, the clock _CL1 is turned on, an instruction is set in the register 14, and an address of data to be processed by the instruction is set in the register 15. If the register 16 is reset at the same time, the clock _CL2 is turned on, the instruction is set in the register 16, and the address of the data to be processed by the instruction is set in the register 17.

Selector 20 selects register 1 by selection signal SEL.
If one of registers 4, 16, and 18 is selected, for example, register 18, the instruction set in register 18 is sent from terminal B to the instruction processing device. Register 18 is reset upon sending an instruction. At this time, the selector 21 selects the register 19 by the selection signal SEL and sends the addresses of the registers 23 and 24 storing data to be processed by the instruction processing device to the flag control circuit 22 via the signal line 25 according to the instruction. , the flag control circuit 22 sends the address to the registers 23 and 24 via the signal line 27.
The address is sent to the register 23 and 24 and used as the read address. The data read from registers 23 and 24 are sent to the instruction processing device from terminals C and D, respectively. The selection signal SEL determines the command to be sent from the command processing device, the context of the command, etc., and selector 2
The registers that hold the instructions corresponding to numbers 0 and 21 and the addresses of the data processed by the instructions are selected as described above, but the description of the selection signal SEL generation circuit is omitted since it has no direct relation to the present invention.

Next, the flag control circuit 22 will be explained. Second
In the figure, the address sent from the selector 21 via the signal line 25 is once latched in the register 54 and then sent out via the signal line 27. register 2
3 and 24 are 2 because there are 4 types of addresses as mentioned above.
It can be displayed in bits. For example, if the address 0 is specified when the value is "00", the outputs of the NOT circuits 30 and 31 will be "1" and the AND circuit 32 will be "1". If you specify address 1 when “01”
The AND circuit 33 becomes "1". If address 2 is specified when the value is “10”, the AND circuit 34 is “1”
becomes. If you specify address 3 when it is “11”, AND
The circuit 35 becomes "1".

Flip-flop (hereinafter abbreviated as FF) 44,4
When set, 5, 46, and 47 indicate that the data at addresses 0 to 3 of registers 23 and 24 are valid, and when reset,
This is a flag indicating that the data at the corresponding address has already been sent to the instruction control device and new data can be used as invalid data. In the initial state, FF4
The terminals Q of 4 to 47 are all "0" and the terminals are "1". Therefore, AND circuits 48, 49, 5
0 and 51 are all “0” and OR circuits 52 and 5
3 is also "0", and the address "00" is sent to the signal line 26. When the set flag signal is input from terminal E, the AND circuit 36 becomes "1" and the FF44
is set. Therefore, the AND circuit 48 is “1”
Therefore, the address “01” is sent to the signal line 26. Next, when the set flag signal is input, the AND circuit 38 becomes "1" and the FF 45 is set.
The output of the AND circuit 49 becomes "1". At this time
The AND circuit 48 becomes "0" because the terminal of the FF 45 becomes "0". Therefore, the address "10" is sent to the signal line 26. Next, when the set flag signal is input, the AND circuit 40 becomes "1", the FF 46 is set, the AND circuit 50 becomes "1", and the address "11" is sent to the signal line 26. When the set flag signal is further input, the AND circuit 42 becomes “1”.
Then, the FF 47 is set, the AND circuit 51 becomes "1", and a busy signal is sent from the terminal G, prohibiting the acquisition of a new command and the data processed by the command.

When a start instruction signal is input from terminal F to send a command, if the address "10" is input to the signal line 25, then the AND signal is output as described above.
Since the circuit 34 becomes "1", the AND circuit 41 becomes "1" and the FF 46 is reset. accordingly
AND circuits 51 and 50 become "0", and signal line 2
Address “10” is sent to 6, and a new instruction and the data to be processed by the instruction are taken in.
The data is stored at address 2 of registers 23 and 24. Similarly, each time a start instruction signal is applied, the FF corresponding to the address input from the signal line 25 is reset. That is, when the address is "00", the AND circuit 37 becomes "1" and the FF 44 is set, and when the address is "01", the AND circuit 37 becomes "1"
The AND circuit 39 becomes "1" and the FF 45 becomes "1", and when the address is "11", the AND circuit 43 becomes "1",
Reset each FF47. Since the reset FF address is sent to the signal line 26,
New data is stored in the registers 23 and 24 in place of the invalid data that was sent to the instruction processing device.

In this embodiment, the case where the number of data to be processed for an instruction is constant has been explained, but if the number of data to be processed is different, all flags at consecutive addresses for the number of data from a certain address in the registers 23 and 24 are address register 13,
A plurality of numbers 15, 17, and 19 may be used.

(f) Effects of the Invention As explained above, the present invention can control the order of issuing instructions and the order of sending data processed by the instructions in order to overtake instructions in high-speed computers for science and technology. There is something big.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention, and FIG. 2 is a detailed diagram of the flag control circuit of FIG. 11 is batshua, 12, 13, 14, 15, 1
6, 17, 18, 19, 23, 24 are registers,
20 and 21 are selectors, 22 is a flag control circuit,
44, 45, 46, 47 are flip-flops, 5
4 is a register.

Claims (1)

[Scope of Claims] 1. In a command processing device constituting an information processing device, a command issuing circuit that holds a plurality of commands and selects and transmits one of the plurality of commands; A storage circuit that holds data processed by each, and a flag indicating that valid data is held for one or more storage units for each data unit of the storage circuit, and input data are controlled. a flag control circuit for specifying an address of a storage unit to be stored; and a preprocessing circuit for providing an input instruction with a data storage unit address specified by the flag control circuit to the instruction generation circuit; When transmitting a command, the controller sends the address back to the flag control circuit, and the flag control circuit sends the address to the storage circuit and turns off the flag corresponding to the address. A control method for an instruction control device. 2. In the above-mentioned instruction control device, when fetching data to be processed by an instruction, the data is not necessarily stored in the address order of the storage unit of the storage circuit, but is stored in the storage unit whose flag is turned off. 2. A control method for an instruction control device according to claim 1, wherein: 3 In the above instruction control device, all flags are set to
The instruction control device according to claim 1, wherein when the instruction control device is turned on or is predicted to be turned on, import of a new instruction and data processed by the instruction is prohibited. control method.