JPS5882357A - Interprocessor communication system - Google Patents

Abstract

PURPOSE:To perform information transfer among plural processors which do not use a memory in common through simple constitution, by executing an instruction group stored in the memory of a global processor at specified intevals of time. CONSTITUTION:In the system wherein local processors 12 and 13 use their own memories 15 and 16 in common with only a global processor 14, instructions A and B for transfer between the processors 12 and 13 are set up in the memory 30 of the processor 14, and are selected by an external clock. Further, a communication area between the processor 12 and 13 is transferred, clock by clock, in predetermined order, and the processors 12 and 13 are inhibited from accessing the communication area between the processors 12 and 13 until the transfer ends, thereby outputting access permit signals from the processors 12 and 13.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inter-processor communication system, and particularly relates to an information transmission system between processors that do not share memory with each other.

Conventionally, as shown in FIG. 1, for example, in a system consisting of two local processors 2 and 3 and a global processor l that supervises them, each p-carb p processor (2), CB) 2.3 has If the memories 5 and 6 are shared by the Guta-Pal processor l, and the local processors (A) and ω) 2 and 3 do not share the memory with each other, the local 7'o Nanatsusa (4) ,03)2
．． In order to communicate between the local processors (A) and CB) 2 and 3, it was necessary to provide a register 7 between them. When the local processor (A) 2 reads or writes the register 7, the local processor (5) 2 outputs a signal 10 indicating that the register 7 is being accessed, and the gate 9 causes the local processor (B) 3 to read or write the register 7. When the local processor (3) 2 completes reading or writing, the signal IO is released and the local processor (3) is allowed to access the register 7. Conversely, when local processor (A) 3 reads or writes register 7, it outputs signal 11 and prohibits local processor (A) 2 from accessing register 7 through gate 8, and then reads or writes to register 7. After the process was completed, the signal 11 was released and the original state returned.

As mentioned above, in the conventional system, communication between local processors is performed by using registers provided between the local processors, so when the number of local processors becomes three or more, the above-mentioned The control for prohibiting access has become complicated, and it has become necessary to increase the capacity or number of the registers.

゛Also, when sending and receiving a large amount of fragmented data many times via the register, one local processor will have V of the register, and other local processors will have to wait until the register becomes free. There was also the problem of having to manage priority rights.

In order to solve such four sets, instead of providing registers as described above between the four processors, an inter-local processor communication area is provided in the memory of each local processor, and this is transferred to the global processor. It is also possible to do so, but for this,
There were the following problems. That is, if a local processor attempting to write data to the above-mentioned local inter-processor communication area and a global processor attempting to transfer it access the same area at the same time, the data may be destroyed.

The present invention has been made in view of the above circumstances, and its purpose is to eliminate the above-mentioned problems of the conventional inter-processor communication method, and to enable communication between a large number of processors that do not share memory with each other with a simple configuration. An object of the present invention is to provide an inter-processor communication method that enables information transmission between processors.

The above object of the present invention is to consist of a plurality of local processors and a global processor that supervises them, the memory of each of the plurality of local processors is shared with the global processor, and the local processors share mutual memory. In a system configured not to share information, a group of transfer instructions is prepared in the memory of the global processor, and information is transmitted between the local processors by executing the group of instructions at fixed time intervals. This is achieved through communication methods.

The gist of the present invention is that, in the above system, a local processor transfer instruction is prepared in the global processor, this is selected by an external clock, and the transfer is performed every clock in the determined order of each local processor communication area. The access permission signal is provided so that each local processor, even the local processor r+, cannot access the communication area until the transfer is completed.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, but is a block diagram for communication between p-cal processors, and FIG. 3 is a time chart thereof.

Figure 2 shows the local processor (4) @12.13'
In a system consisting of a global processor 14 and a global processor 14, local processor communication areas 17.18 and 19.20 of the memory 15.16 of the local processor (4), Q3) 12.13 are used to perform local processor communication. conduct.

The clock generator 21 starts operating when the power is turned on, and
It generates a logical value, which is initially "0" and thereafter repeats "l" and "0" at regular time intervals until the power is turned off.

While the signal from the gate 26 is "0", the local processor (4) 12 cannot access the LPB information 18, which is an area in its own memory 15 that receives information from the local processor (4) 13. However, other areas in the local memory 15 can always be referenced.The I, PA information 17 in the memory 15 is
This is an area for storing information to be transmitted to local processor Q3 by transfer command A of global processor 14.
) 13 is forwarded to LPA'11 Report 19.

Similarly, while the signal from the gate 2σ is “1 o +”, the local processor @13 uses the LP in its own memory 16.
Although the A information 19 cannot be accessed, other areas within the own memory 16 can always be referenced. The LPE information 20 in the memory 16 is stored in the local processor (to) 1.
This area stores information to be transmitted to the local processor (A
) 12 is transferred to the LPB'ill report 16.

The operation of the apparatus of this embodiment configured as described above will be explained below.

When the clock signal 21A changes from "0" to 1, the transfer instruction A address 22 is selected by the gate 24 and set in the program counter 27, and the transfer instruction A is executed. This is an instruction to transfer to the LPA information 19. At this time, since the signal 27A sent from the program counter 27 is "0" until the end of the transfer, the outputs of the game) 28 and 29 are both "0", and the output of the local processor (4) is "0". )12 is LPB information 1
8, local processor CB) 13 is LPA information 19
cannot be accessed. This corresponds to the range marked ■ in FIG.

When the transfer is completed, the signal 27A sent from the program counter 27 becomes 1''', so the output of the gate 29 becomes "1", and the local processor CB) 13 becomes L.
Although the PA information 19 will be accessible, the local processor (A) 1.2 will also be able to access the LPB information 1.
δ cannot be accessed. This corresponds to the range marked ■ in FIG.

Next, when the clock signal 2LA changes from 1.1'' to 0, the transfer instruction B address 23 is selected by the game 25 and set in the program counter 27, and the transfer instruction B is executed. is an instruction to transfer LPE information @20 to LPB information @18. Until the transfer is completed, the outputs of gate 2829 are both "0'", so local processors (A) 12 and 13 are fidgety. It is not possible to access the LPE information 18 and LPA'1llt 19, respectively.This corresponds to the range (■) in FIG.

When the transfer is completed, the output of the gate 28 becomes 1, allowing the local processor (A) 12 to access the LPB information 18. This corresponds to the range marked ■ in FIG.

Thereafter, transfer instructions are similarly executed using the clock signal 21A, and the local processors (A) l 2 and (B) 13
Transmit information between. In addition, in FIG. 3, 12A is the access permission signal of the local processor prisoner 12, and 13A is the access permission signal of the local processor prisoner 12.
A indicates the same access permission signal of 15.

In the above embodiment, in 43 cases, information is transmitted between 20!11 local processors? As shown, even if there are 13 or more failed local processors, inter-processor communication can be easily performed by adding a transfer command 2 and a counter that counts clocks.

1. If multiple transfers are performed in one clock cycle, the transfer cycle of the communication area between local processors becomes shorter, and the communication speed between local processors can be improved.

As described above, according to the present invention, the present invention includes a plurality of rotary processors and a global processor that supervises them, and the memory of each of the plurality of local processors is shared only with the global processor, In a system configured such that the local processors do not share information with each other, information between the local processors is transferred by preparing a group of transfer instructions in the memory of the global processor and executing the group of instructions at fixed time intervals. Since communication is performed, it is possible to transfer information between multiple processors that do not share memory with each other with a simple configuration, and even when the number of local processors that make up the Samurai system increases, it is possible to deal with 84. This has the remarkable effect of realizing a reliable inter-processor communication system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional system, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a time chart showing its operation. 12: Local processor (4), 13: Local processor CB), 14-Nigelobal processor, 15° 16: Local processor memory, 17.19: LP
A information, 18.20: LPB information, 218 clock generator, 22, 23: Transfer instruction address, 24.25,
26, 28, 29: Gate, 27: Program counter, 30: Main memory, 12A, 13A: 0-cal processor access permission number i, 21A: Clock signal, 2
7A: Transfer end signal. Patent applicant: Hitachi, Ltd. ['r '−゛? ' Figure 1 Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] It consists of a plurality of local processors that share functions, and a global processor that supervises them and performs a series of operations.The memory of each of the plurality of local processors is shared only with the global processor, and the local processors share the memory with each other. In a system configured so as not to be shared, information is transmitted between the local processors by preparing a group of transfer instructions in the memory of the global processor and executing the group of instructions at fixed time intervals. Inter-processor communication method.